public inbox for binutils@sourceware.org
 help / color / mirror / Atom feed
* [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
@ 2022-09-22  6:32 Tsukasa OI
  2022-09-22  6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
                   ` (2 more replies)
  0 siblings, 3 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-09-22  6:32 UTC (permalink / raw)
  To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils

Hello,

Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
ratified yet but at least frozen.  So, I consider it's stable to upstream
it.  According to the documentation, it has register numbers 96 (v0) -
127 (v31).

[Changes: v1 -> v2]
Remove invented word "VPRs" (at least it has no consistent uses in the
RISC-V ecosystem) and replaced with "Vector registers"

[Changes: v2 -> v3]
Changed reference (v1.0-rc3 -> v1.0-rc4).

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>

RISC-V ABIs Specification Version 1.0-rc4: Frozen
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>


I also added DWARF register number tests not just for CSRs (existing) and
vector registers (I just added), but also for GPRs (0-31) and FPRs (32-63).


Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Assign DWARF numbers to vector registers
  RISC-V: Add testcase for DWARF register numbers

 binutils/dwarf.c                     |  28 ++--
 gas/config/tc-riscv.c                |   3 +
 gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++
 4 files changed, 385 insertions(+), 10 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s


base-commit: 90eca7111355e4c6683c1ab10fd07107ea10f6d1
-- 
2.34.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 1/2] RISC-V: Assign DWARF numbers to vector registers
  2022-09-22  6:32 [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Tsukasa OI
@ 2022-09-22  6:32 ` Tsukasa OI
  2022-09-22  6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
  2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
  2 siblings, 0 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-09-22  6:32 UTC (permalink / raw)
  To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils

This commit is to comply RISC-V DWARF Specification version 1.0-rc4
(in the frozen state):

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4

binutils/ChangeLog:

	* dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers
	96..127 to vector registers v0-v31.

gas/ChangeLog:

	* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support
	vector registers.
---
 binutils/dwarf.c      | 28 ++++++++++++++++++----------
 gas/config/tc-riscv.c |  3 +++
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/binutils/dwarf.c b/binutils/dwarf.c
index aef0f77eab6..c6340a28906 100644
--- a/binutils/dwarf.c
+++ b/binutils/dwarf.c
@@ -8540,16 +8540,24 @@ init_dwarf_regnames_s390 (void)
 
 static const char *const dwarf_regnames_riscv[] =
 {
- "zero", "ra",   "sp",   "gp",  "tp",  "t0",  "t1",  "t2",  /* 0  - 7 */
- "s0",   "s1",   "a0",   "a1",  "a2",  "a3",  "a4",  "a5",  /* 8  - 15 */
- "a6",   "a7",   "s2",   "s3",  "s4",  "s5",  "s6",  "s7",  /* 16 - 23 */
- "s8",   "s9",   "s10",  "s11", "t3",  "t4",  "t5",  "t6",  /* 24 - 31 */
- "ft0",  "ft1",  "ft2",  "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */
- "fs0",  "fs1",                                             /* 40 - 41 */
- "fa0",  "fa1",  "fa2",  "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */
- "fs2",  "fs3",  "fs4",  "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */
- "fs10", "fs11",                                            /* 58 - 59 */
- "ft8",  "ft9",  "ft10", "ft11"                             /* 60 - 63 */
+ "zero", "ra",   "sp",   "gp",  "tp",  "t0",  "t1",  "t2",  /*   0 -   7 */
+ "s0",   "s1",   "a0",   "a1",  "a2",  "a3",  "a4",  "a5",  /*   8 -  15 */
+ "a6",   "a7",   "s2",   "s3",  "s4",  "s5",  "s6",  "s7",  /*  16 -  23 */
+ "s8",   "s9",   "s10",  "s11", "t3",  "t4",  "t5",  "t6",  /*  24 -  31 */
+ "ft0",  "ft1",  "ft2",  "ft3", "ft4", "ft5", "ft6", "ft7", /*  32 -  39 */
+ "fs0",  "fs1",                                             /*  40 -  41 */
+ "fa0",  "fa1",  "fa2",  "fa3", "fa4", "fa5", "fa6", "fa7", /*  42 -  49 */
+ "fs2",  "fs3",  "fs4",  "fs5", "fs6", "fs7", "fs8", "fs9", /*  50 -  57 */
+ "fs10", "fs11",                                            /*  58 -  59 */
+ "ft8",  "ft9",  "ft10", "ft11",                            /*  60 -  63 */
+ NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,     /*  64 -  71 */
+ NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,     /*  72 -  79 */
+ NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,     /*  80 -  87 */
+ NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,  NULL,     /*  88 -  95 */
+ "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",     /*  96 - 103 */
+ "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",    /* 104 - 111 */
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",    /* 112 - 119 */
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",    /* 120 - 127 */
 };
 
 /* A RISC-V replacement for REGNAME_INTERNAL_BY_TABLE_ONLY which handles
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5411d68a401..bc36625311a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -4319,6 +4319,9 @@ tc_riscv_regname_to_dw2regnum (char *regname)
   if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0)
     return reg + 32;
 
+  if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0)
+    return reg + 96;
+
   /* CSRs are numbered 4096 -> 8191.  */
   if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0)
     return reg + 4096;
-- 
2.34.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers
  2022-09-22  6:32 [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Tsukasa OI
  2022-09-22  6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
@ 2022-09-22  6:32 ` Tsukasa OI
  2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
  2 siblings, 0 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-09-22  6:32 UTC (permalink / raw)
  To: Tsukasa OI, Nelson Chu, Kito Cheng, Palmer Dabbelt; +Cc: binutils

Although it had csr-dw-regnums.d (for CSRs), it didn't have DWARF register
number test for GPRs/FPRs/vector registers.

This commit adds dw-regnums.{s,d} to test such registers.

gas/ChangeLog:

	* testsuite/gas/riscv/dw-regnums.s: New DWARF register number test
	for GPRs/FPRs/vector registers.
	* testsuite/gas/riscv/dw-regnums.d: New test.
---
 gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++
 gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++
 2 files changed, 364 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
 create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s

diff --git a/gas/testsuite/gas/riscv/dw-regnums.d b/gas/testsuite/gas/riscv/dw-regnums.d
new file mode 100644
index 00000000000..5ec61b98697
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dw-regnums.d
@@ -0,0 +1,180 @@
+#as: -march=rv32iv
+#objdump: --dwarf=frames
+
+
+.*:     file format elf.*-.*riscv
+
+Contents of the .* section:
+
+
+00000000 [a-zA-Z0-9]+ [a-zA-Z0-9]+ CIE
+  Version:               .*
+  Augmentation:          .*
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     .*
+#...
+[a-zA-Z0-9]+ [a-zA-Z0-9]+ [a-zA-Z0-9]+ FDE cie=00000000 pc=[a-zA-Z0-9]+\.\.[a-zA-Z0-9]+
+  DW_CFA_advance_loc: 4 to 0+0000020
+  DW_CFA_offset_extended_sf: r0 \(zero\) at cfa\+4
+  DW_CFA_offset_extended_sf: r1 \(ra\) at cfa\+8
+  DW_CFA_offset_extended_sf: r2 \(sp\) at cfa\+12
+  DW_CFA_offset_extended_sf: r3 \(gp\) at cfa\+16
+  DW_CFA_offset_extended_sf: r4 \(tp\) at cfa\+20
+  DW_CFA_offset_extended_sf: r5 \(t0\) at cfa\+24
+  DW_CFA_offset_extended_sf: r6 \(t1\) at cfa\+28
+  DW_CFA_offset_extended_sf: r7 \(t2\) at cfa\+32
+  DW_CFA_offset_extended_sf: r8 \(s0\) at cfa\+36
+  DW_CFA_offset_extended_sf: r9 \(s1\) at cfa\+40
+  DW_CFA_offset_extended_sf: r10 \(a0\) at cfa\+44
+  DW_CFA_offset_extended_sf: r11 \(a1\) at cfa\+48
+  DW_CFA_offset_extended_sf: r12 \(a2\) at cfa\+52
+  DW_CFA_offset_extended_sf: r13 \(a3\) at cfa\+56
+  DW_CFA_offset_extended_sf: r14 \(a4\) at cfa\+60
+  DW_CFA_offset_extended_sf: r15 \(a5\) at cfa\+64
+  DW_CFA_offset_extended_sf: r16 \(a6\) at cfa\+68
+  DW_CFA_offset_extended_sf: r17 \(a7\) at cfa\+72
+  DW_CFA_offset_extended_sf: r18 \(s2\) at cfa\+76
+  DW_CFA_offset_extended_sf: r19 \(s3\) at cfa\+80
+  DW_CFA_offset_extended_sf: r20 \(s4\) at cfa\+84
+  DW_CFA_offset_extended_sf: r21 \(s5\) at cfa\+88
+  DW_CFA_offset_extended_sf: r22 \(s6\) at cfa\+92
+  DW_CFA_offset_extended_sf: r23 \(s7\) at cfa\+96
+  DW_CFA_offset_extended_sf: r24 \(s8\) at cfa\+100
+  DW_CFA_offset_extended_sf: r25 \(s9\) at cfa\+104
+  DW_CFA_offset_extended_sf: r26 \(s10\) at cfa\+108
+  DW_CFA_offset_extended_sf: r27 \(s11\) at cfa\+112
+  DW_CFA_offset_extended_sf: r28 \(t3\) at cfa\+116
+  DW_CFA_offset_extended_sf: r29 \(t4\) at cfa\+120
+  DW_CFA_offset_extended_sf: r30 \(t5\) at cfa\+124
+  DW_CFA_offset_extended_sf: r31 \(t6\) at cfa\+128
+  DW_CFA_offset_extended_sf: r0 \(zero\) at cfa\+4
+  DW_CFA_offset_extended_sf: r1 \(ra\) at cfa\+8
+  DW_CFA_offset_extended_sf: r2 \(sp\) at cfa\+12
+  DW_CFA_offset_extended_sf: r3 \(gp\) at cfa\+16
+  DW_CFA_offset_extended_sf: r4 \(tp\) at cfa\+20
+  DW_CFA_offset_extended_sf: r5 \(t0\) at cfa\+24
+  DW_CFA_offset_extended_sf: r6 \(t1\) at cfa\+28
+  DW_CFA_offset_extended_sf: r7 \(t2\) at cfa\+32
+  DW_CFA_offset_extended_sf: r8 \(s0\) at cfa\+36
+  DW_CFA_offset_extended_sf: r9 \(s1\) at cfa\+40
+  DW_CFA_offset_extended_sf: r10 \(a0\) at cfa\+44
+  DW_CFA_offset_extended_sf: r11 \(a1\) at cfa\+48
+  DW_CFA_offset_extended_sf: r12 \(a2\) at cfa\+52
+  DW_CFA_offset_extended_sf: r13 \(a3\) at cfa\+56
+  DW_CFA_offset_extended_sf: r14 \(a4\) at cfa\+60
+  DW_CFA_offset_extended_sf: r15 \(a5\) at cfa\+64
+  DW_CFA_offset_extended_sf: r16 \(a6\) at cfa\+68
+  DW_CFA_offset_extended_sf: r17 \(a7\) at cfa\+72
+  DW_CFA_offset_extended_sf: r18 \(s2\) at cfa\+76
+  DW_CFA_offset_extended_sf: r19 \(s3\) at cfa\+80
+  DW_CFA_offset_extended_sf: r20 \(s4\) at cfa\+84
+  DW_CFA_offset_extended_sf: r21 \(s5\) at cfa\+88
+  DW_CFA_offset_extended_sf: r22 \(s6\) at cfa\+92
+  DW_CFA_offset_extended_sf: r23 \(s7\) at cfa\+96
+  DW_CFA_offset_extended_sf: r24 \(s8\) at cfa\+100
+  DW_CFA_offset_extended_sf: r25 \(s9\) at cfa\+104
+  DW_CFA_offset_extended_sf: r26 \(s10\) at cfa\+108
+  DW_CFA_offset_extended_sf: r27 \(s11\) at cfa\+112
+  DW_CFA_offset_extended_sf: r28 \(t3\) at cfa\+116
+  DW_CFA_offset_extended_sf: r29 \(t4\) at cfa\+120
+  DW_CFA_offset_extended_sf: r30 \(t5\) at cfa\+124
+  DW_CFA_offset_extended_sf: r31 \(t6\) at cfa\+128
+  DW_CFA_offset_extended_sf: r32 \(ft0\) at cfa\+132
+  DW_CFA_offset_extended_sf: r33 \(ft1\) at cfa\+136
+  DW_CFA_offset_extended_sf: r34 \(ft2\) at cfa\+140
+  DW_CFA_offset_extended_sf: r35 \(ft3\) at cfa\+144
+  DW_CFA_offset_extended_sf: r36 \(ft4\) at cfa\+148
+  DW_CFA_offset_extended_sf: r37 \(ft5\) at cfa\+152
+  DW_CFA_offset_extended_sf: r38 \(ft6\) at cfa\+156
+  DW_CFA_offset_extended_sf: r39 \(ft7\) at cfa\+160
+  DW_CFA_offset_extended_sf: r40 \(fs0\) at cfa\+164
+  DW_CFA_offset_extended_sf: r41 \(fs1\) at cfa\+168
+  DW_CFA_offset_extended_sf: r42 \(fa0\) at cfa\+172
+  DW_CFA_offset_extended_sf: r43 \(fa1\) at cfa\+176
+  DW_CFA_offset_extended_sf: r44 \(fa2\) at cfa\+180
+  DW_CFA_offset_extended_sf: r45 \(fa3\) at cfa\+184
+  DW_CFA_offset_extended_sf: r46 \(fa4\) at cfa\+188
+  DW_CFA_offset_extended_sf: r47 \(fa5\) at cfa\+192
+  DW_CFA_offset_extended_sf: r48 \(fa6\) at cfa\+196
+  DW_CFA_offset_extended_sf: r49 \(fa7\) at cfa\+200
+  DW_CFA_offset_extended_sf: r50 \(fs2\) at cfa\+204
+  DW_CFA_offset_extended_sf: r51 \(fs3\) at cfa\+208
+  DW_CFA_offset_extended_sf: r52 \(fs4\) at cfa\+212
+  DW_CFA_offset_extended_sf: r53 \(fs5\) at cfa\+216
+  DW_CFA_offset_extended_sf: r54 \(fs6\) at cfa\+220
+  DW_CFA_offset_extended_sf: r55 \(fs7\) at cfa\+224
+  DW_CFA_offset_extended_sf: r56 \(fs8\) at cfa\+228
+  DW_CFA_offset_extended_sf: r57 \(fs9\) at cfa\+232
+  DW_CFA_offset_extended_sf: r58 \(fs10\) at cfa\+236
+  DW_CFA_offset_extended_sf: r59 \(fs11\) at cfa\+240
+  DW_CFA_offset_extended_sf: r60 \(ft8\) at cfa\+244
+  DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248
+  DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252
+  DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256
+  DW_CFA_offset_extended_sf: r32 \(ft0\) at cfa\+132
+  DW_CFA_offset_extended_sf: r33 \(ft1\) at cfa\+136
+  DW_CFA_offset_extended_sf: r34 \(ft2\) at cfa\+140
+  DW_CFA_offset_extended_sf: r35 \(ft3\) at cfa\+144
+  DW_CFA_offset_extended_sf: r36 \(ft4\) at cfa\+148
+  DW_CFA_offset_extended_sf: r37 \(ft5\) at cfa\+152
+  DW_CFA_offset_extended_sf: r38 \(ft6\) at cfa\+156
+  DW_CFA_offset_extended_sf: r39 \(ft7\) at cfa\+160
+  DW_CFA_offset_extended_sf: r40 \(fs0\) at cfa\+164
+  DW_CFA_offset_extended_sf: r41 \(fs1\) at cfa\+168
+  DW_CFA_offset_extended_sf: r42 \(fa0\) at cfa\+172
+  DW_CFA_offset_extended_sf: r43 \(fa1\) at cfa\+176
+  DW_CFA_offset_extended_sf: r44 \(fa2\) at cfa\+180
+  DW_CFA_offset_extended_sf: r45 \(fa3\) at cfa\+184
+  DW_CFA_offset_extended_sf: r46 \(fa4\) at cfa\+188
+  DW_CFA_offset_extended_sf: r47 \(fa5\) at cfa\+192
+  DW_CFA_offset_extended_sf: r48 \(fa6\) at cfa\+196
+  DW_CFA_offset_extended_sf: r49 \(fa7\) at cfa\+200
+  DW_CFA_offset_extended_sf: r50 \(fs2\) at cfa\+204
+  DW_CFA_offset_extended_sf: r51 \(fs3\) at cfa\+208
+  DW_CFA_offset_extended_sf: r52 \(fs4\) at cfa\+212
+  DW_CFA_offset_extended_sf: r53 \(fs5\) at cfa\+216
+  DW_CFA_offset_extended_sf: r54 \(fs6\) at cfa\+220
+  DW_CFA_offset_extended_sf: r55 \(fs7\) at cfa\+224
+  DW_CFA_offset_extended_sf: r56 \(fs8\) at cfa\+228
+  DW_CFA_offset_extended_sf: r57 \(fs9\) at cfa\+232
+  DW_CFA_offset_extended_sf: r58 \(fs10\) at cfa\+236
+  DW_CFA_offset_extended_sf: r59 \(fs11\) at cfa\+240
+  DW_CFA_offset_extended_sf: r60 \(ft8\) at cfa\+244
+  DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248
+  DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252
+  DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256
+  DW_CFA_offset_extended_sf: r96 \(v0\) at cfa\+388
+  DW_CFA_offset_extended_sf: r97 \(v1\) at cfa\+392
+  DW_CFA_offset_extended_sf: r98 \(v2\) at cfa\+396
+  DW_CFA_offset_extended_sf: r99 \(v3\) at cfa\+400
+  DW_CFA_offset_extended_sf: r100 \(v4\) at cfa\+404
+  DW_CFA_offset_extended_sf: r101 \(v5\) at cfa\+408
+  DW_CFA_offset_extended_sf: r102 \(v6\) at cfa\+412
+  DW_CFA_offset_extended_sf: r103 \(v7\) at cfa\+416
+  DW_CFA_offset_extended_sf: r104 \(v8\) at cfa\+420
+  DW_CFA_offset_extended_sf: r105 \(v9\) at cfa\+424
+  DW_CFA_offset_extended_sf: r106 \(v10\) at cfa\+428
+  DW_CFA_offset_extended_sf: r107 \(v11\) at cfa\+432
+  DW_CFA_offset_extended_sf: r108 \(v12\) at cfa\+436
+  DW_CFA_offset_extended_sf: r109 \(v13\) at cfa\+440
+  DW_CFA_offset_extended_sf: r110 \(v14\) at cfa\+444
+  DW_CFA_offset_extended_sf: r111 \(v15\) at cfa\+448
+  DW_CFA_offset_extended_sf: r112 \(v16\) at cfa\+452
+  DW_CFA_offset_extended_sf: r113 \(v17\) at cfa\+456
+  DW_CFA_offset_extended_sf: r114 \(v18\) at cfa\+460
+  DW_CFA_offset_extended_sf: r115 \(v19\) at cfa\+464
+  DW_CFA_offset_extended_sf: r116 \(v20\) at cfa\+468
+  DW_CFA_offset_extended_sf: r117 \(v21\) at cfa\+472
+  DW_CFA_offset_extended_sf: r118 \(v22\) at cfa\+476
+  DW_CFA_offset_extended_sf: r119 \(v23\) at cfa\+480
+  DW_CFA_offset_extended_sf: r120 \(v24\) at cfa\+484
+  DW_CFA_offset_extended_sf: r121 \(v25\) at cfa\+488
+  DW_CFA_offset_extended_sf: r122 \(v26\) at cfa\+492
+  DW_CFA_offset_extended_sf: r123 \(v27\) at cfa\+496
+  DW_CFA_offset_extended_sf: r124 \(v28\) at cfa\+500
+  DW_CFA_offset_extended_sf: r125 \(v29\) at cfa\+504
+  DW_CFA_offset_extended_sf: r126 \(v30\) at cfa\+508
+  DW_CFA_offset_extended_sf: r127 \(v31\) at cfa\+512
+#...
diff --git a/gas/testsuite/gas/riscv/dw-regnums.s b/gas/testsuite/gas/riscv/dw-regnums.s
new file mode 100644
index 00000000000..bbe1b13d894
--- /dev/null
+++ b/gas/testsuite/gas/riscv/dw-regnums.s
@@ -0,0 +1,184 @@
+# Check that CFI directives can accept all of the register names (including
+# aliases).  The results for this test also ensures that the DWARF
+# register numbers for the GPRs/FPRs/vector registers shouldn't change.
+# Note that, because vector register size is "variable" in principle,
+# vector registers are very unlikely to be used within .cfi_offset directive.
+
+	.text
+	.global _start
+_start:
+	.cfi_startproc
+	nop
+
+	# GPRs (ABI)
+	.cfi_offset zero,  4
+	.cfi_offset ra,    8
+	.cfi_offset sp,   12
+	.cfi_offset gp,   16
+	.cfi_offset tp,   20
+	.cfi_offset t0,   24
+	.cfi_offset t1,   28
+	.cfi_offset t2,   32
+	.cfi_offset s0,   36
+	.cfi_offset s1,   40
+	.cfi_offset a0,   44
+	.cfi_offset a1,   48
+	.cfi_offset a2,   52
+	.cfi_offset a3,   56
+	.cfi_offset a4,   60
+	.cfi_offset a5,   64
+	.cfi_offset a6,   68
+	.cfi_offset a7,   72
+	.cfi_offset s2,   76
+	.cfi_offset s3,   80
+	.cfi_offset s4,   84
+	.cfi_offset s5,   88
+	.cfi_offset s6,   92
+	.cfi_offset s7,   96
+	.cfi_offset s8,  100
+	.cfi_offset s9,  104
+	.cfi_offset s10, 108
+	.cfi_offset s11, 112
+	.cfi_offset t3,  116
+	.cfi_offset t4,  120
+	.cfi_offset t5,  124
+	.cfi_offset t6,  128
+
+	# GPRs (Numeric)
+	.cfi_offset x0,    4
+	.cfi_offset x1,    8
+	.cfi_offset x2,   12
+	.cfi_offset x3,   16
+	.cfi_offset x4,   20
+	.cfi_offset x5,   24
+	.cfi_offset x6,   28
+	.cfi_offset x7,   32
+	.cfi_offset x8,   36
+	.cfi_offset x9,   40
+	.cfi_offset x10,  44
+	.cfi_offset x11,  48
+	.cfi_offset x12,  52
+	.cfi_offset x13,  56
+	.cfi_offset x14,  60
+	.cfi_offset x15,  64
+	.cfi_offset x16,  68
+	.cfi_offset x17,  72
+	.cfi_offset x18,  76
+	.cfi_offset x19,  80
+	.cfi_offset x20,  84
+	.cfi_offset x21,  88
+	.cfi_offset x22,  92
+	.cfi_offset x23,  96
+	.cfi_offset x24, 100
+	.cfi_offset x25, 104
+	.cfi_offset x26, 108
+	.cfi_offset x27, 112
+	.cfi_offset x28, 116
+	.cfi_offset x29, 120
+	.cfi_offset x30, 124
+	.cfi_offset x31, 128
+
+	# FPRs (ABI)
+	.cfi_offset ft0,  132
+	.cfi_offset ft1,  136
+	.cfi_offset ft2,  140
+	.cfi_offset ft3,  144
+	.cfi_offset ft4,  148
+	.cfi_offset ft5,  152
+	.cfi_offset ft6,  156
+	.cfi_offset ft7,  160
+	.cfi_offset fs0,  164
+	.cfi_offset fs1,  168
+	.cfi_offset fa0,  172
+	.cfi_offset fa1,  176
+	.cfi_offset fa2,  180
+	.cfi_offset fa3,  184
+	.cfi_offset fa4,  188
+	.cfi_offset fa5,  192
+	.cfi_offset fa6,  196
+	.cfi_offset fa7,  200
+	.cfi_offset fs2,  204
+	.cfi_offset fs3,  208
+	.cfi_offset fs4,  212
+	.cfi_offset fs5,  216
+	.cfi_offset fs6,  220
+	.cfi_offset fs7,  224
+	.cfi_offset fs8,  228
+	.cfi_offset fs9,  232
+	.cfi_offset fs10, 236
+	.cfi_offset fs11, 240
+	.cfi_offset ft8,  244
+	.cfi_offset ft9,  248
+	.cfi_offset ft10, 252
+	.cfi_offset ft11, 256
+
+	# FPRs (Numeric)
+	.cfi_offset f0,  132
+	.cfi_offset f1,  136
+	.cfi_offset f2,  140
+	.cfi_offset f3,  144
+	.cfi_offset f4,  148
+	.cfi_offset f5,  152
+	.cfi_offset f6,  156
+	.cfi_offset f7,  160
+	.cfi_offset f8,  164
+	.cfi_offset f9,  168
+	.cfi_offset f10, 172
+	.cfi_offset f11, 176
+	.cfi_offset f12, 180
+	.cfi_offset f13, 184
+	.cfi_offset f14, 188
+	.cfi_offset f15, 192
+	.cfi_offset f16, 196
+	.cfi_offset f17, 200
+	.cfi_offset f18, 204
+	.cfi_offset f19, 208
+	.cfi_offset f20, 212
+	.cfi_offset f21, 216
+	.cfi_offset f22, 220
+	.cfi_offset f23, 224
+	.cfi_offset f24, 228
+	.cfi_offset f25, 232
+	.cfi_offset f26, 236
+	.cfi_offset f27, 240
+	.cfi_offset f28, 244
+	.cfi_offset f29, 248
+	.cfi_offset f30, 252
+	.cfi_offset f31, 256
+
+	# Vector registers (numeric only)
+	.cfi_offset v0,  388
+	.cfi_offset v1,  392
+	.cfi_offset v2,  396
+	.cfi_offset v3,  400
+	.cfi_offset v4,  404
+	.cfi_offset v5,  408
+	.cfi_offset v6,  412
+	.cfi_offset v7,  416
+	.cfi_offset v8,  420
+	.cfi_offset v9,  424
+	.cfi_offset v10, 428
+	.cfi_offset v11, 432
+	.cfi_offset v12, 436
+	.cfi_offset v13, 440
+	.cfi_offset v14, 444
+	.cfi_offset v15, 448
+	.cfi_offset v16, 452
+	.cfi_offset v17, 456
+	.cfi_offset v18, 460
+	.cfi_offset v19, 464
+	.cfi_offset v20, 468
+	.cfi_offset v21, 472
+	.cfi_offset v22, 476
+	.cfi_offset v23, 480
+	.cfi_offset v24, 484
+	.cfi_offset v25, 488
+	.cfi_offset v26, 492
+	.cfi_offset v27, 496
+	.cfi_offset v28, 500
+	.cfi_offset v29, 504
+	.cfi_offset v30, 508
+	.cfi_offset v31, 512
+
+	nop
+	.cfi_endproc
-- 
2.34.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
  2022-09-22  6:32 [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Tsukasa OI
  2022-09-22  6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
  2022-09-22  6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
@ 2022-10-01 20:27 ` Andrew Burgess
  2022-10-02 15:58   ` Jeff Law
  2 siblings, 1 reply; 9+ messages in thread
From: Andrew Burgess @ 2022-10-01 20:27 UTC (permalink / raw)
  To: Tsukasa OI via Binutils, Tsukasa OI, Nelson Chu, Kito Cheng,
	Palmer Dabbelt
  Cc: binutils

Tsukasa OI via Binutils <binutils@sourceware.org> writes:

> Hello,
>
> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
> register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
> ratified yet but at least frozen.  So, I consider it's stable to upstream
> it.  According to the documentation, it has register numbers 96 (v0) -
> 127 (v31).
>
> [Changes: v1 -> v2]
> Remove invented word "VPRs" (at least it has no consistent uses in the
> RISC-V ecosystem) and replaced with "Vector registers"
>
> [Changes: v2 -> v3]
> Changed reference (v1.0-rc3 -> v1.0-rc4).
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>
>
> RISC-V ABIs Specification Version 1.0-rc4: Frozen
> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>
>
>
> I also added DWARF register number tests not just for CSRs (existing) and
> vector registers (I just added), but also for GPRs (0-31) and FPRs
> (32-63).

Hi Tsukasa,

I can't approve binutils patches, but as this mentioned RISC-V and
DWARF, both of which I'm interested in, I took a look :)

Both these patches look good to me.  The register numbers align with the
spec, and the test makes sense.

Thanks for the patch.

Andrew


>
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (2):
>   RISC-V: Assign DWARF numbers to vector registers
>   RISC-V: Add testcase for DWARF register numbers
>
>  binutils/dwarf.c                     |  28 ++--
>  gas/config/tc-riscv.c                |   3 +
>  gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++
>  4 files changed, 385 insertions(+), 10 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
>  create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s
>
>
> base-commit: 90eca7111355e4c6683c1ab10fd07107ea10f6d1
> -- 
> 2.34.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
  2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
@ 2022-10-02 15:58   ` Jeff Law
  2022-10-02 19:35     ` Palmer Dabbelt
  2022-10-03  1:36     ` Nelson Chu
  0 siblings, 2 replies; 9+ messages in thread
From: Jeff Law @ 2022-10-02 15:58 UTC (permalink / raw)
  To: binutils


On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
> Tsukasa OI via Binutils <binutils@sourceware.org> writes:
>
>> Hello,
>>
>> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
>> register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
>> ratified yet but at least frozen.  So, I consider it's stable to upstream
>> it.  According to the documentation, it has register numbers 96 (v0) -
>> 127 (v31).
>>
>> [Changes: v1 -> v2]
>> Remove invented word "VPRs" (at least it has no consistent uses in the
>> RISC-V ecosystem) and replaced with "Vector registers"
>>
>> [Changes: v2 -> v3]
>> Changed reference (v1.0-rc3 -> v1.0-rc4).
>>
>> Tracker on GitHub:
>> <https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>
>>
>> RISC-V ABIs Specification Version 1.0-rc4: Frozen
>> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>
>>
>>
>> I also added DWARF register number tests not just for CSRs (existing) and
>> vector registers (I just added), but also for GPRs (0-31) and FPRs
>> (32-63).
> Hi Tsukasa,
>
> I can't approve binutils patches, but as this mentioned RISC-V and
> DWARF, both of which I'm interested in, I took a look :)
>
> Both these patches look good to me.  The register numbers align with the
> spec, and the test makes sense.

Well, that's the key property -- they align with the spec.


I'm also not sure if I can approve for binutils, but if I can, OK for 
the trunk ;-)

Jeff

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
  2022-10-02 15:58   ` Jeff Law
@ 2022-10-02 19:35     ` Palmer Dabbelt
  2022-10-03  1:36     ` Nelson Chu
  1 sibling, 0 replies; 9+ messages in thread
From: Palmer Dabbelt @ 2022-10-02 19:35 UTC (permalink / raw)
  To: binutils

On Sun, 02 Oct 2022 08:58:56 PDT (-0700), binutils@sourceware.org wrote:
>
> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
>> Tsukasa OI via Binutils <binutils@sourceware.org> writes:
>>
>>> Hello,
>>>
>>> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
>>> register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
>>> ratified yet but at least frozen.  So, I consider it's stable to upstream
>>> it.  According to the documentation, it has register numbers 96 (v0) -
>>> 127 (v31).
>>>
>>> [Changes: v1 -> v2]
>>> Remove invented word "VPRs" (at least it has no consistent uses in the
>>> RISC-V ecosystem) and replaced with "Vector registers"
>>>
>>> [Changes: v2 -> v3]
>>> Changed reference (v1.0-rc3 -> v1.0-rc4).
>>>
>>> Tracker on GitHub:
>>> <https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>
>>>
>>> RISC-V ABIs Specification Version 1.0-rc4: Frozen
>>> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>
>>>
>>>
>>> I also added DWARF register number tests not just for CSRs (existing) and
>>> vector registers (I just added), but also for GPRs (0-31) and FPRs
>>> (32-63).
>> Hi Tsukasa,
>>
>> I can't approve binutils patches, but as this mentioned RISC-V and
>> DWARF, both of which I'm interested in, I took a look :)
>>
>> Both these patches look good to me.  The register numbers align with the
>> spec, and the test makes sense.
>
> Well, that's the key property -- they align with the spec.

My worry here was the PDF not aligining with the implementation, but I 
think I'd just been mis-reading the sources: I'd seen

  RISCV_PRIV_REGNUM = 4161,
  RISCV_V0_REGNUM,

but hadn't realized that I should actually be looking at

  RISCV_DWARF_REGNUM_V0 = 96,

so this is OK (and it looks like GCC is correct as well).

Thanks!

> I'm also not sure if I can approve for binutils, but if I can, OK for
> the trunk ;-)
>
> Jeff

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
  2022-10-02 15:58   ` Jeff Law
  2022-10-02 19:35     ` Palmer Dabbelt
@ 2022-10-03  1:36     ` Nelson Chu
  2022-10-03  4:04       ` Jeff Law
  2022-10-03  4:31       ` Tsukasa OI
  1 sibling, 2 replies; 9+ messages in thread
From: Nelson Chu @ 2022-10-03  1:36 UTC (permalink / raw)
  To: Jeff Law; +Cc: binutils

On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils
<binutils@sourceware.org> wrote:
>
> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
> > I can't approve binutils patches, but as this mentioned RISC-V and
> > DWARF, both of which I'm interested in, I took a look :)
> >
> > Both these patches look good to me.  The register numbers align with the
> > spec, and the test makes sense.
>
> Well, that's the key property -- they align with the spec.
>
>
> I'm also not sure if I can approve for binutils, but if I can, OK for
> the trunk ;-)

Thanks for your help, Andrew and Jeff!

Hi Jeff,

Of course!  You are a global maintainer of both gcc and binutils.
Welcome and please feel free to approve any RISC-V binutils patch if
you are free and the patch looks good to you :-)

Thanks!
Nelson

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
  2022-10-03  1:36     ` Nelson Chu
@ 2022-10-03  4:04       ` Jeff Law
  2022-10-03  4:31       ` Tsukasa OI
  1 sibling, 0 replies; 9+ messages in thread
From: Jeff Law @ 2022-10-03  4:04 UTC (permalink / raw)
  To: Nelson Chu; +Cc: binutils


On 10/2/22 19:36, Nelson Chu wrote:
> On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils
> <binutils@sourceware.org> wrote:
>> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
>>> I can't approve binutils patches, but as this mentioned RISC-V and
>>> DWARF, both of which I'm interested in, I took a look :)
>>>
>>> Both these patches look good to me.  The register numbers align with the
>>> spec, and the test makes sense.
>> Well, that's the key property -- they align with the spec.
>>
>>
>> I'm also not sure if I can approve for binutils, but if I can, OK for
>> the trunk ;-)
> Thanks for your help, Andrew and Jeff!
>
> Hi Jeff,
>
> Of course!  You are a global maintainer of both gcc and binutils.
> Welcome and please feel free to approve any RISC-V binutils patch if
> you are free and the patch looks good to you :-)

I may be listed as a global maintainer for binutils, but I haven't done 
much in this space in years and I'm cognizant that there's already a 
group of folks (yourself included) working together on RISC-V bits.   I 
don't want to step on anyones toes, but I also want to help share the load.


Jeff


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
  2022-10-03  1:36     ` Nelson Chu
  2022-10-03  4:04       ` Jeff Law
@ 2022-10-03  4:31       ` Tsukasa OI
  1 sibling, 0 replies; 9+ messages in thread
From: Tsukasa OI @ 2022-10-03  4:31 UTC (permalink / raw)
  To: Nelson Chu, Jeff Law, Andrew Burgess; +Cc: binutils

Many thanks to all of you!

Though I have to report that the exact changes you approved are merged
but two commits are splitted differently (due to technical mistake I
made; I mistakenly chose a "working" branch to push).

Approved PATCH v3:
-   PATCH 1: Assign DWARF register numbers to vector ones
-   PATCH 2: Add DWARF register number testcases (GPRs/FPRs/vector)

Merged commits:
-   COMMIT 1: Add DWARF register number testcases (GPRs/FPRs)
-   COMMIT 2: Assign DWARF register numbers to vector ones
              and add them to "existing" tests

I repeat that changes (COMMIT 1+2) are the _exactly_ the same as PATCH
1+2 but splitted differently.  Despite that this is functionally the
same, this is clearly not obvious and I should have checked.  I'll
submit the remaining part (to add "fp" to DWARF register number
testcases) as a separate patch but feel free to revert those two
commits.  In the event, I'll submit PATCH v4 of it.

Regards,
Tsukasa

On 2022/10/03 10:36, Nelson Chu wrote:
> On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils
> <binutils@sourceware.org> wrote:
>>
>> On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
>>> I can't approve binutils patches, but as this mentioned RISC-V and
>>> DWARF, both of which I'm interested in, I took a look :)
>>>
>>> Both these patches look good to me.  The register numbers align with the
>>> spec, and the test makes sense.
>>
>> Well, that's the key property -- they align with the spec.
>>
>>
>> I'm also not sure if I can approve for binutils, but if I can, OK for
>> the trunk ;-)
> 
> Thanks for your help, Andrew and Jeff!
> 
> Hi Jeff,
> 
> Of course!  You are a global maintainer of both gcc and binutils.
> Welcome and please feel free to approve any RISC-V binutils patch if
> you are free and the patch looks good to you :-)
> 
> Thanks!
> Nelson
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-10-03  4:31 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-22  6:32 [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Tsukasa OI
2022-09-22  6:32 ` [PATCH v3 1/2] RISC-V: Assign DWARF " Tsukasa OI
2022-09-22  6:32 ` [PATCH v3 2/2] RISC-V: Add testcase for DWARF register numbers Tsukasa OI
2022-10-01 20:27 ` [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers Andrew Burgess
2022-10-02 15:58   ` Jeff Law
2022-10-02 19:35     ` Palmer Dabbelt
2022-10-03  1:36     ` Nelson Chu
2022-10-03  4:04       ` Jeff Law
2022-10-03  4:31       ` Tsukasa OI

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).