From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by sourceware.org (Postfix) with ESMTPS id 421D13858D32 for ; Sun, 2 Oct 2022 15:58:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 421D13858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x1036.google.com with SMTP id h8-20020a17090a054800b00205ccbae31eso13263208pjf.5 for ; Sun, 02 Oct 2022 08:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:to:subject:user-agent:mime-version:date:message-id:from :to:cc:subject:date; bh=/gfSnXa6N229bNP9G0j2tHdyzYBywyjAe9N3VlDwh48=; b=BkH1NdWYL70i0ZO90sSKMl16ffIO4SOofp6nGl+/PkjHCg5G1843qhgj+JPFy+Uc9C 8yZ3g+nROm5eUAEI95ltk9pbzZqR5uccgdLQtcBOWM+dkn+wDZycyjcgLXkPTl5v/1tE F0siw9lUdLzi4rM4TUicLlGNNBh8wXBhFi6qfRjnZd2T8B6zsnk5gKG80uFNgaGTVvr2 p4AAP8U+m+TQcBtlJHsc4pJSl7CG9z57pDSWoFYfTjB0YCZktTyJdPF8MS1MbKT8rR16 etp2IM4LDFMi7GCb1uGoPmhRlSpPkN3elNdrVmd+zeUyEN9eKNYt+LeGdxvCrQk3Cjrt dq+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date; bh=/gfSnXa6N229bNP9G0j2tHdyzYBywyjAe9N3VlDwh48=; b=jXJpYkWS5XbYZpCPh3l9uFItrA/Gp49nm7Z93B/woqrkPW6fg7pcEIcWXOzqATSoR0 rRnUtlA6CbElalucNCvNDXCPJ8SapzgjEoUX/m8AnNsgEFTAIWvDAJEDB+a6djBjjihr rhzed2fK2C6D9ZbxwHcZw7MQz/RFlpy9KU8b59Lrqa9oj1hec+xoTzs0qMCQ9PT0wZbX V5XyWg/wtTZklB8CZizRhXpckZW3RJIeco+Jx2xrl/e2IFCOyhhWEmuzlZqTm8tgBaq8 W2P5v/3w2XQvoeACKqJd1NVL+9DmzIYD6xXSDQiWRXUNZ8xdnx/jufDAUs2g+J95OfvY MBRA== X-Gm-Message-State: ACrzQf0zu13G/OLuzRbVGXB1vCmJk7lzedDAO44/1zr+AZ3JpXLKJjGs GUD7013wM0OjJdDk+3WpGXLMYXNQ3f1OnQ== X-Google-Smtp-Source: AMsMyM6gzMi5/0HC6Ua4zhb/Yy4vL3vgXSpeGeGRUytsH6s2TNzyTzlxQZhlciRwA85DQNCrHFmIgw== X-Received: by 2002:a17:902:d70e:b0:178:2d9d:ba7b with SMTP id w14-20020a170902d70e00b001782d9dba7bmr18171011ply.90.1664726337972; Sun, 02 Oct 2022 08:58:57 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id h8-20020a170902680800b0017d97d13b18sm3155283plk.65.2022.10.02.08.58.56 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 02 Oct 2022 08:58:57 -0700 (PDT) Message-ID: <7cea93e7-f75b-2d5a-d63b-73288d4b3e5e@gmail.com> Date: Sun, 2 Oct 2022 09:58:56 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers To: binutils@sourceware.org References: <874jwni91f.fsf@redhat.com> Content-Language: en-US From: Jeff Law In-Reply-To: <874jwni91f.fsf@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 10/1/22 14:27, Andrew Burgess via Binutils wrote: > Tsukasa OI via Binutils writes: > >> Hello, >> >> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF >> register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not >> ratified yet but at least frozen. So, I consider it's stable to upstream >> it. According to the documentation, it has register numbers 96 (v0) - >> 127 (v31). >> >> [Changes: v1 -> v2] >> Remove invented word "VPRs" (at least it has no consistent uses in the >> RISC-V ecosystem) and replaced with "Vector registers" >> >> [Changes: v2 -> v3] >> Changed reference (v1.0-rc3 -> v1.0-rc4). >> >> Tracker on GitHub: >> >> >> RISC-V ABIs Specification Version 1.0-rc4: Frozen >> >> >> >> I also added DWARF register number tests not just for CSRs (existing) and >> vector registers (I just added), but also for GPRs (0-31) and FPRs >> (32-63). > Hi Tsukasa, > > I can't approve binutils patches, but as this mentioned RISC-V and > DWARF, both of which I'm interested in, I took a look :) > > Both these patches look good to me. The register numbers align with the > spec, and the test makes sense. Well, that's the key property -- they align with the spec. I'm also not sure if I can approve for binutils, but if I can, OK for the trunk ;-) Jeff