From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: Richard Earnshaw <rearnsha@arm.com>,
Marcus Shawcroft <marcus.shawcroft@arm.com>,
Nick Clifton <nickc@redhat.com>
Subject: [PATCH 5/6] Arm64: correct SVE2.1 ld2q (scalar plus scalar)
Date: Fri, 23 Feb 2024 12:30:28 +0100 [thread overview]
Message-ID: <7d119881-d42a-48cf-b50f-7c97819c5047@suse.com> (raw)
In-Reply-To: <2dbdd49f-2302-4dbc-98ba-0bdaf3c4cad2@suse.com>
It's opcode was wrong, as was e.g. easily visible from the inappropriate
testcase expectation.
--- a/gas/testsuite/gas/aarch64/sve2p1-1.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-1.d
@@ -93,7 +93,7 @@
.*: a49ef000 ld2q {z0.q, z1.q}, p4/z, \[x0, #-4, mul vl\]
.*: a51ef000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, #-6, mul vl\]
.*: a59ef000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, #-8, mul vl\]
-.*: a4a2f000 ld2h {z0.h-z1.h}, p4/z, \[x0, #4, mul vl\]
+.*: a4a29000 ld2q {z0.q, z1.q}, p4/z, \[x0, x2, lsl #4\]
.*: a5249000 ld3q {z0.q, z1.q, z2.q}, p4/z, \[x0, x4, lsl #4\]
.*: a5a69000 ld4q {z0.q, z1.q, z2.q, z3.q}, p4/z, \[x0, x6, lsl #4\]
.*: e4203200 st1q z0.q, p4, \[z16.d, x0\]
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6380,7 +6380,7 @@ const struct aarch64_opcode aarch64_opco
SVE2p1_INSNC("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld4q",0xa590e000, 0xfff0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("ld2q",0xa4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p1_INSNC("ld2q",0xa4a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt2, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld3q",0xa5208000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
SVE2p1_INSNC("ld4q",0xa5a08000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QZU, 0, C_SCAN_MOVPRFX, 0),
next prev parent reply other threads:[~2024-02-23 11:30 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-23 11:26 [PATCH 0/6] Arm64: (mostly) SVE adjustments Jan Beulich
2024-02-23 11:28 ` [PATCH 1/6] Arm64: correct B16B16 indexed bf{mla,mls,mul} Jan Beulich
2024-03-20 15:54 ` Richard Earnshaw (lists)
2024-03-20 16:09 ` Jan Beulich
2024-02-23 11:28 ` [PATCH 2/6] Arm64: check matching operands for predicated B16B16 insns Jan Beulich
2024-03-20 16:19 ` Richard Earnshaw (lists)
2024-02-23 11:29 ` [PATCH 3/6] Arm64: check tied operand specifier in aarch64-gen Jan Beulich
2024-03-15 16:09 ` Andrew Carlotti
2024-03-18 8:35 ` Jan Beulich
2024-03-20 16:51 ` Richard Earnshaw (lists)
2024-03-21 7:38 ` Jan Beulich
2024-02-23 11:29 ` [PATCH 4/6] Arm64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate) Jan Beulich
2024-05-09 14:31 ` Richard Earnshaw (lists)
2024-02-23 11:30 ` Jan Beulich [this message]
2024-05-09 14:34 ` [PATCH 5/6] Arm64: correct SVE2.1 ld2q (scalar plus scalar) Richard Earnshaw (lists)
2024-02-23 11:30 ` [PATCH 6/6] gas/NEWS: drop mention of Arm64's SVE2.1 and SME2.1 Jan Beulich
2024-03-15 16:20 ` [PATCH 0/6] Arm64: (mostly) SVE adjustments Andrew Carlotti
2024-03-18 8:23 ` Jan Beulich
2024-05-09 14:17 ` Richard Earnshaw (lists)
2024-05-14 6:57 ` Jan Beulich
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