From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH 3/3] x86: consolidate VPCLMUL tests
Date: Thu, 20 Oct 2022 12:26:40 +0200 [thread overview]
Message-ID: <7ff09c86-2de7-dc34-3183-5187de3df5ac@suse.com> (raw)
In-Reply-To: <9b353713-17f2-65b6-e9f8-23977f539fdd@suse.com>
There's little point in having Intel syntax disassembler tests when the
purpose of a test is assembler functionality: Drop all
*avx512*_vpclmulqdq-wig1-intel.
For *avx512*_vpclmulqdq-wig1 share source with *avx512*_vpclmulqdq.
Finally put in place similar tests for -mvexwig=1.
--- a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig.s
+++ /dev/null
@@ -1,13 +0,0 @@
-# Check 32bit AVX512F,VPCLMULQDQ WIG instructions
-
- .allow_index_reg
- .text
-_start:
- vpclmulqdq $0xab, %zmm2, %zmm1, %zmm6 # AVX512F,VPCLMULQDQ
- vpclmulqdq $123, -123456(%esp,%esi,8), %zmm1, %zmm6 # AVX512F,VPCLMULQDQ
- vpclmulqdq $123, 8128(%edx), %zmm1, %zmm6 # AVX512F,VPCLMULQDQ Disp8
-
- .intel_syntax noprefix
- vpclmulqdq zmm5, zmm1, zmm2, 0xab # AVX512F,VPCLMULQDQ
- vpclmulqdq zmm5, zmm1, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,VPCLMULQDQ
- vpclmulqdq zmm5, zmm1, ZMMWORD PTR [edx+8128], 123 # AVX512F,VPCLMULQDQ Disp8
--- a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d
+++ b/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d
@@ -1,7 +1,7 @@
#as: -mevexwig=1
#objdump: -dw
#name: i386 AVX512F/VPCLMULQDQ wig insns
-#source: avx512f_vpclmulqdq-wig.s
+#source: avx512f_vpclmulqdq.s
.*: +file format .*
@@ -9,10 +9,14 @@
Disassembly of section \.text:
00000000 <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 f2 ab[ ]*vpclmulqdq \$0xab,%zmm2,%zmm1,%zmm6
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm1,%zmm6
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm1,%zmm6
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ea ab[ ]*vpclmulqdq \$0xab,%zmm2,%zmm1,%zmm5
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ac f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm1,%zmm5
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm1,%zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 e5 48 44 c9 ab[ ]*vpclmulqdq \$0xab,%zmm1,%zmm3,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 e5 48 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm3,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 e5 48 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm3,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 48 44 d9 11[ ]*vpclmulhqhqdq %zmm1,%zmm2,%zmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 e5 48 44 e2 01[ ]*vpclmulhqlqdq %zmm2,%zmm3,%zmm4
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 48 44 eb 10[ ]*vpclmullqhqdq %zmm3,%zmm4,%zmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 44 f4 00[ ]*vpclmullqlqdq %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 48 44 d2 ab[ ]*vpclmulqdq \$0xab,%zmm2,%zmm2,%zmm2
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 48 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm2,%zmm2
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 48 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%edx\),%zmm2,%zmm2
#pass
--- a/gas/testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d
+++ /dev/null
@@ -1,18 +0,0 @@
-#as: -mevexwig=1
-#objdump: -dw -Mintel
-#name: i386 AVX512F/VPCLMULQDQ wig insns (Intel disassembly)
-#source: avx512f_vpclmulqdq-wig.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-00000000 <_start>:
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 f2 ab[ ]*vpclmulqdq zmm6,zmm1,zmm2,0xab
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm6,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 72 7f 7b[ ]*vpclmulqdq zmm6,zmm1,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ea ab[ ]*vpclmulqdq zmm5,zmm1,zmm2,0xab
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 ac f4 c0 1d fe ff 7b[ ]*vpclmulqdq zmm5,zmm1,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 48 44 6a 7f 7b[ ]*vpclmulqdq zmm5,zmm1,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
-#pass
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# Check 32bit AVX512VL,VPCLMULQDQ WIG instructions
-
- .allow_index_reg
- .text
-_start:
- vpclmulqdq $0xab, %xmm4, %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, -123456(%esp,%esi,8), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, 2032(%edx), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ Disp8
- vpclmulqdq $0xab, %ymm2, %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, 4064(%edx), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ Disp8
-
- {evex} vpclmulqdq $0xab, %xmm4, %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, -123456(%esp,%esi,8), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, 2032(%edx), %xmm1, %xmm1 # AVX512VL,VPCLMULQDQ Disp8
- {evex} vpclmulqdq $0xab, %ymm2, %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, -123456(%esp,%esi,8), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, 4064(%edx), %ymm5, %ymm3 # AVX512VL,VPCLMULQDQ Disp8
-
- .intel_syntax noprefix
- vpclmulqdq xmm6, xmm4, xmm1, 0xab # AVX512VL,VPCLMULQDQ
- vpclmulqdq xmm6, xmm4, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
- vpclmulqdq xmm6, xmm4, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
- vpclmulqdq ymm2, ymm4, ymm4, 0xab # AVX512VL,VPCLMULQDQ
- vpclmulqdq ymm2, ymm4, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
- vpclmulqdq ymm2, ymm4, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
-
- {evex} vpclmulqdq xmm6, xmm4, xmm1, 0xab # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq xmm6, xmm4, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq xmm6, xmm4, XMMWORD PTR [edx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
- {evex} vpclmulqdq ymm2, ymm4, ymm4, 0xab # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq ymm2, ymm4, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq ymm2, ymm4, YMMWORD PTR [edx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d
@@ -1,7 +1,7 @@
#as: -mevexwig=1
#objdump: -dw
#name: i386 AVX512VL/VPCLMULQDQ wig insns
-#source: avx512vl_vpclmulqdq-wig.s
+#source: avx512vl_vpclmulqdq.s
.*: +file format .*
@@ -9,28 +9,36 @@
Disassembly of section \.text:
00000000 <_start>:
-[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 cc ab[ ]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
-[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
-[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
-[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 da ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
-[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
-[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9a e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
-[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 f1 ab[ ]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
-[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
-[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b2 f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 d4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
-[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
-[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 da ab[ ]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 69 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 08 44 da ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 e1 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 a4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 62 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 e5 08 44 e2 11[ ]*\{evex\} vpclmulhqhqdq %xmm2,%xmm3,%xmm4
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 eb 01[ ]*\{evex\} vpclmulhqlqdq %xmm3,%xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 08 44 f4 10[ ]*\{evex\} vpclmullqhqdq %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 cd 08 44 fd 00[ ]*\{evex\} vpclmullqlqdq %xmm5,%xmm6,%xmm7
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 28 44 d9 11[ ]*\{evex\} vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+[ ]*[a-f0-9]+:[ ]*62 f3 e5 28 44 e2 01[ ]*\{evex\} vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 eb 10[ ]*\{evex\} vpclmullqhqdq %ymm3,%ymm4,%ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 f4 00[ ]*\{evex\} vpclmullqlqdq %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 08 44 db ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 28 44 d2 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 ed 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
#pass
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d
+++ /dev/null
@@ -1,36 +0,0 @@
-#as: -mevexwig=1
-#objdump: -dw -Mintel
-#name: i386 AVX512VL/VPCLMULQDQ wig insns (Intel disassembly)
-#source: avx512vl_vpclmulqdq-wig.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-00000000 <_start>:
-[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 cc ab[ ]*vpclmulqdq xmm1,xmm1,xmm4,0xab
-[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 71 44 8a f0 07 00 00 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 da ab[ ]*vpclmulqdq ymm3,ymm5,ymm2,0xab
-[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9a e0 0f 00 00 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*\{evex\} vpclmulqdq xmm1,xmm1,xmm4,0xab
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*\{evex\} vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*\{evex\} vpclmulqdq ymm3,ymm5,ymm2,0xab
-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 f1 ab[ ]*vpclmulqdq xmm6,xmm4,xmm1,0xab
-[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b2 f0 07 00 00 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 d4 ab[ ]*vpclmulqdq ymm2,ymm4,ymm4,0xab
-[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*\{evex\} vpclmulqdq xmm6,xmm4,xmm1,0xab
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*\{evex\} vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*\{evex\} vpclmulqdq ymm2,ymm4,ymm4,0xab
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
-#pass
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -458,11 +458,9 @@ if [gas_32_check] then {
run_dump_test "avx512f_vpclmulqdq"
run_dump_test "avx512f_vpclmulqdq-intel"
run_dump_test "avx512f_vpclmulqdq-wig1"
- run_dump_test "avx512f_vpclmulqdq-wig1-intel"
run_dump_test "avx512vl_vpclmulqdq"
run_dump_test "avx512vl_vpclmulqdq-intel"
run_dump_test "avx512vl_vpclmulqdq-wig1"
- run_dump_test "avx512vl_vpclmulqdq-wig1-intel"
run_dump_test "avx512vnni"
run_dump_test "avx512vnni-intel"
run_dump_test "avx512vnni_vl"
@@ -496,6 +494,7 @@ if [gas_32_check] then {
run_dump_test "vaes-wig1"
run_dump_test "vpclmulqdq"
run_dump_test "vpclmulqdq-intel"
+ run_dump_test "vpclmulqdq-wig1"
run_dump_test "wbnoinvd"
run_dump_test "wbnoinvd-intel"
run_dump_test "pconfig"
@@ -1124,11 +1123,9 @@ if [gas_64_check] then {
run_dump_test "x86-64-avx512f_vpclmulqdq"
run_dump_test "x86-64-avx512f_vpclmulqdq-intel"
run_dump_test "x86-64-avx512f_vpclmulqdq-wig1"
- run_dump_test "x86-64-avx512f_vpclmulqdq-wig1-intel"
run_dump_test "x86-64-avx512vl_vpclmulqdq"
run_dump_test "x86-64-avx512vl_vpclmulqdq-intel"
run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1"
- run_dump_test "x86-64-avx512vl_vpclmulqdq-wig1-intel"
run_dump_test "x86-64-avx512vnni"
run_dump_test "x86-64-avx512vnni-intel"
run_dump_test "x86-64-avx512vnni_vl"
@@ -1157,6 +1154,7 @@ if [gas_64_check] then {
run_dump_test "x86-64-vaes-wig1"
run_dump_test "x86-64-vpclmulqdq"
run_dump_test "x86-64-vpclmulqdq-intel"
+ run_dump_test "x86-64-vpclmulqdq-wig1"
run_dump_test "x86-64-wbnoinvd"
run_dump_test "x86-64-wbnoinvd-intel"
run_dump_test "x86-64-pconfig"
--- /dev/null
+++ b/gas/testsuite/gas/i386/vpclmulqdq-wig1.d
@@ -0,0 +1,44 @@
+#as: -mvexwig=1
+#objdump: -dw
+#name: i386 AVX/VPCLMULQDQ wig insns
+#source: avx512vl_vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 e3 e9 44 da ab[ ]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 e9 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 e9 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*c4 e3 d5 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 65 08 44 e2 11[ ]*\{evex\} vpclmulhqhqdq %xmm2,%xmm3,%xmm4
+[ ]*[a-f0-9]+:[ ]*62 f3 5d 08 44 eb 01[ ]*\{evex\} vpclmulhqlqdq %xmm3,%xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 f4 10[ ]*\{evex\} vpclmullqhqdq %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 44 fd 00[ ]*\{evex\} vpclmullqlqdq %xmm5,%xmm6,%xmm7
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d9 11[ ]*\{evex\} vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+[ ]*[a-f0-9]+:[ ]*62 f3 65 28 44 e2 01[ ]*\{evex\} vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+[ ]*[a-f0-9]+:[ ]*62 f3 5d 28 44 eb 10[ ]*\{evex\} vpclmullqhqdq %ymm3,%ymm4,%ymm5
+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 f4 00[ ]*\{evex\} vpclmullqlqdq %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+:[ ]*c4 e3 d1 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 d1 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 d1 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*c4 e3 ed 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+#pass
--- a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s
+++ /dev/null
@@ -1,13 +0,0 @@
-# Check 64bit AVX512F,VPCLMULQDQ WIG instructions
-
- .allow_index_reg
- .text
-_start:
- vpclmulqdq $0xab, %zmm19, %zmm20, %zmm22 # AVX512F,VPCLMULQDQ
- vpclmulqdq $123, 0x123(%rax,%r14,8), %zmm20, %zmm22 # AVX512F,VPCLMULQDQ
- vpclmulqdq $123, 8128(%rdx), %zmm20, %zmm22 # AVX512F,VPCLMULQDQ Disp8
-
- .intel_syntax noprefix
- vpclmulqdq zmm29, zmm28, zmm23, 0xab # AVX512F,VPCLMULQDQ
- vpclmulqdq zmm29, zmm28, ZMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512F,VPCLMULQDQ
- vpclmulqdq zmm29, zmm28, ZMMWORD PTR [rdx+8128], 123 # AVX512F,VPCLMULQDQ Disp8
--- a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d
@@ -1,7 +1,7 @@
#as: -mevexwig=1
#objdump: -dw
#name: x86_64 AVX512F/VPCLMULQDQ wig insns
-#source: x86-64-avx512f_vpclmulqdq-wig.s
+#source: x86-64-avx512f_vpclmulqdq.s
.*: +file format .*
@@ -9,10 +9,14 @@
Disassembly of section \.text:
0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 f3 ab[ ]*vpclmulqdq \$0xab,%zmm19,%zmm20,%zmm22
-[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 b4 f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm20,%zmm22
-[ ]*[a-f0-9]+:[ ]*62 e3 dd 40 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm20,%zmm22
-[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ef ab[ ]*vpclmulqdq \$0xab,%zmm23,%zmm28,%zmm29
-[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm28,%zmm29
-[ ]*[a-f0-9]+:[ ]*62 63 9d 40 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm28,%zmm29
+[ ]*[a-f0-9]+:[ ]*62 03 c5 40 44 d0 ab[ ]*vpclmulqdq \$0xab,%zmm24,%zmm23,%zmm26
+[ ]*[a-f0-9]+:[ ]*62 23 c5 40 44 94 f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%zmm23,%zmm26
+[ ]*[a-f0-9]+:[ ]*62 63 c5 40 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm23,%zmm26
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 40 44 f4 11[ ]*vpclmulhqhqdq %zmm20,%zmm21,%zmm22
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 40 44 fd 01[ ]*vpclmulhqlqdq %zmm21,%zmm22,%zmm23
+[ ]*[a-f0-9]+:[ ]*62 23 c5 40 44 c6 10[ ]*vpclmullqhqdq %zmm22,%zmm23,%zmm24
+[ ]*[a-f0-9]+:[ ]*62 23 bd 40 44 cf 00[ ]*vpclmullqlqdq %zmm23,%zmm24,%zmm25
+[ ]*[a-f0-9]+:[ ]*62 83 d5 40 44 eb ab[ ]*vpclmulqdq \$0xab,%zmm27,%zmm21,%zmm21
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%zmm21,%zmm21
+[ ]*[a-f0-9]+:[ ]*62 e3 d5 40 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0x1fc0\(%rdx\),%zmm21,%zmm21
#pass
--- a/gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d
+++ /dev/null
@@ -1,18 +0,0 @@
-#as: -mevexwig=1
-#objdump: -dw -Mintel
-#name: x86_64 AVX512F/VPCLMULQDQ wig insns (Intel disassembly)
-#source: x86-64-avx512f_vpclmulqdq-wig.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 f3 ab[ ]*vpclmulqdq zmm22,zmm20,zmm19,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 dd 40 44 b4 f0 23 01 00 00 7b[ ]*vpclmulqdq zmm22,zmm20,ZMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 dd 40 44 72 7f 7b[ ]*vpclmulqdq zmm22,zmm20,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ef ab[ ]*vpclmulqdq zmm29,zmm28,zmm23,0xab
-[ ]*[a-f0-9]+:[ ]*62 23 9d 40 44 ac f0 34 12 00 00 7b[ ]*vpclmulqdq zmm29,zmm28,ZMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 9d 40 44 6a 7f 7b[ ]*vpclmulqdq zmm29,zmm28,ZMMWORD PTR \[rdx\+0x1fc0\],0x7b
-#pass
--- a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s
+++ /dev/null
@@ -1,33 +0,0 @@
-# Check 64bit AVX512VL,VPCLMULQDQ WIG instructions
-
- .allow_index_reg
- .text
-_start:
- vpclmulqdq $0xab, %xmm23, %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, 2032(%rdx), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ Disp8
- vpclmulqdq $0xab, %ymm19, %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
- vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ Disp8
-
- {evex} vpclmulqdq $0xab, %xmm23, %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, 2032(%rdx), %xmm21, %xmm17 # AVX512VL,VPCLMULQDQ Disp8
- {evex} vpclmulqdq $0xab, %ymm19, %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, 0x123(%rax,%r14,8), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq $123, 4064(%rdx), %ymm18, %ymm23 # AVX512VL,VPCLMULQDQ Disp8
-
- .intel_syntax noprefix
- vpclmulqdq xmm18, xmm22, xmm17, 0xab # AVX512VL,VPCLMULQDQ
- vpclmulqdq xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
- vpclmulqdq xmm18, xmm22, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
- vpclmulqdq ymm26, ymm25, ymm23, 0xab # AVX512VL,VPCLMULQDQ
- vpclmulqdq ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
- vpclmulqdq ymm26, ymm25, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
-
- {evex} vpclmulqdq xmm18, xmm22, xmm17, 0xab # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq xmm18, xmm22, XMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq xmm18, xmm22, XMMWORD PTR [rdx+2032], 123 # AVX512VL,VPCLMULQDQ Disp8
- {evex} vpclmulqdq ymm26, ymm25, ymm23, 0xab # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq ymm26, ymm25, YMMWORD PTR [rax+r14*8+0x1234], 123 # AVX512VL,VPCLMULQDQ
- {evex} vpclmulqdq ymm26, ymm25, YMMWORD PTR [rdx+4064], 123 # AVX512VL,VPCLMULQDQ Disp8
--- a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d
@@ -1,7 +1,7 @@
#as: -mevexwig=1
#objdump: -dw
#name: x86_64 AVX512VL/VPCLMULQDQ wig insns
-#source: x86-64-avx512vl_vpclmulqdq-wig.s
+#source: x86-64-avx512vl_vpclmulqdq.s
.*: +file format .*
@@ -9,28 +9,36 @@
Disassembly of section \.text:
0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq \$0xab,%xmm23,%xmm21,%xmm17
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm21,%xmm17
-[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm21,%xmm17
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm19,%ymm18,%ymm23
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm23
-[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm23
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq \$0xab,%xmm23,%xmm21,%xmm17
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm21,%xmm17
-[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm21,%xmm17
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm19,%ymm18,%ymm23
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm23
-[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm23
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq \$0xab,%xmm17,%xmm22,%xmm18
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm22,%xmm18
-[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm22,%xmm18
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq \$0xab,%ymm23,%ymm25,%ymm26
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm25,%ymm26
-[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm25,%ymm26
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq \$0xab,%xmm17,%xmm22,%xmm18
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm22,%xmm18
-[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm22,%xmm18
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq \$0xab,%ymm23,%ymm25,%ymm26
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm25,%ymm26
-[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm25,%ymm26
+[ ]*[a-f0-9]+:[ ]*62 23 95 00 44 ca ab[ ]*vpclmulqdq \$0xab,%xmm18,%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 95 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 ed 20 44 ea ab[ ]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 23 ed 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 63 ed 20 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 23 95 00 44 ca ab[ ]*vpclmulqdq \$0xab,%xmm18,%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 95 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 63 95 00 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm29,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 23 ed 20 44 ea ab[ ]*vpclmulqdq \$0xab,%ymm18,%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 23 ed 20 44 ac f0 23 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x123\(%rax,%r14,8\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 63 ed 20 44 6a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm18,%ymm29
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 f4 11[ ]*vpclmulhqhqdq %xmm20,%xmm21,%xmm22
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 fd 01[ ]*vpclmulhqlqdq %xmm21,%xmm22,%xmm23
+[ ]*[a-f0-9]+:[ ]*62 23 c5 00 44 c6 10[ ]*vpclmullqhqdq %xmm22,%xmm23,%xmm24
+[ ]*[a-f0-9]+:[ ]*62 23 bd 00 44 cf 00[ ]*vpclmullqlqdq %xmm23,%xmm24,%xmm25
+[ ]*[a-f0-9]+:[ ]*62 a3 d5 20 44 f4 11[ ]*vpclmulhqhqdq %ymm20,%ymm21,%ymm22
+[ ]*[a-f0-9]+:[ ]*62 a3 cd 20 44 fd 01[ ]*vpclmulhqlqdq %ymm21,%ymm22,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 23 c5 20 44 c6 10[ ]*vpclmullqhqdq %ymm22,%ymm23,%ymm24
+[ ]*[a-f0-9]+:[ ]*62 23 bd 20 44 cf 00[ ]*vpclmullqlqdq %ymm23,%ymm24,%ymm25
+[ ]*[a-f0-9]+:[ ]*62 a3 ad 00 44 dc ab[ ]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 a3 ad 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 e3 ad 00 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 83 95 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm27,%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 95 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 e3 95 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 ad 00 44 dc ab[ ]*vpclmulqdq \$0xab,%xmm20,%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 a3 ad 00 44 9c f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 e3 ad 00 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%rdx\),%xmm26,%xmm19
+[ ]*[a-f0-9]+:[ ]*62 83 95 20 44 fb ab[ ]*vpclmulqdq \$0xab,%ymm27,%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 a3 95 20 44 bc f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm29,%ymm23
+[ ]*[a-f0-9]+:[ ]*62 e3 95 20 44 7a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm29,%ymm23
#pass
--- a/gas/testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d
+++ /dev/null
@@ -1,36 +0,0 @@
-#as: -mevexwig=1
-#objdump: -dw -Mintel
-#name: x86_64 AVX512VL/VPCLMULQDQ wig insns (Intel disassembly)
-#source: x86-64-avx512vl_vpclmulqdq-wig.s
-
-.*: +file format .*
-
-
-Disassembly of section \.text:
-
-0+ <_start>:
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq xmm17,xmm21,xmm23,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rdx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm18,ymm19,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 cf ab[ ]*vpclmulqdq xmm17,xmm21,xmm23,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 d5 00 44 8c f0 23 01 00 00 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 d5 00 44 4a 7f 7b[ ]*vpclmulqdq xmm17,xmm21,XMMWORD PTR \[rdx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 fb ab[ ]*vpclmulqdq ymm23,ymm18,ymm19,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 ed 20 44 bc f0 23 01 00 00 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rax\+r14\*8\+0x123\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 ed 20 44 7a 7f 7b[ ]*vpclmulqdq ymm23,ymm18,YMMWORD PTR \[rdx\+0xfe0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq xmm18,xmm22,xmm17,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rdx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq ymm26,ymm25,ymm23,0xab
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rdx\+0xfe0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 d1 ab[ ]*vpclmulqdq xmm18,xmm22,xmm17,0xab
-[ ]*[a-f0-9]+:[ ]*62 a3 cd 00 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 e3 cd 00 44 52 7f 7b[ ]*vpclmulqdq xmm18,xmm22,XMMWORD PTR \[rdx\+0x7f0\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 d7 ab[ ]*vpclmulqdq ymm26,ymm25,ymm23,0xab
-[ ]*[a-f0-9]+:[ ]*62 23 b5 20 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rax\+r14\*8\+0x1234\],0x7b
-[ ]*[a-f0-9]+:[ ]*62 63 b5 20 44 52 7f 7b[ ]*vpclmulqdq ymm26,ymm25,YMMWORD PTR \[rdx\+0xfe0\],0x7b
-#pass
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vpclmulqdq-wig1.d
@@ -0,0 +1,22 @@
+#as: -mvexwig=1
+#objdump: -dw
+#name: x86_64 AVX/VPCLMULQDQ wig insns
+#source: x86-64-vpclmulqdq.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+:[ ]*c4 43 b5 44 d0 ab[ ]*vpclmulqdq \$0xab,%ymm8,%ymm9,%ymm10
+[ ]*[a-f0-9]+:[ ]*c4 23 b5 44 94 f0 24 01 00 00 7b[ ]*vpclmulqdq \$0x7b,0x124\(%rax,%r14,8\),%ymm9,%ymm10
+[ ]*[a-f0-9]+:[ ]*c4 63 b5 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm9,%ymm10
+[ ]*[a-f0-9]+:[ ]*c4 43 a5 44 e2 11[ ]*vpclmulhqhqdq %ymm10,%ymm11,%ymm12
+[ ]*[a-f0-9]+:[ ]*c4 43 9d 44 eb 01[ ]*vpclmulhqlqdq %ymm11,%ymm12,%ymm13
+[ ]*[a-f0-9]+:[ ]*c4 43 95 44 f4 10[ ]*vpclmullqhqdq %ymm12,%ymm13,%ymm14
+[ ]*[a-f0-9]+:[ ]*c4 43 8d 44 fd 00[ ]*vpclmullqlqdq %ymm13,%ymm14,%ymm15
+[ ]*[a-f0-9]+:[ ]*c4 43 b5 44 d0 ab[ ]*vpclmulqdq \$0xab,%ymm8,%ymm9,%ymm10
+[ ]*[a-f0-9]+:[ ]*c4 23 b5 44 94 f0 34 12 00 00 7b[ ]*vpclmulqdq \$0x7b,0x1234\(%rax,%r14,8\),%ymm9,%ymm10
+[ ]*[a-f0-9]+:[ ]*c4 63 b5 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%rdx\),%ymm9,%ymm10
+#pass
next prev parent reply other threads:[~2022-10-20 10:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 10:24 [PATCH 0/3] x86: optionally emit {evex} prefix / testsuite tidying Jan Beulich
2022-10-20 10:25 ` [PATCH 1/3] x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns Jan Beulich
2022-10-20 10:26 ` [PATCH 2/3] x86: consolidate VAES tests Jan Beulich
2022-10-20 10:26 ` Jan Beulich [this message]
2022-10-21 19:39 ` [PATCH 0/3] x86: optionally emit {evex} prefix / testsuite tidying H.J. Lu
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