* [PATCH] Reorder MSA branches
@ 2013-10-18 0:18 Chao-Ying Fu
2013-10-18 8:04 ` Richard Sandiford
0 siblings, 1 reply; 3+ messages in thread
From: Chao-Ying Fu @ 2013-10-18 0:18 UTC (permalink / raw)
To: 'Richard Sandiford', 'Maciej W. Rozycki'
Cc: 'binutils@sourceware.org'
Hi All,
I forgot to support the reordering of MSA branches.
Here are two versions of patches.
Version 1. We disable the reordering of MSA branches conservatively.
2013-10-17 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* config/tc-mips.c (can_swap_branch_p): Don't swap MSA branches.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.594
diff -u -p -r1.594 tc-mips.c
--- gas/config/tc-mips.c 14 Oct 2013 18:50:54 -0000 1.594
+++ gas/config/tc-mips.c 17 Oct 2013 23:43:58 -0000
@@ -6144,6 +6144,10 @@ can_swap_branch_p (struct mips_cl_insn *
if (gpr_read & prev_gpr_write)
return FALSE;
+ /* If the branch reads MSA registers, we won't swap conservatively. */
+ if (insn_reg_mask (ip, 1 << OP_REG_MSA, insn_read_mask (ip->insn_mo)))
+ return FALSE;
+
/* If the branch writes a register that the previous
instruction sets, we can not swap. */
gpr_write = gpr_write_mask (ip);
Version 2.
Because the MSA registers share the FP registers (if the FPU is present),
we combine FP and MSA register dependences together.
2013-10-17 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* config/tc-mips.c (fpr_read_mask): Test MSA registers.
(fpr_write_mask): Test MSA registers.
(can_swap_branch_p): Check fpr write followed by fpr read.
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.594
diff -u -p -r1.594 tc-mips.c
--- gas/config/tc-mips.c 14 Oct 2013 18:50:54 -0000 1.594
+++ gas/config/tc-mips.c 17 Oct 2013 23:38:59 -0000
@@ -4161,7 +4161,8 @@ fpr_read_mask (const struct mips_cl_insn
unsigned long pinfo;
unsigned int mask;
- mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
+ mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC)
+ | (1 << OP_REG_MSA),
insn_read_mask (ip->insn_mo));
pinfo = ip->insn_mo->pinfo;
/* Conservatively treat all operands to an FP_D instruction are doubles.
@@ -4179,7 +4180,8 @@ fpr_write_mask (const struct mips_cl_ins
unsigned long pinfo;
unsigned int mask;
- mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
+ mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC)
+ | (1 << OP_REG_MSA),
insn_write_mask (ip->insn_mo));
pinfo = ip->insn_mo->pinfo;
/* Conservatively treat all operands to an FP_D instruction are doubles.
@@ -6070,6 +6072,7 @@ can_swap_branch_p (struct mips_cl_insn *
{
unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
+ unsigned int fpr_read, prev_fpr_write;
/* -O2 and above is required for this optimization. */
if (mips_optimize < 2)
@@ -6144,6 +6147,11 @@ can_swap_branch_p (struct mips_cl_insn *
if (gpr_read & prev_gpr_write)
return FALSE;
+ fpr_read = fpr_read_mask (ip);
+ prev_fpr_write = fpr_write_mask (&history[0]);
+ if (fpr_read & prev_fpr_write)
+ return FALSE;
+
/* If the branch writes a register that the previous
instruction sets, we can not swap. */
gpr_write = gpr_write_mask (ip);
# Testing
# cat r.s
.set reorder
test:
fsune.d $w0,$w1,$w2
bz.d $w0, test
fsune.d $w0,$w1,$w2
bz.d $w1, test
fsune.d $w0,$w1,$w2
bz.d $w2, test
add.s $f0,$f1,$f2
bz.d $w0, test
add.s $f0,$f1,$f2
bz.d $w1, test
add.s $f0,$f1,$f2
bz.d $w2, test
add.d $f0,$f2,$f4
bz.d $w0, test
add.d $f0,$f2,$f4
bz.d $w1, test
add.d $f0,$f2,$f4
bz.d $w2, test
# as-new r.s -o r.o -mmsa -mips32r2 -mfp64
# objdump -d r.o
00000000 <test>:
0: 7aa2081c fsune.d $w0,$w1,$w2
4: 4760fffe bz.d $w0,0 <test>
8: 00000000 nop
c: 4761fffc bz.d $w1,0 <test>
10: 7aa2081c fsune.d $w0,$w1,$w2
14: 4762fffa bz.d $w2,0 <test>
18: 7aa2081c fsune.d $w0,$w1,$w2
1c: 46020800 add.s $f0,$f1,$f2
20: 4760fff7 bz.d $w0,0 <test>
24: 00000000 nop
28: 4761fff5 bz.d $w1,0 <test>
2c: 46020800 add.s $f0,$f1,$f2
30: 4762fff3 bz.d $w2,0 <test>
34: 46020800 add.s $f0,$f1,$f2
38: 46241000 add.d $f0,$f2,$f4
3c: 4760fff0 bz.d $w0,0 <test>
40: 00000000 nop
44: 4761ffee bz.d $w1,0 <test>
48: 46241000 add.d $f0,$f2,$f4
4c: 4762ffec bz.d $w2,0 <test>
50: 46241000 add.d $f0,$f2,$f4
Any feedback? Which version is better? Thanks a lot!
Regards,
Chao-ying
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] Reorder MSA branches
2013-10-18 0:18 [PATCH] Reorder MSA branches Chao-Ying Fu
@ 2013-10-18 8:04 ` Richard Sandiford
2013-10-18 21:01 ` Chao-Ying Fu
0 siblings, 1 reply; 3+ messages in thread
From: Richard Sandiford @ 2013-10-18 8:04 UTC (permalink / raw)
To: Chao-Ying Fu
Cc: 'Maciej W. Rozycki', 'binutils@sourceware.org'
Chao-Ying Fu <Chao-Ying.Fu@imgtec.com> writes:
> Version 2.
> Because the MSA registers share the FP registers (if the FPU is present),
> we combine FP and MSA register dependences together.
I think we should go for this one. The patch looks good with the testcase
added to the testsuite.
One very minor formatting nit though:
> @@ -4161,7 +4161,8 @@ fpr_read_mask (const struct mips_cl_insn
> unsigned long pinfo;
> unsigned int mask;
>
> - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
> + mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC)
> + | (1 << OP_REG_MSA),
> insn_read_mask (ip->insn_mo));
> pinfo = ip->insn_mo->pinfo;
> /* Conservatively treat all operands to an FP_D instruction are doubles.
> @@ -4179,7 +4180,8 @@ fpr_write_mask (const struct mips_cl_ins
> unsigned long pinfo;
> unsigned int mask;
>
> - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
> + mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC)
> + | (1 << OP_REG_MSA),
> insn_write_mask (ip->insn_mo));
> pinfo = ip->insn_mo->pinfo;
> /* Conservatively treat all operands to an FP_D instruction are doubles.
In these two cases, please add an extra "(" (the GCC emacs indentation rule).
mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
| (1 << OP_REG_MSA)),
Thanks,
Richard
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] Reorder MSA branches
2013-10-18 8:04 ` Richard Sandiford
@ 2013-10-18 21:01 ` Chao-Ying Fu
0 siblings, 0 replies; 3+ messages in thread
From: Chao-Ying Fu @ 2013-10-18 21:01 UTC (permalink / raw)
To: 'Richard Sandiford'
Cc: 'Maciej W. Rozycki', 'binutils@sourceware.org'
Richard Sandiford wrote:
> Chao-Ying Fu <Chao-Ying.Fu@imgtec.com> writes:
> > Version 2.
> > Because the MSA registers share the FP registers (if the
> FPU is present),
> > we combine FP and MSA register dependences together.
>
> I think we should go for this one. The patch looks good with
> the testcase
> added to the testsuite.
Yes. Thanks!
>
> One very minor formatting nit though:
>
> > @@ -4161,7 +4161,8 @@ fpr_read_mask (const struct mips_cl_insn
> > unsigned long pinfo;
> > unsigned int mask;
> >
> > - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
> > + mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC)
> > + | (1 << OP_REG_MSA),
> > insn_read_mask (ip->insn_mo));
> > pinfo = ip->insn_mo->pinfo;
> > /* Conservatively treat all operands to an FP_D
> instruction are doubles.
> > @@ -4179,7 +4180,8 @@ fpr_write_mask (const struct mips_cl_ins
> > unsigned long pinfo;
> > unsigned int mask;
> >
> > - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC),
> > + mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC)
> > + | (1 << OP_REG_MSA),
> > insn_write_mask (ip->insn_mo));
> > pinfo = ip->insn_mo->pinfo;
> > /* Conservatively treat all operands to an FP_D
> instruction are doubles.
>
> In these two cases, please add an extra "(" (the GCC emacs
> indentation rule).
>
> mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC)
> | (1 << OP_REG_MSA)),
Yes. I will add "(" and ")", and check in the patch with new tests attached below. Thanks a lot!
Regards,
Chao-ying
2013-10-18 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
* gas/mips/micromips@msa-branch.d, gas/mips/msa-branch.d,
gas/mips/msa-branch.s: New.
* gas/mips/mips.exp: Run new tests.
Index: gas/mips/micromips@msa-branch.d
===================================================================
RCS file: gas/mips/micromips@msa-branch.d
diff -N gas/mips/micromips@msa-branch.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/mips/micromips@msa-branch.d 18 Oct 2013 20:54:46 -0000
@@ -0,0 +1,319 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA branch reorder
+#as: -32 -mmsa
+#source: msa-branch.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8360 fffe bz\.d \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8361 fffe bz\.d \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8362 fffe bz\.d \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8360 fffe bz\.d \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8361 fffe bz\.d \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8362 fffe bz\.d \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8360 fffe bz\.d \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8361 fffe bz\.d \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8362 fffe bz\.d \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8160 fffe bz\.v \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8161 fffe bz\.v \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8160 fffe bz\.v \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8161 fffe bz\.v \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8160 fffe bz\.v \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8161 fffe bz\.v \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test
+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4
+ \.\.\.
Index: gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.235
diff -u -p -r1.235 mips.exp
--- gas/mips/mips.exp 14 Oct 2013 19:06:20 -0000 1.235
+++ gas/mips/mips.exp 18 Oct 2013 20:54:46 -0000
@@ -1151,4 +1151,5 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "msa" [mips_arch_list_matching mips32r2]
run_dump_test_arches "msa64" [mips_arch_list_matching mips64r2]
run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
}
Index: gas/mips/msa-branch.d
===================================================================
RCS file: gas/mips/msa-branch.d
diff -N gas/mips/msa-branch.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/mips/msa-branch.d 18 Oct 2013 20:54:46 -0000
@@ -0,0 +1,228 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa
+#name: MSA branch reorder
+#as: -32 -mmsa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4700fffe bz\.b \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4701fffc bz\.b \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4702fffa bz\.b \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4700fff7 bz\.b \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4701fff5 bz\.b \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4702fff3 bz\.b \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4700fff0 bz\.b \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4701ffed bz\.b \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4702ffeb bz\.b \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4720ffe8 bz\.h \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4721ffe6 bz\.h \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4722ffe4 bz\.h \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4720ffe1 bz\.h \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4721ffdf bz\.h \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4722ffdd bz\.h \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4720ffda bz\.h \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4721ffd7 bz\.h \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4722ffd5 bz\.h \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4740ffd2 bz\.w \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4741ffd0 bz\.w \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4742ffce bz\.w \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4740ffcb bz\.w \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4741ffc9 bz\.w \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4742ffc7 bz\.w \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4740ffc4 bz\.w \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4741ffc1 bz\.w \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4742ffbf bz\.w \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4760ffbc bz\.d \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4761ffba bz\.d \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4762ffb8 bz\.d \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4760ffb5 bz\.d \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4761ffb3 bz\.d \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4762ffb1 bz\.d \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4760ffae bz\.d \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4761ffab bz\.d \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4762ffa9 bz\.d \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4560ffa6 bz\.v \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4561ffa4 bz\.v \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4562ffa2 bz\.v \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4560ff9f bz\.v \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4561ff9d bz\.v \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4562ff9b bz\.v \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4560ff98 bz\.v \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4561ff95 bz\.v \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4562ff93 bz\.v \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4780ff90 bnz\.b \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4781ff8e bnz\.b \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 4782ff8c bnz\.b \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4780ff89 bnz\.b \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4781ff87 bnz\.b \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4782ff85 bnz\.b \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4780ff82 bnz\.b \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 4781ff7f bnz\.b \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 4782ff7d bnz\.b \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47a0ff7a bnz\.h \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47a1ff78 bnz\.h \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47a2ff76 bnz\.h \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47a0ff73 bnz\.h \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47a1ff71 bnz\.h \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47a2ff6f bnz\.h \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47a0ff6c bnz\.h \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47a1ff69 bnz\.h \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47a2ff67 bnz\.h \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47c0ff64 bnz\.w \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47c1ff62 bnz\.w \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47c2ff60 bnz\.w \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47c0ff5d bnz\.w \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47c1ff5b bnz\.w \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47c2ff59 bnz\.w \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47c0ff56 bnz\.w \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47c1ff53 bnz\.w \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47c2ff51 bnz\.w \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47e0ff4e bnz\.d \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47e1ff4c bnz\.d \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 47e2ff4a bnz\.d \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47e0ff47 bnz\.d \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47e1ff45 bnz\.d \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 47e2ff43 bnz\.d \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47e0ff40 bnz\.d \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 47e1ff3d bnz\.d \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 47e2ff3b bnz\.d \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 45e0ff38 bnz\.v \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e1ff36 bnz\.v \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 45e2ff34 bnz\.v \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 45e0ff31 bnz\.v \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e1ff2f bnz\.v \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 45e2ff2d bnz\.v \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 45e0ff2a bnz\.v \$w0,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+[0-9a-f]+ <[^>]*> 45e1ff27 bnz\.v \$w1,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 00000000 nop
+[0-9a-f]+ <[^>]*> 45e2ff25 bnz\.v \$w2,[0-9a-f]+ <test>
+[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4
+ \.\.\.
Index: gas/mips/msa-branch.s
===================================================================
RCS file: gas/mips/msa-branch.s
diff -N gas/mips/msa-branch.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/mips/msa-branch.s 18 Oct 2013 20:54:46 -0000
@@ -0,0 +1,196 @@
+ .text
+ .set reorder
+test:
+ fsune.d $w0,$w1,$w2
+ bz.b $w0, test
+ fsune.d $w0,$w1,$w2
+ bz.b $w1, test
+ fsune.d $w0,$w1,$w2
+ bz.b $w2, test
+ add.s $f0,$f1,$f2
+ bz.b $w0, test
+ add.s $f0,$f1,$f2
+ bz.b $w1, test
+ add.s $f0,$f1,$f2
+ bz.b $w2, test
+ add.d $f0,$f2,$f4
+ bz.b $w0, test
+ add.d $f0,$f2,$f4
+ bz.b $w1, test
+ add.d $f0,$f2,$f4
+ bz.b $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bz.h $w0, test
+ fsune.d $w0,$w1,$w2
+ bz.h $w1, test
+ fsune.d $w0,$w1,$w2
+ bz.h $w2, test
+ add.s $f0,$f1,$f2
+ bz.h $w0, test
+ add.s $f0,$f1,$f2
+ bz.h $w1, test
+ add.s $f0,$f1,$f2
+ bz.h $w2, test
+ add.d $f0,$f2,$f4
+ bz.h $w0, test
+ add.d $f0,$f2,$f4
+ bz.h $w1, test
+ add.d $f0,$f2,$f4
+ bz.h $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bz.w $w0, test
+ fsune.d $w0,$w1,$w2
+ bz.w $w1, test
+ fsune.d $w0,$w1,$w2
+ bz.w $w2, test
+ add.s $f0,$f1,$f2
+ bz.w $w0, test
+ add.s $f0,$f1,$f2
+ bz.w $w1, test
+ add.s $f0,$f1,$f2
+ bz.w $w2, test
+ add.d $f0,$f2,$f4
+ bz.w $w0, test
+ add.d $f0,$f2,$f4
+ bz.w $w1, test
+ add.d $f0,$f2,$f4
+ bz.w $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bz.d $w0, test
+ fsune.d $w0,$w1,$w2
+ bz.d $w1, test
+ fsune.d $w0,$w1,$w2
+ bz.d $w2, test
+ add.s $f0,$f1,$f2
+ bz.d $w0, test
+ add.s $f0,$f1,$f2
+ bz.d $w1, test
+ add.s $f0,$f1,$f2
+ bz.d $w2, test
+ add.d $f0,$f2,$f4
+ bz.d $w0, test
+ add.d $f0,$f2,$f4
+ bz.d $w1, test
+ add.d $f0,$f2,$f4
+ bz.d $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bz.v $w0, test
+ fsune.d $w0,$w1,$w2
+ bz.v $w1, test
+ fsune.d $w0,$w1,$w2
+ bz.v $w2, test
+ add.s $f0,$f1,$f2
+ bz.v $w0, test
+ add.s $f0,$f1,$f2
+ bz.v $w1, test
+ add.s $f0,$f1,$f2
+ bz.v $w2, test
+ add.d $f0,$f2,$f4
+ bz.v $w0, test
+ add.d $f0,$f2,$f4
+ bz.v $w1, test
+ add.d $f0,$f2,$f4
+ bz.v $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bnz.b $w0, test
+ fsune.d $w0,$w1,$w2
+ bnz.b $w1, test
+ fsune.d $w0,$w1,$w2
+ bnz.b $w2, test
+ add.s $f0,$f1,$f2
+ bnz.b $w0, test
+ add.s $f0,$f1,$f2
+ bnz.b $w1, test
+ add.s $f0,$f1,$f2
+ bnz.b $w2, test
+ add.d $f0,$f2,$f4
+ bnz.b $w0, test
+ add.d $f0,$f2,$f4
+ bnz.b $w1, test
+ add.d $f0,$f2,$f4
+ bnz.b $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bnz.h $w0, test
+ fsune.d $w0,$w1,$w2
+ bnz.h $w1, test
+ fsune.d $w0,$w1,$w2
+ bnz.h $w2, test
+ add.s $f0,$f1,$f2
+ bnz.h $w0, test
+ add.s $f0,$f1,$f2
+ bnz.h $w1, test
+ add.s $f0,$f1,$f2
+ bnz.h $w2, test
+ add.d $f0,$f2,$f4
+ bnz.h $w0, test
+ add.d $f0,$f2,$f4
+ bnz.h $w1, test
+ add.d $f0,$f2,$f4
+ bnz.h $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bnz.w $w0, test
+ fsune.d $w0,$w1,$w2
+ bnz.w $w1, test
+ fsune.d $w0,$w1,$w2
+ bnz.w $w2, test
+ add.s $f0,$f1,$f2
+ bnz.w $w0, test
+ add.s $f0,$f1,$f2
+ bnz.w $w1, test
+ add.s $f0,$f1,$f2
+ bnz.w $w2, test
+ add.d $f0,$f2,$f4
+ bnz.w $w0, test
+ add.d $f0,$f2,$f4
+ bnz.w $w1, test
+ add.d $f0,$f2,$f4
+ bnz.w $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bnz.d $w0, test
+ fsune.d $w0,$w1,$w2
+ bnz.d $w1, test
+ fsune.d $w0,$w1,$w2
+ bnz.d $w2, test
+ add.s $f0,$f1,$f2
+ bnz.d $w0, test
+ add.s $f0,$f1,$f2
+ bnz.d $w1, test
+ add.s $f0,$f1,$f2
+ bnz.d $w2, test
+ add.d $f0,$f2,$f4
+ bnz.d $w0, test
+ add.d $f0,$f2,$f4
+ bnz.d $w1, test
+ add.d $f0,$f2,$f4
+ bnz.d $w2, test
+
+ fsune.d $w0,$w1,$w2
+ bnz.v $w0, test
+ fsune.d $w0,$w1,$w2
+ bnz.v $w1, test
+ fsune.d $w0,$w1,$w2
+ bnz.v $w2, test
+ add.s $f0,$f1,$f2
+ bnz.v $w0, test
+ add.s $f0,$f1,$f2
+ bnz.v $w1, test
+ add.s $f0,$f1,$f2
+ bnz.v $w2, test
+ add.d $f0,$f2,$f4
+ bnz.v $w0, test
+ add.d $f0,$f2,$f4
+ bnz.v $w1, test
+ add.d $f0,$f2,$f4
+ bnz.v $w2, test
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
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2013-10-18 0:18 [PATCH] Reorder MSA branches Chao-Ying Fu
2013-10-18 8:04 ` Richard Sandiford
2013-10-18 21:01 ` Chao-Ying Fu
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