* PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bits
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (15 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 349 bytes --]
Hi all,
fifth patch of the series adding support for PACBTI for Cortex-M.
As all the bits in the 'core' field of 'arm_feature_set' struct are
in use this adding a third element to it and is updating the accessor
macros we have. This is in order to support the following patch that
adds "-march=armv8.1-m.main+pacbti" flag.
Regards
Andrea
[-- Attachment #2: 0005-PATCH-5-10-arm-Extend-again-arm_feature_set-struct-t.patch --]
[-- Type: text/plain, Size: 3618 bytes --]
From 5f466825eb8240711888c9d32c67ef81be494b47 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Thu, 3 Jun 2021 16:48:05 +0200
Subject: [PATCH 05/10] PATCH [5/10] arm: Extend again arm_feature_set struct
to provide more bits
include/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* opcode/arm.h (arm_feature_set): Extend 'core' field.
(ARM_CPU_HAS_FEATURE, ARM_FSET_CPU_SUBSET, ARM_CPU_IS_ANY)
(ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, ARM_FEATURE_EQUAL)
(ARM_FEATURE_ZERO, ARM_FEATURE_CORE_EQUAL): Account for
'core[2]'.
(ARM_FEATURE_CORE_HIGH_HIGH): New macro.
---
include/opcode/arm.h | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 90c09a70658..1152e781222 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -427,7 +427,7 @@
and use macro ARM_FEATURE to initialize the feature set variable. */
typedef struct
{
- unsigned long core[2];
+ unsigned long core[3];
unsigned long coproc;
} arm_feature_set;
@@ -435,23 +435,27 @@ typedef struct
#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
(((CPU).core[0] & (FEAT).core[0]) != 0 \
|| ((CPU).core[1] & (FEAT).core[1]) != 0 \
+ || ((CPU).core[2] & (FEAT).core[2]) != 0 \
|| ((CPU).coproc & (FEAT).coproc) != 0)
/* Tests whether the features of A are a subset of B. */
#define ARM_FSET_CPU_SUBSET(A,B) \
(((A).core[0] & (B).core[0]) == (A).core[0] \
&& ((A).core[1] & (B).core[1]) == (A).core[1] \
+ && ((A).core[2] & (B).core[2]) == (A).core[2] \
&& ((A).coproc & (B).coproc) == (A).coproc)
#define ARM_CPU_IS_ANY(CPU) \
((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \
- && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1])
+ && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1] \
+ && (CPU).core[2] == ((arm_feature_set)ARM_ANY).core[2])
#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
do \
{ \
(TARG).core[0] = (F1).core[0] | (F2).core[0]; \
(TARG).core[1] = (F1).core[1] | (F2).core[1]; \
+ (TARG).core[2] = (F1).core[2] | (F2).core[2]; \
(TARG).coproc = (F1).coproc | (F2).coproc; \
} \
while (0)
@@ -461,6 +465,7 @@ typedef struct
{ \
(TARG).core[0] = (F1).core[0] &~ (F2).core[0]; \
(TARG).core[1] = (F1).core[1] &~ (F2).core[1]; \
+ (TARG).core[2] = (F1).core[2] &~ (F2).core[2]; \
(TARG).coproc = (F1).coproc &~ (F2).coproc; \
} \
while (0)
@@ -468,17 +473,24 @@ typedef struct
#define ARM_FEATURE_EQUAL(T1,T2) \
( (T1).core[0] == (T2).core[0] \
&& (T1).core[1] == (T2).core[1] \
+ && (T1).core[2] == (T2).core[2] \
&& (T1).coproc == (T2).coproc)
#define ARM_FEATURE_ZERO(T) \
- ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0)
+ ((T).core[0] == 0 \
+ && (T).core[1] == 0 \
+ && (T).core[2] == 0 \
+ && (T).coproc == 0)
#define ARM_FEATURE_CORE_EQUAL(T1, T2) \
- ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1])
+ ((T1).core[0] == (T2).core[0] \
+ && (T1).core[1] == (T2).core[1] \
+ && (T1).core[2] == (T2).core[2])
#define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)}
#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0}
#define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0}
#define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0}
+#define ARM_FEATURE_CORE_HIGH_HIGH(core) {{0, 0, (core)}, 0}
#define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)}
#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)}
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
2021-07-20 15:38 ` PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bits Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [8/10] arm: add 'autg' " Andrea Corallo
` (14 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 559 bytes --]
Hi all,
seventh patch of the series adding support for PACBTI for Cortex-M.
This is to add the 'bxaut' instruction.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0007-PATCH-7-10-arm-add-bxaut-instruction-for-Armv8.1-M-p.patch --]
[-- Type: text/plain, Size: 3970 bytes --]
From 86ca3e580342a231b50cdadd10034c771b178eb1 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Wed, 19 May 2021 15:04:24 +0200
Subject: [PATCH 07/10] PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M
pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_bxaut'.
(do_t_pacbti_nonop): New function.
(insns): Define 'bxaut' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'bxaut'.
---
| 14 ++++++++++++++
| 3 ++-
| 1 +
| 2 ++
4 files changed, 19 insertions(+), 1 deletion(-)
--git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3ec353abf78..30ef1991249 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11463,6 +11463,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_bflx, 0000, f070e001), \
X(_bic, 4380, ea200000), \
X(_bics, 4380, ea300000), \
+ X(_bxaut, 0000, fb500f10), \
X(_cinc, 0000, ea509000), \
X(_cinv, 0000, ea50a000), \
X(_cmn, 42c0, eb100f00), \
@@ -22343,6 +22344,18 @@ do_t_pacbti (void)
inst.instruction = THUMB_OP32 (inst.instruction);
}
+static void
+do_t_pacbti_nonop (void)
+{
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext),
+ _(BAD_PACBTI));
+
+ inst.instruction = THUMB_OP32 (inst.instruction);
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+}
+
\f
/* Overall per-instruction processing. */
@@ -26333,6 +26346,7 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8_1m_main
toU("aut", _aut, 3, (R12, LR, SP), t_pacbti),
ToU("bti", f3af800f, 0, (), noargs),
+ toU("bxaut", _bxaut, 3, (RR, RR, RR), t_pacbti_nonop),
toU("pac", _pac, 3, (R12, LR, SP), t_pacbti),
toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
--git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 9df123af8eb..411454a5fd1 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -1,6 +1,6 @@
#name: Valid Armv8.1-M pointer authentication and branch target identification extention
#source: armv8_1-m-pacbti.s
-#as: -march=armv8.1-m.main
+#as: -march=armv8.1-m.main+pacbti
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
@@ -10,4 +10,5 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 800d pacbti r12, lr, sp
0[0-9a-f]+ <[^>]+> f3af 802d aut r12, lr, sp
0[0-9a-f]+ <[^>]+> f3af 801d pac r12, lr, sp
+0[0-9a-f]+ <[^>]+> fb54 3f15 bxaut r3, r4, r5
#...
--git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 38000c3fc0d..22da2cefb4e 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -6,3 +6,4 @@
pacbti r12, lr, sp
aut r12, lr, sp
pac r12, lr, sp
+ bxaut r3, r4, r5
--git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 930fbbfa385..1d183605030 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4658,6 +4658,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800f, 0xffffffff, "bti"},
+ {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+ 0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
2021-07-20 15:38 ` PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bits Andrea Corallo
2021-07-20 15:38 ` PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extension Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flag Andrea Corallo
` (13 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 557 bytes --]
Hi all,
eighth patch of the series adding support for PACBTI for Cortex-M.
This is to add the 'autg' instruction.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0008-PATCH-8-10-arm-add-autg-instruction-for-Armv8.1-M-pa.patch --]
[-- Type: text/plain, Size: 3078 bytes --]
From 7a07e27c0219f430ab4eabf9062c1bdd2bff9e35 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Tue, 8 Jun 2021 15:22:12 +0200
Subject: [PATCH 08/10] PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M
pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_autg'.
(insns): Define 'autg' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'autg'.
---
gas/config/tc-arm.c | 2 ++
gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 +
gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 +
opcodes/arm-dis.c | 2 ++
4 files changed, 6 insertions(+)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 30ef1991249..cd65b25601e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11454,6 +11454,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_asr, 1000, fa40f000), \
X(_asrs, 1000, fa50f000), \
X(_aut, 0000, f3af802d), \
+ X(_autg, 0000, fb500f00), \
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
@@ -26345,6 +26346,7 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
toU("aut", _aut, 3, (R12, LR, SP), t_pacbti),
+ toU("autg", _autg, 3, (RR, RR, RR), t_pacbti_nonop),
ToU("bti", f3af800f, 0, (), noargs),
toU("bxaut", _bxaut, 3, (RR, RR, RR), t_pacbti_nonop),
toU("pac", _pac, 3, (R12, LR, SP), t_pacbti),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 411454a5fd1..6ddf218c9f9 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -11,4 +11,5 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 802d aut r12, lr, sp
0[0-9a-f]+ <[^>]+> f3af 801d pac r12, lr, sp
0[0-9a-f]+ <[^>]+> fb54 3f15 bxaut r3, r4, r5
+0[0-9a-f]+ <[^>]+> fb54 3f05 autg r3, r4, r5
#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 22da2cefb4e..eccd5797ed7 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -7,3 +7,4 @@
aut r12, lr, sp
pac r12, lr, sp
bxaut r3, r4, r5
+ autg r3, r4, r5
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 1d183605030..d54cfa8fe84 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4656,6 +4656,8 @@ static const struct opcode32 thumb32_opcodes[] =
Identification Extension. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
+ {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+ 0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800f, 0xffffffff, "bti"},
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flag
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (2 preceding siblings ...)
2021-07-20 15:38 ` PATCH [8/10] arm: add 'autg' " Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti Andrea Corallo
` (12 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 512 bytes --]
Hi all,
sixth patch of the series adding support for PACBTI for Cortex-M.
This is to add the -march=armv8.1-m.main+pacbti flag.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0006-PATCH-6-10-arm-Add-march-armv8.1-m.main-pacbti-flag.patch --]
[-- Type: text/plain, Size: 2982 bytes --]
From a1a693d81c8291788428e9bc2a2b5e5b48f181f1 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Fri, 4 Jun 2021 10:17:17 +0200
Subject: [PATCH 06/10] PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flag
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (pacbti_ext): Define.
(BAD_PACBTI): New macro.
(armv8_1m_main_ext_table): Add 'pacbti' extension.
include/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* opcode/arm.h (ARM_EXT3_PACBTI, ARM_AEXT3_V8_1M_MAIN_PACBTI): New
macro.
---
gas/config/tc-arm.c | 4 ++++
include/opcode/arm.h | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 6ef0cd97a5e..3ec353abf78 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -365,6 +365,8 @@ static const arm_feature_set fpu_neon_ext_v8_1 =
ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
static const arm_feature_set fpu_neon_ext_dotprod =
ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
+static const arm_feature_set pacbti_ext =
+ ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI);
static int mfloat_abi_opt = -1;
/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
@@ -945,6 +947,7 @@ struct asm_opcode
"and source operands makes instruction UNPREDICTABLE")
#define BAD_EL_TYPE _("bad element type for instruction")
#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
+#define BAD_PACBTI _("selected processor does not support PACBTI extention")
static htab_t arm_ops_hsh;
static htab_t arm_cond_hsh;
@@ -31934,6 +31937,7 @@ static const struct arm_ext_table armv8_1m_main_ext_table[] =
ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
CDE_EXTENSIONS,
+ ARM_ADD ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_AEXT3_V8_1M_MAIN_PACBTI)),
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
};
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index 1152e781222..4a6044f6f68 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -90,6 +90,11 @@
#define ARM_EXT2_CDE7 0x40000000 /* Using CDE coproc 7. */
#define ARM_EXT2_V8R 0x80000000 /* Arm V8R. */
+#define ARM_EXT3_PACBTI 0x00000001 /* Arm v8-M Mainline Pointer
+ Authentication and Branch
+ Target Identification
+ Extension. */
+
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
@@ -197,6 +202,8 @@
#define ARM_AEXT2_V8_1M_MAIN (ARM_AEXT2_V8M_MAIN | ARM_EXT2_V8_1M_MAIN \
| ARM_EXT2_FP16_INST)
+#define ARM_AEXT3_V8_1M_MAIN_PACBTI (ARM_AEXT2_V8M_MAIN | ARM_EXT3_PACBTI)
+
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
#define ARM_ARCH_IWMMXT \
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (3 preceding siblings ...)
2021-07-20 15:38 ` PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flag Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (11 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 625 bytes --]
Hi all,
last patch of the series adding support for PACBTI for Cortex-M.
This is to alias r12 to 'ra_auth_code' as this is used to store the signed return
address of each function.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0010-PATCH-10-10-arm-Alias-ra_auth_code-to-r12-for-pacbti.patch --]
[-- Type: text/plain, Size: 857 bytes --]
From 5c852c7e94d15cb509cb924a16cd560c4db1cba1 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Fri, 11 Jun 2021 09:53:09 +0200
Subject: [PATCH 10/10] PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for
pacbti.
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (reg_names): Alias 'ra_auth_code' to r12.
---
gas/config/tc-arm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 40e9d2e02f2..c9e65582b17 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -23957,6 +23957,9 @@ static const struct reg_entry reg_names[] =
/* XScale accumulator registers. */
REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
+
+ /* Alias 'ra_auth_code' to r12 for pacbti. */
+ REGDEF(ra_auth_code,12,RN),
};
#undef REGDEF
#undef REGNUM
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (4 preceding siblings ...)
2021-07-20 15:38 ` PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [3/4] arm: Add Tag_BTI_use build attribute Andrea Corallo
` (10 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 556 bytes --]
Hi all,
ninth patch of the series adding support for PACBTI for Cortex-M.
This is to add the 'pacg' instruction.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0009-PATCH-9-10-arm-add-pacg-instruction-for-Armv8.1-M-pa.patch --]
[-- Type: text/plain, Size: 3699 bytes --]
From 9f8ad24c49a405f5503dde2487d952df8efbda5e Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Tue, 8 Jun 2021 19:03:29 +0200
Subject: [PATCH 09/10] PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M
pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_pacg'.
(do_t_pacbti_pacg): New function.
(insns): Define 'pacg' insn.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pacg'.
---
gas/config/tc-arm.c | 14 ++++++++++++++
gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 +
gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 +
opcodes/arm-dis.c | 2 ++
4 files changed, 18 insertions(+)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index cd65b25601e..40e9d2e02f2 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11513,6 +11513,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_orrs, 4300, ea500000), \
X(_pac, 0000, f3af801d), \
X(_pacbti, 0000, f3af800d), \
+ X(_pacg, 0000, fb60f000), \
X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
X(_push, b400, e92d0000), /* stmdb sp!,... */ \
X(_rev, ba00, fa90f080), \
@@ -22357,6 +22358,18 @@ do_t_pacbti_nonop (void)
inst.instruction |= inst.operands[2].reg;
}
+static void
+do_t_pacbti_pacg (void)
+{
+ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext),
+ _(BAD_PACBTI));
+
+ inst.instruction = THUMB_OP32 (inst.instruction);
+ inst.instruction |= inst.operands[0].reg << 8;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= inst.operands[2].reg;
+}
+
\f
/* Overall per-instruction processing. */
@@ -26351,6 +26364,7 @@ static const struct asm_opcode insns[] =
toU("bxaut", _bxaut, 3, (RR, RR, RR), t_pacbti_nonop),
toU("pac", _pac, 3, (R12, LR, SP), t_pacbti),
toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
+ toU("pacg", _pacg, 3, (RR, RR, RR), t_pacbti_pacg),
toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 6ddf218c9f9..2e7082216ce 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -12,4 +12,5 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 801d pac r12, lr, sp
0[0-9a-f]+ <[^>]+> fb54 3f15 bxaut r3, r4, r5
0[0-9a-f]+ <[^>]+> fb54 3f05 autg r3, r4, r5
+0[0-9a-f]+ <[^>]+> fb64 f305 pacg r3, r4, r5
#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index eccd5797ed7..8d3a4a44c1c 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -8,3 +8,4 @@
pac r12, lr, sp
bxaut r3, r4, r5
autg r3, r4, r5
+ pacg r3, r4, r5
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index d54cfa8fe84..faabd42b5b3 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4666,6 +4666,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
+ {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+ 0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
instructions. */
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [3/4] arm: Add Tag_BTI_use build attribute
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (5 preceding siblings ...)
2021-07-20 15:38 ` PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [2/4] arm: Add Tag_BTI_extension " Andrea Corallo
` (9 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 650 bytes --]
Hi all,
third patch of the series adding 'Tag_BTI_use' build attribute
support.
Here follows its semantic:
0 This code is compiled without branch target enforcement
1 This code is compiled with branch target enforcement
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
Regtested clean on current master.
Best Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0003-PATCH-3-4-arm-Add-Tag_BTI_use-build-attribute.patch --]
[-- Type: text/plain, Size: 3524 bytes --]
From 853ada30059936dd1b1541edc939b895c351de49 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Mon, 5 Jul 2021 17:14:47 +0200
Subject: [PATCH 3/4] PATCH [3/4] arm: Add Tag_BTI_use build attribute
bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_BTI_use' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_BTI_use' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_BTI_use' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_use'.
---
bfd/elf32-arm.c | 1 +
binutils/readelf.c | 5 +++++
elfcpp/arm.h | 1 +
gas/config/tc-arm.c | 1 +
include/elf/arm.h | 1 +
5 files changed, 9 insertions(+)
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 73061047e29..98f92401942 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -14614,6 +14614,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
case Tag_MVE_arch:
case Tag_PAC_extension:
case Tag_BTI_extension:
+ case Tag_BTI_use:
/* Use the largest value specified. */
if (in_attr[i].i > out_attr[i].i)
out_attr[i].i = in_attr[i].i;
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 9091a44eac4..993f3160ab6 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -16149,6 +16149,10 @@ static const char * arm_attr_tag_BTI_extension[] =
"BTI instructions permitted in the NOP space",
"BTI instructions permitted in the NOP and in the non-NOP space"};
+static const char * arm_attr_tag_BTI_use[] =
+ {"Compiled without branch target enforcement",
+ "Compiled with branch target enforcement"};
+
#define LOOKUP(id, name) \
{id, #name, 0x80 | ARRAY_SIZE(arm_attr_tag_##name), arm_attr_tag_##name}
static arm_attr_public_tag arm_attr_public_tags[] =
@@ -16191,6 +16195,7 @@ static arm_attr_public_tag arm_attr_public_tags[] =
LOOKUP(48, MVE_arch),
LOOKUP(50, PAC_extension),
LOOKUP(52, BTI_extension),
+ LOOKUP(74, BTI_use),
{64, "nodefaults", 0, NULL},
{65, "also_compatible_with", 0, NULL},
LOOKUP(66, T2EE_use),
diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index 42144ce13be..12ba3fa7a1e 100644
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -308,6 +308,7 @@ enum
Tag_MVE_arch = 48,
Tag_PAC_extension = 50,
Tag_BTI_extension = 52,
+ Tag_BTI_use = 74,
Tag_nodefaults = 64,
Tag_also_compatible_with = 65,
Tag_T2EE_use = 66,
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 0ad1219ba9c..6248adccf2d 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -33561,6 +33561,7 @@ arm_convert_symbolic_attribute (const char *name)
T (Tag_MVE_arch),
T (Tag_PAC_extension),
T (Tag_BTI_extension),
+ T (Tag_BTI_use),
/* We deliberately do not include Tag_MPextension_use_legacy. */
#undef T
};
diff --git a/include/elf/arm.h b/include/elf/arm.h
index eb2ae9f4301..0f6e734e6d0 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -329,6 +329,7 @@ enum
Tag_MVE_arch = 48,
Tag_PAC_extension = 50,
Tag_BTI_extension = 52,
+ Tag_BTI_use = 74,
Tag_nodefaults = 64,
Tag_also_compatible_with,
Tag_T2EE_use,
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [2/4] arm: Add Tag_BTI_extension build attribute
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (6 preceding siblings ...)
2021-07-20 15:38 ` PATCH [3/4] arm: Add Tag_BTI_use build attribute Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [4/4] arm: Add Tag_PACRET_use " Andrea Corallo
` (8 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 775 bytes --]
Hi all,
second patch of the series adding 'Tag_BTI_extension' build attribute
support.
Here follows its semantic:
0 The user did not permit this entity to use BTI instructions
1 The user permitted this entity to use BTI instructions in the NOP space
2 The user permitted this entity to use BTI instructions in the NOP and in the non-NOP space
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
Regtested clean on current master.
Best Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0002-PATCH-2-4-arm-Add-Tag_BTI_extension-build-attribute.patch --]
[-- Type: text/plain, Size: 3658 bytes --]
From a9888c54abba17d87a64a3be509d12b848c2378a Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Mon, 5 Jul 2021 16:37:19 +0200
Subject: [PATCH 2/4] PATCH [2/4] arm: Add Tag_BTI_extension build attribute
bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_BTI_extension' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_BTI_extension' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_BTI_extension' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_BTI_extension'.
---
bfd/elf32-arm.c | 1 +
binutils/readelf.c | 6 ++++++
elfcpp/arm.h | 1 +
gas/config/tc-arm.c | 1 +
include/elf/arm.h | 1 +
5 files changed, 10 insertions(+)
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bb4ba89357e..73061047e29 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -14613,6 +14613,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
case Tag_MPextension_use:
case Tag_MVE_arch:
case Tag_PAC_extension:
+ case Tag_BTI_extension:
/* Use the largest value specified. */
if (in_attr[i].i > out_attr[i].i)
out_attr[i].i = in_attr[i].i;
diff --git a/binutils/readelf.c b/binutils/readelf.c
index cccc17afc3f..9091a44eac4 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -16144,6 +16144,11 @@ static const char * arm_attr_tag_PAC_extension[] =
"PAC/AUT instructions permitted in the NOP space",
"PAC/AUT instructions permitted in the NOP and in the non-NOP space"};
+static const char * arm_attr_tag_BTI_extension[] =
+ {"BTI instructions not permitted",
+ "BTI instructions permitted in the NOP space",
+ "BTI instructions permitted in the NOP and in the non-NOP space"};
+
#define LOOKUP(id, name) \
{id, #name, 0x80 | ARRAY_SIZE(arm_attr_tag_##name), arm_attr_tag_##name}
static arm_attr_public_tag arm_attr_public_tags[] =
@@ -16185,6 +16190,7 @@ static arm_attr_public_tag arm_attr_public_tags[] =
LOOKUP(46, DSP_extension),
LOOKUP(48, MVE_arch),
LOOKUP(50, PAC_extension),
+ LOOKUP(52, BTI_extension),
{64, "nodefaults", 0, NULL},
{65, "also_compatible_with", 0, NULL},
LOOKUP(66, T2EE_use),
diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index ce682a5bdc6..42144ce13be 100644
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -307,6 +307,7 @@ enum
Tag_DIV_use = 44,
Tag_MVE_arch = 48,
Tag_PAC_extension = 50,
+ Tag_BTI_extension = 52,
Tag_nodefaults = 64,
Tag_also_compatible_with = 65,
Tag_T2EE_use = 66,
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 9213134eb55..0ad1219ba9c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -33560,6 +33560,7 @@ arm_convert_symbolic_attribute (const char *name)
T (Tag_DSP_extension),
T (Tag_MVE_arch),
T (Tag_PAC_extension),
+ T (Tag_BTI_extension),
/* We deliberately do not include Tag_MPextension_use_legacy. */
#undef T
};
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 27b676860dd..eb2ae9f4301 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -328,6 +328,7 @@ enum
Tag_DSP_extension = 46,
Tag_MVE_arch = 48,
Tag_PAC_extension = 50,
+ Tag_BTI_extension = 52,
Tag_nodefaults = 64,
Tag_also_compatible_with,
Tag_T2EE_use,
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [4/4] arm: Add Tag_PACRET_use build attribute
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (7 preceding siblings ...)
2021-07-20 15:38 ` PATCH [2/4] arm: Add Tag_BTI_extension " Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (7 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 684 bytes --]
Hi all,
last patch of the series adding 'Tag_PACRET_use' build attribute
support.
Here follows its semantic:
0 This code is compiled without return address signing and authentication
1 This code is compiled with return address signing and authentication
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
Regtested clean on current master.
Best Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0004-PATCH-4-4-arm-Add-Tag_PACRET_use-build-attribute.patch --]
[-- Type: text/plain, Size: 3554 bytes --]
From 5e2aa6357180ace750e80856acd1370b07118567 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Mon, 5 Jul 2021 17:27:00 +0200
Subject: [PATCH 4/4] PATCH [4/4] arm: Add Tag_PACRET_use build attribute
bfd/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add
'Tag_PACRET_use' case.
binutils/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* readelf.c (arm_attr_tag_PAC_extension): Declare.
(arm_attr_public_tags): Add 'PAC_extension' lookup.
elfcpp/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* arm.h: Define 'Tag_PACRET_use' enum.
gas/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (arm_convert_symbolic_attribute): Add
'Tag_PACRET_use' to the attribute_table.
include/
2021-07-06 Andrea Corallo <andrea.corallo@arm.com>
* elf/arm.h (elf_arm_reloc_type): Add 'Tag_PACRET_use'.
---
bfd/elf32-arm.c | 1 +
binutils/readelf.c | 5 +++++
elfcpp/arm.h | 1 +
gas/config/tc-arm.c | 1 +
include/elf/arm.h | 1 +
5 files changed, 9 insertions(+)
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 98f92401942..2cb8768868b 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -14615,6 +14615,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
case Tag_PAC_extension:
case Tag_BTI_extension:
case Tag_BTI_use:
+ case Tag_PACRET_use:
/* Use the largest value specified. */
if (in_attr[i].i > out_attr[i].i)
out_attr[i].i = in_attr[i].i;
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 993f3160ab6..9fbb9e7a852 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -16153,6 +16153,10 @@ static const char * arm_attr_tag_BTI_use[] =
{"Compiled without branch target enforcement",
"Compiled with branch target enforcement"};
+static const char * arm_attr_tag_PACRET_use[] =
+ {"Compiled without return address signing and authentication",
+ "Compiled with return address signing and authentication"};
+
#define LOOKUP(id, name) \
{id, #name, 0x80 | ARRAY_SIZE(arm_attr_tag_##name), arm_attr_tag_##name}
static arm_attr_public_tag arm_attr_public_tags[] =
@@ -16196,6 +16200,7 @@ static arm_attr_public_tag arm_attr_public_tags[] =
LOOKUP(50, PAC_extension),
LOOKUP(52, BTI_extension),
LOOKUP(74, BTI_use),
+ LOOKUP(76, PACRET_use),
{64, "nodefaults", 0, NULL},
{65, "also_compatible_with", 0, NULL},
LOOKUP(66, T2EE_use),
diff --git a/elfcpp/arm.h b/elfcpp/arm.h
index 12ba3fa7a1e..db549a8ee68 100644
--- a/elfcpp/arm.h
+++ b/elfcpp/arm.h
@@ -309,6 +309,7 @@ enum
Tag_PAC_extension = 50,
Tag_BTI_extension = 52,
Tag_BTI_use = 74,
+ Tag_PACRET_use = 76,
Tag_nodefaults = 64,
Tag_also_compatible_with = 65,
Tag_T2EE_use = 66,
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 6248adccf2d..16959fa540c 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -33562,6 +33562,7 @@ arm_convert_symbolic_attribute (const char *name)
T (Tag_PAC_extension),
T (Tag_BTI_extension),
T (Tag_BTI_use),
+ T (Tag_PACRET_use),
/* We deliberately do not include Tag_MPextension_use_legacy. */
#undef T
};
diff --git a/include/elf/arm.h b/include/elf/arm.h
index 0f6e734e6d0..299f394b7ae 100644
--- a/include/elf/arm.h
+++ b/include/elf/arm.h
@@ -330,6 +330,7 @@ enum
Tag_PAC_extension = 50,
Tag_BTI_extension = 52,
Tag_BTI_use = 74,
+ Tag_PACRET_use = 76,
Tag_nodefaults = 64,
Tag_also_compatible_with,
Tag_T2EE_use,
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (8 preceding siblings ...)
2021-07-20 15:38 ` PATCH [4/4] arm: Add Tag_PACRET_use " Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH V2 [2/10] arm: add 'pacbti' " Andrea Corallo
` (6 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 555 bytes --]
Hi all,
forth patch of the series adding support for PACBTI for Cortex-M.
This is to add the 'pac' instruction.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0004-PATCH-4-10-arm-add-pac-instruction-for-Armv8.1-M-pac.patch --]
[-- Type: text/plain, Size: 4314 bytes --]
From e533b632d067cbee9a64e54754f48b10ef7f482a Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Wed, 19 May 2021 09:51:40 +0200
Subject: [PATCH 04/10] PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M
pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (T16_32_TAB): Add '_pac'.
(insns): Add 'pac' insn.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add pac tests.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pac'.
---
gas/config/tc-arm.c | 2 ++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l | 3 +++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s | 3 +++
gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 +
gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 +
opcodes/arm-dis.c | 2 ++
6 files changed, 12 insertions(+)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b5d23357fc0..6ef0cd97a5e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11506,6 +11506,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_negs, 4240, f1d00000), /* rsbs #0 */ \
X(_orr, 4300, ea400000), \
X(_orrs, 4300, ea500000), \
+ X(_pac, 0000, f3af801d), \
X(_pacbti, 0000, f3af800d), \
X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
X(_push, b400, e92d0000), /* stmdb sp!,... */ \
@@ -26329,6 +26330,7 @@ static const struct asm_opcode insns[] =
#define THUMB_VARIANT & arm_ext_v8_1m_main
toU("aut", _aut, 3, (R12, LR, SP), t_pacbti),
ToU("bti", f3af800f, 0, (), noargs),
+ toU("pac", _pac, 3, (R12, LR, SP), t_pacbti),
toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
index 317e62f731b..f6f0d41ac71 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
@@ -5,3 +5,6 @@
.*:9: Error: operand must be r12 -- `aut r11,lr,sp'
.*:10: Error: operand must be LR register -- `aut r12,r10,sp'
.*:11: Error: operand must be SP register -- `aut r12,lr,r10'
+.*:12: Error: operand must be r12 -- `pac r11,lr,sp'
+.*:13: Error: operand must be LR register -- `pac r12,r10,sp'
+.*:14: Error: operand must be SP register -- `pac r12,lr,r10'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
index c2ad20455c7..4948f855534 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
@@ -9,3 +9,6 @@
aut r11, lr, sp
aut r12, r10, sp
aut r12, lr, r10
+ pac r11, lr, sp
+ pac r12, r10, sp
+ pac r12, lr, r10
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index fe11d7eb036..9df123af8eb 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -9,4 +9,5 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 800f bti
0[0-9a-f]+ <[^>]+> f3af 800d pacbti r12, lr, sp
0[0-9a-f]+ <[^>]+> f3af 802d aut r12, lr, sp
+0[0-9a-f]+ <[^>]+> f3af 801d pac r12, lr, sp
#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 14b0414a59b..38000c3fc0d 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -5,3 +5,4 @@
bti
pacbti r12, lr, sp
aut r12, lr, sp
+ pac r12, lr, sp
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 8eeb303630b..930fbbfa385 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4658,6 +4658,8 @@ static const struct opcode32 thumb32_opcodes[] =
0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800f, 0xffffffff, "bti"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH V2 [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (9 preceding siblings ...)
2021-07-20 15:38 ` PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extension Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-20 15:38 ` PATCH [3/10] arm: add 'aut' " Andrea Corallo
` (5 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw, Nick Clifton
[-- Attachment #1: Type: text/plain, Size: 666 bytes --]
Hi all,
second patch of the series adding support for PACBTI for Cortex-M.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
This is to add the 'pacbti' instruction.
This version is incorporating Nick suggestion to skip the
armv8_1-m-pacbti-bad test on PE format targets.
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0001-PATCH-2-10-arm-add-pacbti-instruction-for-Armv8.1-M-.patch --]
[-- Type: text/plain, Size: 6265 bytes --]
From 936f5b0ed14703ce5ae5cf7959acf85bdc22ed79 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Tue, 18 May 2021 11:28:17 +0200
Subject: [PATCH] PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M
pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c
(enum operand_parse_code): Add OP_SP and OP_R12.
(parse_operands): Add switch cases for OP_SP and OP_R12.
(T16_32_TAB): Add '_pacbti'.
(do_t_pacbti): New function.
(insns): Add 'pacbti'.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
---
gas/config/tc-arm.c | 22 ++++++++++++++++++++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d | 5 +++++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l | 4 ++++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s | 8 +++++++
gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 +
gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 +
opcodes/arm-dis.c | 2 ++
7 files changed, 43 insertions(+)
create mode 100644 gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
create mode 100644 gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
create mode 100644 gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index d7f8fca803b..ed870f01aee 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7115,6 +7115,8 @@ enum operand_parse_code
/* New operands for Armv8.1-M Mainline. */
OP_LR, /* ARM LR register */
+ OP_SP, /* ARM SP register */
+ OP_R12,
OP_RRe, /* ARM register, only even numbered. */
OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
@@ -7425,6 +7427,8 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
case OP_RRo:
case OP_LR:
case OP_oLR:
+ case OP_SP:
+ case OP_R12:
case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
@@ -8122,6 +8126,16 @@ parse_operands (char *str, const unsigned int *pattern, bool thumb)
inst.error = _("operand must be LR register");
break;
+ case OP_SP:
+ if (inst.operands[i].reg != REG_SP)
+ inst.error = _("operand must be SP register");
+ break;
+
+ case OP_R12:
+ if (inst.operands[i].reg != REG_R12)
+ inst.error = _("operand must be r12");
+ break;
+
case OP_RMQRZ:
case OP_oRMQRZ:
case OP_RR_ZR:
@@ -11491,6 +11505,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_negs, 4240, f1d00000), /* rsbs #0 */ \
X(_orr, 4300, ea400000), \
X(_orrs, 4300, ea500000), \
+ X(_pacbti, 0000, f3af800d), \
X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
X(_push, b400, e92d0000), /* stmdb sp!,... */ \
X(_rev, ba00, fa90f080), \
@@ -22317,6 +22332,12 @@ do_vmmla (void)
neon_three_args (1);
}
+static void
+do_t_pacbti (void)
+{
+ inst.instruction = THUMB_OP32 (inst.instruction);
+}
+
\f
/* Overall per-instruction processing. */
@@ -26306,6 +26327,7 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
ToU("bti", f3af800f, 0, (), noargs),
+ toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
new file mode 100644
index 00000000000..77638ee3f62
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.d
@@ -0,0 +1,5 @@
+#name: Invalid Armv8.1-M pointer authentication and branch target identification extention
+#skip: *-*-pe
+#source: armv8_1-m-pacbti-bad.s
+#as: -march=armv8.1-m.main
+#error_output: armv8_1-m-pacbti-bad.l
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
new file mode 100644
index 00000000000..a812603d88d
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*:6: Error: operand must be r12 -- `pacbti r11,lr,sp'
+.*:7: Error: operand must be LR register -- `pacbti r12,r10,sp'
+.*:8: Error: operand must be SP register -- `pacbti r12,lr,r10'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
new file mode 100644
index 00000000000..64e71e70c11
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
@@ -0,0 +1,8 @@
+ .syntax unified
+ .text
+ .thumb
+.Lstart:
+ bti
+ pacbti r11, lr, sp
+ pacbti r12, r10, sp
+ pacbti r12, lr, r10
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 3c693728468..593ac34ed49 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -7,4 +7,5 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 800f bti
+0[0-9a-f]+ <[^>]+> f3af 800d pacbti r12, lr, sp
#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 38929e3dd02..39db4542e39 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -3,3 +3,4 @@
.thumb
.Lstart:
bti
+ pacbti r12, lr, sp
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 1e096997543..34b0ace58bc 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4656,6 +4656,8 @@ static const struct opcode32 thumb32_opcodes[] =
Identification Extension. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800f, 0xffffffff, "bti"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
/* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
instructions. */
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (10 preceding siblings ...)
2021-07-20 15:38 ` PATCH V2 [2/10] arm: add 'pacbti' " Andrea Corallo
@ 2021-07-20 15:38 ` Andrea Corallo
2021-07-21 14:31 ` PATCH [1/10] arm: add 'bti' " Nick Clifton
` (4 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-20 15:38 UTC (permalink / raw)
To: Binutils; +Cc: richard.earnshaw
[-- Attachment #1: Type: text/plain, Size: 555 bytes --]
Hi all,
third patch of the series adding support for PACBTI for Cortex-M.
See:
- Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
- Armv8-M Architecture Reference Manual [2]
This is to add the 'aut' instruction.
The series was tested and does not introduce regressions.
Regards
Andrea
[1] <https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension>
[2] <https://developer.arm.com/documentation/ddi0553/latest>
[-- Attachment #2: 0003-PATCH-3-10-arm-add-aut-instruction-for-Armv8.1-M-pac.patch --]
[-- Type: text/plain, Size: 4180 bytes --]
From 3f9648d785b2a710949995ce3b1b84785badcff4 Mon Sep 17 00:00:00 2001
From: Andrea Corallo <andrea.corallo@arm.com>
Date: Wed, 19 May 2021 09:00:14 +0200
Subject: [PATCH 03/10] PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M
pacbti extension
gas/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* config/tc-arm.c (insns): Add 'aut.'
(T16_32_TAB): Add '_aut'.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests.
* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise.
* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.
opcodes/
2021-06-11 Andrea Corallo <andrea.corallo@arm.com>
* arm-dis.c (thumb32_opcodes): Add 'aut'.
---
gas/config/tc-arm.c | 2 ++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l | 3 +++
gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s | 3 +++
gas/testsuite/gas/arm/armv8_1-m-pacbti.d | 1 +
gas/testsuite/gas/arm/armv8_1-m-pacbti.s | 1 +
opcodes/arm-dis.c | 2 ++
6 files changed, 12 insertions(+)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ed870f01aee..b5d23357fc0 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11450,6 +11450,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
X(_ands, 4000, ea100000), \
X(_asr, 1000, fa40f000), \
X(_asrs, 1000, fa50f000), \
+ X(_aut, 0000, f3af802d), \
X(_b, e000, f000b000), \
X(_bcond, d000, f0008000), \
X(_bf, 0000, f040e001), \
@@ -26326,6 +26327,7 @@ static const struct asm_opcode insns[] =
/* Armv8.1-M Mainline instructions. */
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8_1m_main
+ toU("aut", _aut, 3, (R12, LR, SP), t_pacbti),
ToU("bti", f3af800f, 0, (), noargs),
toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
index a812603d88d..317e62f731b 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.l
@@ -2,3 +2,6 @@
.*:6: Error: operand must be r12 -- `pacbti r11,lr,sp'
.*:7: Error: operand must be LR register -- `pacbti r12,r10,sp'
.*:8: Error: operand must be SP register -- `pacbti r12,lr,r10'
+.*:9: Error: operand must be r12 -- `aut r11,lr,sp'
+.*:10: Error: operand must be LR register -- `aut r12,r10,sp'
+.*:11: Error: operand must be SP register -- `aut r12,lr,r10'
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
index 64e71e70c11..c2ad20455c7 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti-bad.s
@@ -6,3 +6,6 @@
pacbti r11, lr, sp
pacbti r12, r10, sp
pacbti r12, lr, r10
+ aut r11, lr, sp
+ aut r12, r10, sp
+ aut r12, lr, r10
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 593ac34ed49..fe11d7eb036 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -8,4 +8,5 @@
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3af 800f bti
0[0-9a-f]+ <[^>]+> f3af 800d pacbti r12, lr, sp
+0[0-9a-f]+ <[^>]+> f3af 802d aut r12, lr, sp
#...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index 39db4542e39..14b0414a59b 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -4,3 +4,4 @@
.Lstart:
bti
pacbti r12, lr, sp
+ aut r12, lr, sp
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 34b0ace58bc..8eeb303630b 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4654,6 +4654,8 @@ static const struct opcode32 thumb32_opcodes[] =
{
/* Arm v8.1-M Mainline Pointer Authentication and Branch Target
Identification Extension. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf3af800f, 0xffffffff, "bti"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (11 preceding siblings ...)
2021-07-20 15:38 ` PATCH [3/10] arm: add 'aut' " Andrea Corallo
@ 2021-07-21 14:31 ` Nick Clifton
2021-07-21 15:12 ` Andrea Corallo
2021-07-26 12:32 ` Andrea Corallo
2021-08-10 15:31 ` PATCH [2/4] arm: Add Tag_BTI_extension build attribute Nick Clifton
` (3 subsequent siblings)
16 siblings, 2 replies; 21+ messages in thread
From: Nick Clifton @ 2021-07-21 14:31 UTC (permalink / raw)
To: Andrea Corallo, Binutils; +Cc: richard.earnshaw
Hi Andrea,
> The series was tested and does not introduce regressions.
I found one regression with this series applied:
GAS REGRESSION: Valid Armv8.1-M pointer authentication and branch target identification extention
Admittedly this was with a toolchain configure for "arm-wince-pe", but still
please could you add an exception for PE format targets to this test.
The patch series (with that change) is approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension
2021-07-21 14:31 ` PATCH [1/10] arm: add 'bti' " Nick Clifton
@ 2021-07-21 15:12 ` Andrea Corallo
2021-07-26 12:32 ` Andrea Corallo
1 sibling, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-21 15:12 UTC (permalink / raw)
To: Nick Clifton; +Cc: Binutils, richard.earnshaw
Nick Clifton <nickc@redhat.com> writes:
> Hi Andrea,
>
>> The series was tested and does not introduce regressions.
>
> I found one regression with this series applied:
>
> GAS REGRESSION: Valid Armv8.1-M pointer authentication and branch target identification extention
>
> Admittedly this was with a toolchain configure for "arm-wince-pe", but still
> please could you add an exception for PE format targets to this test.
>
> The patch series (with that change) is approved
Hi Nick,
Thanks for reviewing, I've posted the updated patch (2/10).
> - please apply.
I've GCC write access but not the binutils one, is there a way I can ask
for it?
Best Regards
Andrea
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension
2021-07-21 14:31 ` PATCH [1/10] arm: add 'bti' " Nick Clifton
2021-07-21 15:12 ` Andrea Corallo
@ 2021-07-26 12:32 ` Andrea Corallo
1 sibling, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-07-26 12:32 UTC (permalink / raw)
To: Nick Clifton; +Cc: Binutils, richard.earnshaw
Nick Clifton <nickc@redhat.com> writes:
> Hi Andrea,
>
>> The series was tested and does not introduce regressions.
>
> I found one regression with this series applied:
>
> GAS REGRESSION: Valid Armv8.1-M pointer authentication and branch target identification extention
>
> Admittedly this was with a toolchain configure for "arm-wince-pe", but still
> please could you add an exception for PE format targets to this test.
>
> The patch series (with that change) is approved - please apply.
>
> Cheers
> Nick
Hi Nick & all,
The patchset is upstreamed as:
0264bf6fe30 * PATCH [10/10] arm: Alias 'ra_auth_code' to r12 for pacbti.
5c43020d83f * PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension
be05908c0c0 * PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extension
e07352fa4fb * PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extension
5a0c7a819f1 * PATCH [6/10] arm: Add -march=armv8.1-m.main+pacbti flag
2c6ccfcfdde * PATCH [5/10] arm: Extend again arm_feature_set struct to provide more bits
ce537a7db78 * PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extension
e43ca2cbaea * PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extension
f1e1d7f305e * PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension
3751264cdd1 * PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension
Thanks and Best Regards!
Andrea
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: PATCH [2/4] arm: Add Tag_BTI_extension build attribute
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (12 preceding siblings ...)
2021-07-21 14:31 ` PATCH [1/10] arm: add 'bti' " Nick Clifton
@ 2021-08-10 15:31 ` Nick Clifton
2021-08-17 12:59 ` Andrea Corallo
2021-08-10 15:32 ` PATCH [3/4] arm: Add Tag_BTI_use " Nick Clifton
` (2 subsequent siblings)
16 siblings, 1 reply; 21+ messages in thread
From: Nick Clifton @ 2021-08-10 15:31 UTC (permalink / raw)
To: Andrea Corallo, Binutils; +Cc: richard.earnshaw
Hi Andrea,
> second patch of the series adding 'Tag_BTI_extension' build attribute
> support.
>
> Here follows its semantic:
>
> 0 The user did not permit this entity to use BTI instructions
> 1 The user permitted this entity to use BTI instructions in the NOP space
> 2 The user permitted this entity to use BTI instructions in the NOP and in the non-NOP space
Approved - please apply.
(I am not sure if I have already approved patch 1/4 as I cannot
find it in my email queue, but if I have not, then please consider
it approved as well).
Cheers
Nick
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: PATCH [2/4] arm: Add Tag_BTI_extension build attribute
2021-08-10 15:31 ` PATCH [2/4] arm: Add Tag_BTI_extension build attribute Nick Clifton
@ 2021-08-17 12:59 ` Andrea Corallo
0 siblings, 0 replies; 21+ messages in thread
From: Andrea Corallo @ 2021-08-17 12:59 UTC (permalink / raw)
To: Nick Clifton; +Cc: Binutils, richard.earnshaw
Nick Clifton <nickc@redhat.com> writes:
> Hi Andrea,
>
>> second patch of the series adding 'Tag_BTI_extension' build attribute
>> support.
>> Here follows its semantic:
>> 0 The user did not permit this entity to use BTI instructions
>> 1 The user permitted this entity to use BTI instructions in the NOP space
>> 2 The user permitted this entity to use BTI instructions in the NOP and in the non-NOP space
>
> Approved - please apply.
>
> (I am not sure if I have already approved patch 1/4 as I cannot
> find it in my email queue, but if I have not, then please consider
> it approved as well).
>
> Cheers
> Nick
Hi Nick & all,
Thanks for approving, I've applied this small series of patches as
c9fed6655f4 b81ee92f034 4b535030189 99db83d07d1.
Best Regards
Andrea
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: PATCH [3/4] arm: Add Tag_BTI_use build attribute
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (13 preceding siblings ...)
2021-08-10 15:31 ` PATCH [2/4] arm: Add Tag_BTI_extension build attribute Nick Clifton
@ 2021-08-10 15:32 ` Nick Clifton
2021-08-10 15:33 ` PATCH [4/4] arm: Add Tag_PACRET_use " Nick Clifton
2021-08-10 15:33 ` PATCH V2 [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension Nick Clifton
16 siblings, 0 replies; 21+ messages in thread
From: Nick Clifton @ 2021-08-10 15:32 UTC (permalink / raw)
To: Andrea Corallo, Binutils; +Cc: richard.earnshaw
Hi Andrea,
> third patch of the series adding 'Tag_BTI_use' build attribute
> support.
Go ahead - make my day.
Err, I mean, patch approved, please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: PATCH [4/4] arm: Add Tag_PACRET_use build attribute
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (14 preceding siblings ...)
2021-08-10 15:32 ` PATCH [3/4] arm: Add Tag_BTI_use " Nick Clifton
@ 2021-08-10 15:33 ` Nick Clifton
2021-08-10 15:33 ` PATCH V2 [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension Nick Clifton
16 siblings, 0 replies; 21+ messages in thread
From: Nick Clifton @ 2021-08-10 15:33 UTC (permalink / raw)
To: binutils
Hi Andrea,
> Here follows its semantic:
>
> 0 This code is compiled without return address signing and authentication
> 1 This code is compiled with return address signing and authentication
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: PATCH V2 [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension
2021-07-20 15:38 PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension Andrea Corallo
` (15 preceding siblings ...)
2021-08-10 15:33 ` PATCH [4/4] arm: Add Tag_PACRET_use " Nick Clifton
@ 2021-08-10 15:33 ` Nick Clifton
16 siblings, 0 replies; 21+ messages in thread
From: Nick Clifton @ 2021-08-10 15:33 UTC (permalink / raw)
To: Andrea Corallo, Binutils; +Cc: richard.earnshaw
Hi Andrea,
> second patch of the series adding support for PACBTI for Cortex-M.
>
> See:
> - Armv8.1-M Pointer Authentication and Branch Target Identification Extension [1]
> - Armv8-M Architecture Reference Manual [2]
>
> This is to add the 'pacbti' instruction.
>
> This version is incorporating Nick suggestion to skip the
> armv8_1-m-pacbti-bad test on PE format targets.
Approved - please apply.
Cheers
Nick
^ permalink raw reply [flat|nested] 21+ messages in thread