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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Subject: [PATCH 3/4] x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear
Date: Wed, 24 Mar 2021 10:24:01 +0100	[thread overview]
Message-ID: <825e850a-8fc7-95fe-f90b-af8fb7e8ff8c@suse.com> (raw)
In-Reply-To: <f18dff3a-419c-0776-be2d-1fb98609450e@suse.com>

This combination makes no sense and is documented to cause #UD.

gas/
2021-03-XX  Jan Beulich  <jbeulich@suse.com>

	* testsuite/gas/i386/avx512f-nondef.s: Add case for EVEX.z
	without mask register.
	* testsuite/gas/i386/avx512f-nondef.d: Adjust expectations.

opcodes/
2021-03-XX  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
	zeroing-masking without masking.

---
Alternatively we could append "/(bad)" to the destination operand.

--- a/gas/testsuite/gas/i386/avx512f-nondef.d
+++ b/gas/testsuite/gas/i386/avx512f-nondef.d
@@ -1,6 +1,6 @@
 #as: 
 #objdump: -dw
-#name: i386 AVX512F insns with nondefault values in ignored bits
+#name: i386 AVX512F insns with nondefault values in ignored / reserved bits
 
 .*: +file format .*
 
@@ -16,4 +16,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62                   	vpmovdb %zmm6,\(bad\)
 [ 	]*[a-f0-9]+:	f2 7e 58             	bnd jle (0x7d|7d <.text\+0x7d>)
 [ 	]*[a-f0-9]+:	31 72 7f             	xor    %esi,0x7f\(%edx\)
+[ 	]*[a-f0-9]+:	62 f1 7c 88 58       	\(bad\)
+[ 	]*[a-f0-9]+:	c3                   	ret *
 #pass
--- a/gas/testsuite/gas/i386/avx512f-nondef.s
+++ b/gas/testsuite/gas/i386/avx512f-nondef.s
@@ -13,3 +13,5 @@
 .byte 0x62, 0xf2, 0x7e, 0x48, 0x31, 0x72, 0x7f
 # vpmovdb	%zmm6, 2032(%rdx) # with set EVEX.B bit - we should get (bad) operand
 .byte 0x62, 0xf2, 0x7e, 0x58, 0x31, 0x72, 0x7f
+# vaddps xmm0, xmm0, xmm3 # with EVEX.z set
+.byte 0x62, 0xf1, 0x7c, 0x88, 0x58, 0xc3
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -9739,6 +9739,13 @@ print_insn (bfd_vma pc, disassemble_info
       return end_codep - priv.the_buffer;
     }
 
+  /* If EVEX.z is set, there must be an actual mask register in use.  */
+  if (vex.zeroing && vex.mask_register_specifier == 0)
+    {
+      (*info->fprintf_func) (info->stream, "(bad)");
+      return end_codep - priv.the_buffer;
+    }
+
   switch (dp->prefix_requirement)
     {
     case PREFIX_DATA:


  parent reply	other threads:[~2021-03-24  9:24 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-24  9:21 [PATCH 0/4] x86: assorted bug fixes Jan Beulich
2021-03-24  9:22 ` [PATCH 1/4] x86-64: limit breakage from gcc movdir64b et al workaround Jan Beulich
2021-03-24  9:23 ` [PATCH 2/4] x86: fix AMD Zen3 insns Jan Beulich
2021-03-24  9:24 ` Jan Beulich [this message]
2021-03-24  9:24 ` [PATCH 4/4] x86: flag bad S/G insn operand combinations Jan Beulich
2021-03-24 14:02 ` [PATCH 0/4] x86: assorted bug fixes H.J. Lu

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