From: Xi Ruoyao <xry111@xry111.site>
To: changjiachen <changjiachen@stu.xupt.edu.cn>, binutils@sourceware.org
Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn,
liuzhensong@loongson.cn, i.swmail@xen0n.name,
maskray@google.com, cailulu@loongson.cn, luweining@loongson.cn,
wanglei@loongson.cn, hejinyang@loongson.cn, Lazy_Linux@126.com,
mengqinggang@loongson.cn
Subject: Re: [PATCH v2 3/5] LoongArch: opcodes: Add support for tls le relax.
Date: Sat, 02 Dec 2023 15:14:28 +0800 [thread overview]
Message-ID: <8295edb277bbeae2e5a7e12e1ffb09e33898ba58.camel@xry111.site> (raw)
In-Reply-To: <20231202065334.25904-4-changjiachen@stu.xupt.edu.cn>
On Sat, 2023-12-02 at 14:53 +0800, changjiachen wrote:
> Add new opcode for tls le relax.
>
> opcode/ChangeLog:
>
> * loongarch-opc.c: Add new loongarch opcode.
> ---
> opcodes/loongarch-opc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
> index 82b88bdad2a..e9ced5383e5 100644
> --- a/opcodes/loongarch-opc.c
> +++ b/opcodes/loongarch-opc.c
> @@ -399,6 +399,7 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
> { 0x000c0000, 0xfffc0000, "bytepick.d", "r0:5,r5:5,r10:5,u15:3", 0, 0, 0, 0 },
> { 0x00100000, 0xffff8000, "add.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
> { 0x00108000, 0xffff8000, "add.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
> + { 0x00108000, 0xffff8000, "add.d", "r0:5,r5:5,r10:5,s10:5", 0, 0, 0, 0 },
This is just wrong, as I've pointed out in v1.
You can always write
.reloc 0, R_LARCH_LE_ADD_R, a
add.d $t0, $t0, $tp
If you think it looks nasty you can add a new pseudo instruction for
this. Anyway there is not an "add.d" instruction accepting an
immediate. Try not to puzzle people.
(The trailing ",0" in the sc instructions is already much annoying to
me. Do not make things even worse.)
And please make the technical discussion public, instead of sending a
private reply (unless you have a good reason).
> { 0x00110000, 0xffff8000, "sub.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
> { 0x00118000, 0xffff8000, "sub.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
> { 0x00120000, 0xffff8000, "slt", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
next prev parent reply other threads:[~2023-12-02 7:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-02 6:53 [PATCH v2 0/5] LoongArch tls le model linker relaxation support changjiachen
2023-12-02 6:53 ` [PATCH v2 1/5] LoongArch: bfd: Add support for tls le relax changjiachen
2023-12-02 7:20 ` Xi Ruoyao
2023-12-02 9:36 ` 常佳琛
2023-12-02 6:53 ` [PATCH v2 2/5] LoongArch: include: " changjiachen
2023-12-02 6:53 ` [PATCH v2 3/5] LoongArch: opcodes: " changjiachen
2023-12-02 7:14 ` Xi Ruoyao [this message]
2023-12-02 9:40 ` 常佳琛
2023-12-05 1:36 ` mengqinggang
2023-12-05 3:59 ` Xi Ruoyao
2023-12-05 9:13 ` mengqinggang
2023-12-02 6:53 ` [PATCH v2 4/5] LoongArch: gas: " changjiachen
2023-12-02 6:53 ` [PATCH v2 5/5] LoongArch: ld: " changjiachen
2023-12-02 7:17 ` Xi Ruoyao
2023-12-02 9:30 ` 常佳琛
2023-12-04 2:25 ` [PATCH v2 0/5] LoongArch tls le model linker relaxation support Jinyang He
2023-12-04 3:39 ` 常佳琛
2023-12-04 8:57 ` Jinyang He
2023-12-04 9:25 ` 常佳琛
2023-12-04 9:37 ` Xi Ruoyao
2023-12-04 9:42 ` Xi Ruoyao
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