diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 63397bcb162747c9fe77ebcf6f0066c286c6c620..1b67843a4dd1744ef1ab2a7f9af3013922b7dbec 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -24,3 +24,6 @@
 .*: Error: selected processor does not support system register name 'pfar_el1'
 .*: Error: selected processor does not support system register name 'pfar_el2'
 .*: Error: selected processor does not support system register name 'pfar_el12'
+.*: Error: selected processor does not support system register name 's1e1a'
+.*: Error: selected processor does not support system register name 's1e2a'
+.*: Error: selected processor does not support system register name 's1e3a'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index 3b66e2bc57c1be243737679e2b85758bfe2af871..18376bb5ac19d821c8fcef2dcb272cdc2b9c5e52 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -31,3 +31,6 @@ Disassembly of section \.text:
 .*:	d51860a0 	msr	pfar_el1, x0
 .*:	d51c60a0 	msr	pfar_el2, x0
 .*:	d51d60a0 	msr	pfar_el12, x0
+.*:	d5087941 	at	s1e1a, x1
+.*:	d50c7943 	at	s1e2a, x3
+.*:	d50e7945 	at	s1e3a, x5
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 9ad0a532acc1bd8714f89b193d1b41f57ffb80d2..4e494a965f6a9196395b2da1f8fb7da3e42faa7c 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -27,3 +27,8 @@
 	msr PFAR_EL1, x0
 	msr PFAR_EL2, x0
 	msr PFAR_EL12, x0
+
+	/* AT.  */
+	at s1e1a, x1
+	at s1e2a, x3
+	at s1e3a, x5
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 03ef907cac1c574516f1e1cc4d0537b33c803986..792d6a4f4a7603487899f175c2b49763cbb47697 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -183,6 +183,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_FGT2,
   /* Physical Fault Address.  */
   AARCH64_FEATURE_PFAR,
+  /* Address Translate Stage 1.  */
+  AARCH64_FEATURE_ATS1A,
   AARCH64_NUM_FEATURES
 };
 
@@ -245,7 +247,8 @@ enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, RASv2)	\
 					 | AARCH64_FEATBIT (X, SCTLR2)	\
 					 | AARCH64_FEATBIT (X, FGT2)	\
-					 | AARCH64_FEATBIT (X, PFAR))
+					 | AARCH64_FEATBIT (X, PFAR)	\
+					 | AARCH64_FEATBIT (X, ATS1A))
 
 #define AARCH64_ARCH_V9A_FEATURES(X)	(AARCH64_FEATBIT (X, V9A)	\
 					 | AARCH64_FEATBIT (X, F16)	\
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 80816d633661eb5a39e0da28c1cd5d4c87df308f..126a4aa0a4cd559a4697eab678cca160660d615a 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4810,6 +4810,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
     { "s1e3w",      CPENS (6, C7, C8, 1), F_HASXT },
     { "s1e1rp",     CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
     { "s1e1wp",     CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
+    { "s1e1a",      CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT },
+    { "s1e2a",      CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT },
+    { "s1e3a",      CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT },
     { 0,       CPENS(0,0,0,0), 0 }
 };
 
@@ -5041,6 +5044,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
       && AARCH64_CPU_HAS_FEATURE (features, THE))
     return true;
 
+  if ((reg_value == CPENS (0, C7, C9, 2)
+       || reg_value == CPENS (4, C7, C9, 2)
+       || reg_value == CPENS (6, C7, C9, 2))
+      && AARCH64_CPU_HAS_FEATURE (features, ATS1A))
+    return true;
+
   return false;
 }