From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id C117A3889E1E for ; Sun, 20 Nov 2022 01:09:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C117A3889E1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 2111D300089; Sun, 20 Nov 2022 01:09:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1668906562; bh=c9w4MxVEN+tim8nfr5DV+v5NsT0j00VJqM27kLNUwEU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=azOePFIhcnX6J0GWSZ5z/pD5tF38HOCx1QPOBw5iMQDawCQb7m80tQCnNeekkPMZx J3Xmty1GqoApfDTRhLcpLC1ybC31WKq0lj8QMKwQcNXlmpeyObGO2IAcnWC+7Pk/xG wpPJeQ3TF9RDXkKpzNHzScBwxS/jW4SoP4OY0jsA= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 3/3] RISC-V: Cache instruction support Date: Sun, 20 Nov 2022 01:08:42 +0000 Message-Id: <844db363911065a3b5f0c5e4601f89ee1d7360c5.1668906514.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Tsukasa OI Calling riscv_subset_supports repeatedly harms the performance in a measurable way (about 3-13% in total on the most cases). As a simple solution, this commit now caches instruction class support (whether specific instruction class is supported) as a signed char array. It is expected to have 5-7% performance improvements when disassembling linked RISC-V ELF programs using objdump but this is particularly effective with programs with many CSR instructions (up to ~42% on the author's PC). include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add NUM_INSN_CLASSES. opcodes/ChangeLog: * riscv-dis.c (riscv_insn_support_cache) New. (init_riscv_dis_state_for_arch): Clear the instruction support cache. (riscv_disassemble_insn): Cache the instruction support. --- include/opcode/riscv.h | 2 ++ opcodes/riscv-dis.c | 15 ++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index c3cbde600cb0..6a029a1034e1 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -422,6 +422,8 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, + + NUM_INSN_CLASSES, }; /* This structure holds information for a particular instruction. */ diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 197f6a31d439..32e7b1174436 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -107,6 +107,9 @@ static bool no_aliases = false; /* If set, disassemble with numeric register names. */ static bool is_numeric = false; + +/* Instruction support cache. */ +static signed char riscv_insn_support_cache[NUM_INSN_CLASSES]; /* Set current disassembler context (dis_arch_context_current). @@ -200,6 +203,9 @@ static void init_riscv_dis_state_for_arch (void) { is_arch_changed = true; + /* Clear instruction support cache. */ + for (size_t i = 0; i < NUM_INSN_CLASSES; i++) + riscv_insn_support_cache[i] = 0; } /* Initialization (for arch and options). */ @@ -955,7 +961,14 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) continue; /* Is this instruction supported by the current architecture? */ - if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) + if (riscv_insn_support_cache[op->insn_class] == 0) + { + riscv_insn_support_cache[op->insn_class] + = riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class) + ? +1 + : -1; + } + if (riscv_insn_support_cache[op->insn_class] < 0) continue; matched_op = op; -- 2.38.1