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From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>, Lili Cui <lili.cui@intel.com>
Subject: [PATCH 2/2] x86-64: refuse "high" 8-bit regs with .insn and VEX/XOP/EVEX encodings
Date: Fri, 15 Dec 2023 14:32:26 +0100	[thread overview]
Message-ID: <870d2722-85a5-4ab8-9680-4b1c4e8f98af@suse.com> (raw)
In-Reply-To: <663a2bcd-188c-42d9-9147-9f5d1e627429@suse.com>

Much like REX, those encodings - if permitting 8-bit regs at all, i.e.
only starting with APX - permit use of "new" 8-bit registers only. %ah,
%ch, %dh, and %bh cannot be encoded and hence should be rejected.

Permit their use outside of 64-bit code though, as "new" registers
simply don't exist there.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -11484,6 +11484,16 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
 
       for (j = i.imm_operands; j < i.operands; ++j)
 	{
+	  /* Look for 8-bit operands that use old registers.  */
+	  if (i.vec_encoding != vex_encoding_default
+	      && flag_code == CODE_64BIT
+	      && i.types[j].bitfield.class == Reg
+	      && i.types[j].bitfield.byte
+	      && !(i.op[j].regs->reg_flags & RegRex64)
+	      && i.op[j].regs->reg_num > 3)
+	    as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"),
+		    register_prefix, i.op[j].regs->reg_name);
+
 	  i.types[j].bitfield.instance = InstanceNone;
 
 	  if (operand_type_check (i.types[j], disp))


      parent reply	other threads:[~2023-12-15 13:32 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-15 13:30 [PATCH 0/2] x86: .insn and diagnostic fixes Jan Beulich
2023-12-15 13:32 ` [PATCH 1/2] x86: properly respect rex/{rex} Jan Beulich
2023-12-15 13:32 ` Jan Beulich [this message]

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