From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Subject: [AArch64][SVE 17/32] Add a prefix parameter to print_register_list
Date: Tue, 23 Aug 2016 09:16:00 -0000 [thread overview]
Message-ID: <8737lv3kwk.fsf@e105548-lin.cambridge.arm.com> (raw)
In-Reply-To: <874m6b6ekq.fsf@e105548-lin.cambridge.arm.com> (Richard Sandiford's message of "Tue, 23 Aug 2016 10:04:53 +0100")
This patch generalises the interface to print_register_list so
that it can print register lists involving SVE z registers as
well as AdvSIMD v ones.
OK to install?
Thanks,
Richard
opcodes/
* aarch64-opc.c (print_register_list): Add a prefix parameter.
(aarch64_print_operand): Update accordingly.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 84da821..6eac70a 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2261,9 +2261,11 @@ expand_fp_imm (int size, uint32_t imm8)
}
/* Produce the string representation of the register list operand *OPND
- in the buffer pointed by BUF of size SIZE. */
+ in the buffer pointed by BUF of size SIZE. PREFIX is the part of
+ the register name that comes before the register number, such as "v". */
static void
-print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd)
+print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
+ const char *prefix)
{
const int num_regs = opnd->reglist.num_regs;
const int first_reg = opnd->reglist.first_regno;
@@ -2284,8 +2286,8 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd)
more than two registers in the list, and the register numbers
are monotonically increasing in increments of one. */
if (num_regs > 2 && last_reg > first_reg)
- snprintf (buf, size, "{v%d.%s-v%d.%s}%s", first_reg, qlf_name,
- last_reg, qlf_name, tb);
+ snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
+ prefix, last_reg, qlf_name, tb);
else
{
const int reg0 = first_reg;
@@ -2296,20 +2298,21 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd)
switch (num_regs)
{
case 1:
- snprintf (buf, size, "{v%d.%s}%s", reg0, qlf_name, tb);
+ snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
break;
case 2:
- snprintf (buf, size, "{v%d.%s, v%d.%s}%s", reg0, qlf_name,
- reg1, qlf_name, tb);
+ snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
+ prefix, reg1, qlf_name, tb);
break;
case 3:
- snprintf (buf, size, "{v%d.%s, v%d.%s, v%d.%s}%s", reg0, qlf_name,
- reg1, qlf_name, reg2, qlf_name, tb);
+ snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
+ prefix, reg0, qlf_name, prefix, reg1, qlf_name,
+ prefix, reg2, qlf_name, tb);
break;
case 4:
- snprintf (buf, size, "{v%d.%s, v%d.%s, v%d.%s, v%d.%s}%s",
- reg0, qlf_name, reg1, qlf_name, reg2, qlf_name,
- reg3, qlf_name, tb);
+ snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
+ prefix, reg0, qlf_name, prefix, reg1, qlf_name,
+ prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
break;
}
}
@@ -2513,7 +2516,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_LVt:
case AARCH64_OPND_LVt_AL:
case AARCH64_OPND_LEt:
- print_register_list (buf, size, opnd);
+ print_register_list (buf, size, opnd, "v");
break;
case AARCH64_OPND_Cn:
next prev parent reply other threads:[~2016-08-23 9:16 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-23 9:05 [AArch64][SVE 00/32] Add support for the ARMv8-A Scalable Vector Extension Richard Sandiford
2016-08-23 9:06 ` [AArch64][SVE 02/32] Avoid hard-coded limit in indented_print Richard Sandiford
2016-08-23 14:35 ` Richard Earnshaw (lists)
2016-08-23 9:06 ` [AArch64][SVE 01/32] Remove parse_neon_operand_type Richard Sandiford
2016-08-23 14:28 ` Richard Earnshaw (lists)
2016-08-23 9:07 ` [AArch64][SVE 04/32] Rename neon_type_el to vector_type_el Richard Sandiford
2016-08-23 14:37 ` Richard Earnshaw (lists)
2016-08-23 9:07 ` [AArch64][SVE 03/32] Rename neon_el_type to vector_el_type Richard Sandiford
2016-08-23 14:36 ` Richard Earnshaw (lists)
2016-08-23 9:08 ` [AArch64][SVE 06/32] Generalise parse_neon_reg_list Richard Sandiford
2016-08-23 14:39 ` Richard Earnshaw (lists)
2016-08-23 9:08 ` [AArch64][SVE 05/32] Rename parse_neon_type_for_operand Richard Sandiford
2016-08-23 14:37 ` Richard Earnshaw (lists)
2016-08-23 9:09 ` [AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V Richard Sandiford
2016-08-25 10:36 ` Richard Earnshaw (lists)
2016-08-23 9:10 ` [AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable Richard Sandiford
2016-08-25 13:17 ` Richard Earnshaw (lists)
2016-08-23 9:11 ` [AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float Richard Sandiford
2016-08-25 13:20 ` Richard Earnshaw (lists)
2016-08-23 9:11 ` [AArch64][SVE 09/32] Improve error messages for invalid floats Richard Sandiford
2016-08-25 13:19 ` Richard Earnshaw (lists)
2016-08-23 9:12 ` [AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface Richard Sandiford
2016-08-25 13:27 ` Richard Earnshaw (lists)
2016-09-16 11:51 ` Richard Sandiford
2016-09-20 10:47 ` Richard Earnshaw (lists)
2016-08-23 9:13 ` [AArch64][SVE 12/32] Make more use of bfd_boolean Richard Sandiford
2016-08-25 13:39 ` Richard Earnshaw (lists)
2016-09-16 11:56 ` Richard Sandiford
2016-09-20 12:39 ` Richard Earnshaw (lists)
2016-08-23 9:14 ` [AArch64][SVE 13/32] Add an F_STRICT flag Richard Sandiford
2016-08-25 13:45 ` Richard Earnshaw (lists)
2016-08-23 9:15 ` [AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers Richard Sandiford
2016-08-25 13:50 ` Richard Earnshaw (lists)
2016-08-23 9:15 ` [AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size Richard Sandiford
2016-08-25 13:48 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 16/32] Use specific insert/extract methods for fpimm Richard Sandiford
2016-08-25 13:52 ` Richard Earnshaw (lists)
2016-08-23 9:16 ` Richard Sandiford [this message]
2016-08-25 13:53 ` [AArch64][SVE 17/32] Add a prefix parameter to print_register_list Richard Earnshaw (lists)
2016-08-23 9:16 ` [AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg Richard Sandiford
2016-08-25 13:55 ` Richard Earnshaw (lists)
2016-08-23 9:17 ` [AArch64][SVE 19/32] Refactor address-printing code Richard Sandiford
2016-08-25 13:57 ` Richard Earnshaw (lists)
2016-08-23 9:18 ` [AArch64][SVE 21/32] Add Zn and Pn registers Richard Sandiford
2016-08-25 14:07 ` Richard Earnshaw (lists)
2016-08-23 9:18 ` [AArch64][SVE 20/32] Add support for tied operands Richard Sandiford
2016-08-25 13:59 ` Richard Earnshaw (lists)
2016-08-23 9:19 ` [AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication Richard Sandiford
2016-08-25 14:08 ` Richard Earnshaw (lists)
2016-08-23 9:20 ` [AArch64][SVE 23/32] Add SVE pattern and prfop operands Richard Sandiford
2016-08-25 14:12 ` Richard Earnshaw (lists)
2016-08-23 9:21 ` [AArch64][SVE 25/32] Add support for SVE addressing modes Richard Sandiford
2016-08-25 14:38 ` Richard Earnshaw (lists)
2016-09-16 12:06 ` Richard Sandiford
2016-09-20 13:40 ` Richard Earnshaw (lists)
2016-08-23 9:21 ` [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Richard Sandiford
2016-08-25 14:28 ` Richard Earnshaw (lists)
2016-08-23 9:23 ` [AArch64][SVE 26/32] Add SVE MUL VL addressing modes Richard Sandiford
2016-08-25 14:44 ` Richard Earnshaw (lists)
2016-09-16 12:10 ` Richard Sandiford
2016-09-20 13:51 ` Richard Earnshaw (lists)
2016-08-23 9:24 ` [AArch64][SVE 27/32] Add SVE integer immediate operands Richard Sandiford
2016-08-25 14:51 ` Richard Earnshaw (lists)
2016-08-23 9:25 ` [AArch64][SVE 28/32] Add SVE FP " Richard Sandiford
2016-08-25 14:59 ` Richard Earnshaw (lists)
2016-08-23 9:25 ` [AArch64][SVE 29/32] Add new SVE core & FP register operands Richard Sandiford
2016-08-25 15:01 ` Richard Earnshaw (lists)
2016-08-23 9:26 ` [AArch64][SVE 30/32] Add SVE instruction classes Richard Sandiford
2016-08-25 15:07 ` Richard Earnshaw (lists)
2016-08-23 9:29 ` [AArch64][SVE 31/32] Add SVE instructions Richard Sandiford
2016-08-25 15:18 ` Richard Earnshaw (lists)
2016-08-23 9:31 ` [AArch64][SVE 32/32] Add SVE tests Richard Sandiford
2016-08-25 15:23 ` Richard Earnshaw (lists)
2016-08-30 21:23 ` Richard Sandiford
2016-08-31 9:47 ` Richard Earnshaw (lists)
2016-08-30 13:04 ` [AArch64][SVE 00/32] Add support for the ARMv8-A Scalable Vector Extension Nick Clifton
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