From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id 698F03858C20 for ; Sat, 1 Oct 2022 20:27:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 698F03858C20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1664656064; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=wdj2Nhc8osEcJojKt1x0uidENrE6pDWp6UrdUzING2E=; b=epk5jIDAUihFWKBA5P5XQmuG/Qvt1ZUWkJVsMp53AbSth0w/XWDu6zIlf9tWZ/L792BqSl /60GkTVzB+9AcnTVPpscgqwQZTDtHYh0daJSavlweMJB3tlrgXy5a0xEgSFDYsHBP0CD9T iS0aqLzBkSihUREfBLLLa8KjRUTG01E= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-283-6p6-wMWwONaSyLOVOYpxKg-1; Sat, 01 Oct 2022 16:27:43 -0400 X-MC-Unique: 6p6-wMWwONaSyLOVOYpxKg-1 Received: by mail-wm1-f69.google.com with SMTP id n32-20020a05600c3ba000b003b5054c71faso6447545wms.9 for ; Sat, 01 Oct 2022 13:27:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=mime-version:message-id:date:references:in-reply-to:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date; bh=wdj2Nhc8osEcJojKt1x0uidENrE6pDWp6UrdUzING2E=; b=N8Fhv/7cIbyfe941ohc0vJpwOGZhG9znEUlwWIgPctQLiftiRGmB2R4Cre0RIwMN3t uZLqNARGnvLpyqJO+k4KUmJTQMh5pt4cKu0MX7bGfvFuB8MoR0UvMVJSu+zO6jxFM+BF ad3PNajssvFhTGkyajZe5QuRa0lOPl5JztexaoK9iX3ea5CMy1BEaMRDHIqWBp2XkC6P OXunpJdNOB1oOD1XZacFkrMzVAj9duOgFI3uHXLTrpf9XP1b9/pVPWbtpOjLUVdfDnev +/i4WVCb3wwhdVzsdPZ9ffW7PJM1QPWxY8dSU/0WP4XMuPo+oNa7fmuP//LCjGifp/fG +Xbg== X-Gm-Message-State: ACrzQf2eZTjaQvVPctioC7/FSzPEqg+QDp9i5MWd2iGlueEFTWmvoMlh fJd8PEIi4NrFMGwQdceZ+8Fhf6rg1AnpLzkeatCaygJJWakn+QinFAPSnZZZNA82v2UPtcO8cBe IbQaUWmkjp1hKnTJL8ffKH4gKpEeA8dxy3sv1QskgbxGSOrWgHzShRt3t9klLy0AjEIE7aQ== X-Received: by 2002:adf:c641:0:b0:22a:2da9:e248 with SMTP id u1-20020adfc641000000b0022a2da9e248mr9284618wrg.132.1664656061993; Sat, 01 Oct 2022 13:27:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4O0vjgnU6EaD51ZW9KNpDum/QRvSWpjbjZwkKAGiANfZ5ip5FHW4o59ImkslcW5hTT9ErTgQ== X-Received: by 2002:adf:c641:0:b0:22a:2da9:e248 with SMTP id u1-20020adfc641000000b0022a2da9e248mr9284609wrg.132.1664656061685; Sat, 01 Oct 2022 13:27:41 -0700 (PDT) Received: from localhost (52.72.115.87.dyn.plus.net. [87.115.72.52]) by smtp.gmail.com with ESMTPSA id p3-20020a5d4e03000000b002238ea5750csm5910379wrt.72.2022.10.01.13.27.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Oct 2022 13:27:41 -0700 (PDT) From: Andrew Burgess To: Tsukasa OI via Binutils , Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers In-Reply-To: References: Date: Sat, 01 Oct 2022 21:27:40 +0100 Message-ID: <874jwni91f.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Tsukasa OI via Binutils writes: > Hello, > > Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF > register numbers. RISC-V ABIs Specification (riscv-elf-psabi-doc) is not > ratified yet but at least frozen. So, I consider it's stable to upstream > it. According to the documentation, it has register numbers 96 (v0) - > 127 (v31). > > [Changes: v1 -> v2] > Remove invented word "VPRs" (at least it has no consistent uses in the > RISC-V ecosystem) and replaced with "Vector registers" > > [Changes: v2 -> v3] > Changed reference (v1.0-rc3 -> v1.0-rc4). > > Tracker on GitHub: > > > RISC-V ABIs Specification Version 1.0-rc4: Frozen > > > > I also added DWARF register number tests not just for CSRs (existing) and > vector registers (I just added), but also for GPRs (0-31) and FPRs > (32-63). Hi Tsukasa, I can't approve binutils patches, but as this mentioned RISC-V and DWARF, both of which I'm interested in, I took a look :) Both these patches look good to me. The register numbers align with the spec, and the test makes sense. Thanks for the patch. Andrew > > > Thanks, > Tsukasa > > > > > Tsukasa OI (2): > RISC-V: Assign DWARF numbers to vector registers > RISC-V: Add testcase for DWARF register numbers > > binutils/dwarf.c | 28 ++-- > gas/config/tc-riscv.c | 3 + > gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++ > gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++ > 4 files changed, 385 insertions(+), 10 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d > create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s > > > base-commit: 90eca7111355e4c6683c1ab10fd07107ea10f6d1 > -- > 2.34.1