* Re: [PATCH MIPS][LS3A]Generic Support
[not found] <8762xu164h.fsf@firetop.home>
@ 2010-09-27 12:55 ` Nick Clifton
2010-09-28 1:28 ` Mingming Sun
2010-11-10 11:12 ` Mingming Sun
0 siblings, 2 replies; 14+ messages in thread
From: Nick Clifton @ 2010-09-27 12:55 UTC (permalink / raw)
To: mingm.sun; +Cc: Richard Sandiford, binutils
[-- Attachment #1: Type: text/plain, Size: 372 bytes --]
Hi Mingming,
Thanks very much for submitting this patch. The work itself is fine,
but unfortunately we cannot accept it without a binutils FSF copyright
assignment in place. (I know that you have a GCC assignment, but we
need a binutils one). Please could you fill out the attached form and
send it off so that the assignment can be sorted out.
Cheers
Nick
[-- Attachment #2: request-assign.future --]
[-- Type: text/plain, Size: 971 bytes --]
Please email the following information to assign@gnu.org, and we
will send you the assignment form for your past and future changes.
Please use your full legal name (in ASCII characters) as the subject
line of the message.
----------------------------------------------------------------------
REQUEST: SEND FORM FOR PAST AND FUTURE CHANGES
[What is the name of the program or package you're contributing to?]
[Did you copy any files or text written by someone else in these changes?
Even if that material is free software, we need to know about it.]
[Do you have an employer who might have a basis to claim to own
your changes? Do you attend a school which might make such a claim?]
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so far?]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-09-27 12:55 ` [PATCH MIPS][LS3A]Generic Support Nick Clifton
@ 2010-09-28 1:28 ` Mingming Sun
2010-11-10 11:12 ` Mingming Sun
1 sibling, 0 replies; 14+ messages in thread
From: Mingming Sun @ 2010-09-28 1:28 UTC (permalink / raw)
To: Nick Clifton; +Cc: Richard Sandiford, binutils
On Mon, Sep 27, 2010 at 8:55 PM, Nick Clifton <nickc@redhat.com> wrote:
> Hi Mingming,
>
> Thanks very much for submitting this patch. The work itself is fine, but
> unfortunately we cannot accept it without a binutils FSF copyright
> assignment in place. (I know that you have a GCC assignment, but we need a
> binutils one). Please could you fill out the attached form and send it off
> so that the assignment can be sorted out.
>
> Cheers
> Nick
>
Thanks very much for your review.
I've send a request for binutils to assignment@gnu.org, and received
the reply 4 days ago.
I'll send off the assignment as soon as I receive it.
Thanks,
Mingming Sun
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-09-27 12:55 ` [PATCH MIPS][LS3A]Generic Support Nick Clifton
2010-09-28 1:28 ` Mingming Sun
@ 2010-11-10 11:12 ` Mingming Sun
2010-11-10 23:27 ` Maciej W. Rozycki
2010-11-11 10:24 ` Nick Clifton
1 sibling, 2 replies; 14+ messages in thread
From: Mingming Sun @ 2010-11-10 11:12 UTC (permalink / raw)
To: Nick Clifton, binutils
[-- Attachment #1: Type: text/plain, Size: 1601 bytes --]
2010/9/27 Nick Clifton <nickc@redhat.com>:
> Hi Mingming,
>
> Thanks very much for submitting this patch. The work itself is fine, but
> unfortunately we cannot accept it without a binutils FSF copyright
> assignment in place. (I know that you have a GCC assignment, but we need a
> binutils one). Please could you fill out the attached form and send it off
> so that the assignment can be sorted out.
>
> Cheers
> Nick
>
Hi Nick,
I've got the binutils FSF copyright assignment recently.
Is this patch ok for binutils?
Thanks,
Mingming Sun
2010-09-21 Mingming Sun <mingm.sun@gmail.com>
bfd/
* archures.c (bfd_mach_mips_loongson_3a): Defined.
* bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
* cpu-mips.c (I_loongson_3a): New add.
(arch_info_struct): Add loongson_3a.
* elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
(mips_set_isa_flags): Add loongson_3a.
(mips_mach_extensions): Add loongson_3a in MIPS64 extensions.
binutils/
* readelf.c (get_machine_flags): Add loongson-3a.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
* doc/c-mips.texi (MIPS cpu): Add loongson3a.
include/
* elf/mips.h (E_MIPS_MACH_LS3A): Defined.
* opcode/mips.h (INSN_LOONGSON_3A): Defined.
(CPU_LOONGSON_3A): Defined.
(OPCODE_IS_MEMBER): Add LOONGSON_3A.
opcodes/
* mips-dis.c (mips_arch_choices): Add loongson3a.
* mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
(mips_builtin_opcodes): Modify some instructions' membership from
IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
[-- Attachment #2: binutils-3a.patch --]
[-- Type: application/octet-stream, Size: 23707 bytes --]
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.150
diff -u -p -r1.150 archures.c
--- bfd/archures.c 23 Jul 2010 14:52:46 -0000 1.150
+++ bfd/archures.c 21 Sep 2010 08:52:40 -0000
@@ -173,6 +173,7 @@ DESCRIPTION
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_loongson_2f 3002
+.#define bfd_mach_mips_loongson_3a 3003
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.517
diff -u -p -r1.517 bfd-in2.h
--- bfd/bfd-in2.h 18 Aug 2010 12:24:04 -0000 1.517
+++ bfd/bfd-in2.h 21 Sep 2010 08:52:44 -0000
@@ -1839,6 +1839,7 @@ enum bfd_architecture
#define bfd_mach_mips5 5
#define bfd_mach_mips_loongson_2e 3001
#define bfd_mach_mips_loongson_2f 3002
+#define bfd_mach_mips_loongson_3a 3003
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.34
diff -u -p -r1.34 cpu-mips.c
--- bfd/cpu-mips.c 6 May 2010 15:02:24 -0000 1.34
+++ bfd/cpu-mips.c 21 Sep 2010 08:52:44 -0000
@@ -91,6 +91,7 @@ enum
I_sb1,
I_loongson_2e,
I_loongson_2f,
+ I_loongson_3a,
I_mipsocteon,
I_xlr
};
@@ -130,6 +131,7 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
+ N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0)
};
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.274
diff -u -p -r1.274 elfxx-mips.c
--- bfd/elfxx-mips.c 19 Sep 2010 10:52:17 -0000 1.274
+++ bfd/elfxx-mips.c 21 Sep 2010 08:52:49 -0000
@@ -5963,6 +5963,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_LS2F:
return bfd_mach_mips_loongson_2f;
+ case E_MIPS_MACH_LS3A:
+ return bfd_mach_mips_loongson_3a;
+
case E_MIPS_MACH_OCTEON:
return bfd_mach_mips_octeon;
@@ -10561,6 +10564,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
break;
+ case bfd_mach_mips_loongson_3a:
+ val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
+ break;
+
case bfd_mach_mips_sb1:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
@@ -12263,6 +12270,7 @@ static const struct mips_mach_extension
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
{ bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
+ { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64 },
/* MIPS V extensions. */
{ bfd_mach_mipsisa64, bfd_mach_mips5 },
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.515
diff -u -p -r1.515 readelf.c
--- binutils/readelf.c 7 Sep 2010 15:02:17 -0000 1.515
+++ binutils/readelf.c 21 Sep 2010 08:53:02 -0000
@@ -2426,6 +2426,7 @@ get_machine_flags (unsigned e_flags, uns
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
+ case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break;
case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.425
diff -u -p -r1.425 tc-mips.c
--- gas/config/tc-mips.c 27 Jul 2010 21:04:59 -0000 1.425
+++ gas/config/tc-mips.c 21 Sep 2010 08:53:08 -0000
@@ -15383,6 +15383,7 @@ static const struct mips_cpu_info mips_c
{ "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
{ "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
{ "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
+ { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
/* Broadcom SB-1 CPU core */
{ "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.55
diff -u -p -r1.55 c-mips.texi
--- gas/doc/c-mips.texi 25 Feb 2010 11:15:47 -0000 1.55
+++ gas/doc/c-mips.texi 21 Sep 2010 08:53:09 -0000
@@ -298,6 +298,7 @@ sb1,
sb1a,
loongson2e,
loongson2f,
+loongson3a,
octeon,
xlr
@end quotation
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.43
diff -u -p -r1.43 mips.h
--- include/elf/mips.h 15 Apr 2010 10:26:08 -0000 1.43
+++ include/elf/mips.h 21 Sep 2010 08:53:11 -0000
@@ -222,6 +222,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_9000 0x00990000
#define E_MIPS_MACH_LS2E 0x00A00000
#define E_MIPS_MACH_LS2F 0x00A10000
+#define E_MIPS_MACH_LS3A 0x00A20000
\f
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.67
diff -u -p -r1.67 mips.h
--- include/opcode/mips.h 6 Jul 2010 00:02:44 -0000 1.67
+++ include/opcode/mips.h 21 Sep 2010 08:53:11 -0000
@@ -594,6 +594,8 @@ static const unsigned int mips_isa_table
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* Loongson 3A. */
+#define INSN_LOONGSON_3A 0x80000400
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
@@ -647,6 +649,7 @@ static const unsigned int mips_isa_table
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
+#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
#define CPU_XLR 887682 /* decimal 'XLR' */
@@ -680,6 +683,8 @@ static const unsigned int mips_isa_table
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|| (cpu == CPU_LOONGSON_2F \
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
+ || (cpu == CPU_LOONGSON_3A \
+ && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.81
diff -u -p -r1.81 mips-dis.c
--- opcodes/mips-dis.c 6 Jul 2010 00:06:04 -0000 1.81
+++ opcodes/mips-dis.c 21 Sep 2010 08:53:12 -0000
@@ -512,6 +512,10 @@ const struct mips_arch_choice mips_arch_
ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
+ { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
+ ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
+ NULL, 0, mips_hwr_names_numeric },
+
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
mips_hwr_names_numeric },
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.78
diff -u -p -r1.78 mips-opc.c
--- opcodes/mips-opc.c 14 Sep 2010 23:49:04 -0000 1.78
+++ opcodes/mips-opc.c 21 Sep 2010 08:53:13 -0000
@@ -107,6 +107,7 @@
#define IL2E (INSN_LOONGSON_2E)
#define IL2F (INSN_LOONGSON_2F)
+#define IL3A (INSN_LOONGSON_3A)
#define P3 INSN_4650
#define L1 INSN_4010
@@ -1858,123 +1859,123 @@ const struct mips_opcode mips_builtin_op
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packushb", "D,S,T", 0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddb", "D,S,T", 0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddh", "D,S,T", 0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddw", "D,S,T", 0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddd", "D,S,T", 0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddsb", "D,S,T", 0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddsh", "D,S,T", 0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddush", "D,S,T", 0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pandn", "D,S,T", 0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pavgb", "D,S,T", 0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pavgh", "D,S,T", 0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pminub", "D,S,T", 0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmovmskb", "D,S", 0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E },
-{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F },
+{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A },
{"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmullh", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"biadd", "D,S", 0x46800005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E },
-{"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F },
+{"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A },
{"pshufh", "D,S,T", 0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psllh", "D,S,T", 0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psllw", "D,S,T", 0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psrah", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psraw", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psrlh", "D,S,T", 0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psrlw", "D,S,T", 0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubb", "D,S,T", 0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubh", "D,S,T", 0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubw", "D,S,T", 0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubd", "D,S,T", 0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubsb", "D,S,T", 0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubsh", "D,S,T", 0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubush", "D,S,T", 0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-10 11:12 ` Mingming Sun
@ 2010-11-10 23:27 ` Maciej W. Rozycki
2010-11-19 16:49 ` Nick Clifton
2010-11-11 10:24 ` Nick Clifton
1 sibling, 1 reply; 14+ messages in thread
From: Maciej W. Rozycki @ 2010-11-10 23:27 UTC (permalink / raw)
To: Mingming Sun; +Cc: Nick Clifton, binutils
On Wed, 10 Nov 2010, Mingming Sun wrote:
> I've got the binutils FSF copyright assignment recently.
> Is this patch ok for binutils?
Overall it looks OK to me, but I cannot approve the change, though I can
make objections. ;) A couple of comments follow.
First I think your new entry should be placed after one for the SB-1A.
Specifically here:
> Index: bfd/elfxx-mips.c
> ===================================================================
> RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
> retrieving revision 1.274
> diff -u -p -r1.274 elfxx-mips.c
> --- bfd/elfxx-mips.c 19 Sep 2010 10:52:17 -0000 1.274
> +++ bfd/elfxx-mips.c 21 Sep 2010 08:52:49 -0000
> @@ -10561,6 +10564,10 @@ mips_set_isa_flags (bfd *abfd)
> val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
> break;
>
> + case bfd_mach_mips_loongson_3a:
> + val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
> + break;
> +
> case bfd_mach_mips_sb1:
> val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
> break;
and here:
> Index: gas/config/tc-mips.c
> ===================================================================
> RCS file: /cvs/src/src/gas/config/tc-mips.c,v
> retrieving revision 1.425
> diff -u -p -r1.425 tc-mips.c
> --- gas/config/tc-mips.c 27 Jul 2010 21:04:59 -0000 1.425
> +++ gas/config/tc-mips.c 21 Sep 2010 08:53:08 -0000
> @@ -15383,6 +15383,7 @@ static const struct mips_cpu_info mips_c
> { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
> { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
> { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
> + { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
>
> /* Broadcom SB-1 CPU core */
> { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
Then:
> Index: include/opcode/mips.h
> ===================================================================
> RCS file: /cvs/src/src/include/opcode/mips.h,v
> retrieving revision 1.67
> diff -u -p -r1.67 mips.h
> --- include/opcode/mips.h 6 Jul 2010 00:02:44 -0000 1.67
> +++ include/opcode/mips.h 21 Sep 2010 08:53:11 -0000
> @@ -594,6 +594,8 @@ static const unsigned int mips_isa_table
> #define INSN_LOONGSON_2E 0x40000000
> /* ST Microelectronics Loongson 2F. */
> #define INSN_LOONGSON_2F 0x80000000
> +/* Loongson 3A. */
> +#define INSN_LOONGSON_3A 0x80000400
> /* RMI Xlr instruction */
> #define INSN_XLR 0x00000020
>
one bit per CPU type and you need to update INSN_CHIP_MASK accordingly.
Maciej
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-10 11:12 ` Mingming Sun
2010-11-10 23:27 ` Maciej W. Rozycki
@ 2010-11-11 10:24 ` Nick Clifton
2010-11-11 13:47 ` Maciej W. Rozycki
1 sibling, 1 reply; 14+ messages in thread
From: Nick Clifton @ 2010-11-11 10:24 UTC (permalink / raw)
To: Mingming Sun; +Cc: binutils
Hi Mingming,
> 2010-09-21 Mingming Sun<mingm.sun@gmail.com>
> bfd/
> * archures.c (bfd_mach_mips_loongson_3a): Defined.
> * bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
> * cpu-mips.c (I_loongson_3a): New add.
> (arch_info_struct): Add loongson_3a.
> * elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
> (mips_set_isa_flags): Add loongson_3a.
> (mips_mach_extensions): Add loongson_3a in MIPS64 extensions.
>
> binutils/
> * readelf.c (get_machine_flags): Add loongson-3a.
>
> gas/
> * config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
> * doc/c-mips.texi (MIPS cpu): Add loongson3a.
>
> include/
> * elf/mips.h (E_MIPS_MACH_LS3A): Defined.
> * opcode/mips.h (INSN_LOONGSON_3A): Defined.
> (CPU_LOONGSON_3A): Defined.
> (OPCODE_IS_MEMBER): Add LOONGSON_3A.
>
> opcodes/
> * mips-dis.c (mips_arch_choices): Add loongson3a.
> * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
> (mips_builtin_opcodes): Modify some instructions' membership from
> IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
Approved and applied - thank you very much for creating this patch.
Cheers
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-11 10:24 ` Nick Clifton
@ 2010-11-11 13:47 ` Maciej W. Rozycki
2010-11-23 17:53 ` Jan Kratochvil
0 siblings, 1 reply; 14+ messages in thread
From: Maciej W. Rozycki @ 2010-11-11 13:47 UTC (permalink / raw)
To: Nick Clifton; +Cc: Mingming Sun, binutils
On Thu, 11 Nov 2010, Nick Clifton wrote:
> Approved and applied - thank you very much for creating this patch.
Have you addressed any of the concerns I had, especially about changes to
include/opcode/mips.h?
Maciej
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-10 23:27 ` Maciej W. Rozycki
@ 2010-11-19 16:49 ` Nick Clifton
2010-11-20 2:13 ` Maciej W. Rozycki
0 siblings, 1 reply; 14+ messages in thread
From: Nick Clifton @ 2010-11-19 16:49 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Mingming Sun, binutils
Hi Maciej,
My apologies for approving Mingming's patch without checking through
your objections first.
I think that the placement of the loongson_3a entry in the elfxx-mips.c
and tc-mips.c is not really that important, so I am inclined to let the
patch stand as it is. But your objections to the include/opcodes/mips.h
patch is valid:
>> > #define INSN_LOONGSON_2F 0x80000000
>> > +/* Loongson 3A. */
>> > +#define INSN_LOONGSON_3A 0x80000400
>> > /* RMI Xlr instruction */
>> > #define INSN_XLR 0x00000020
>
> one bit per CPU type and you need to update INSN_CHIP_MASK accordingly.
How about this fix to correct the problem:
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.68
diff -u -3 -p -r1.68 mips.h
--- include/opcode/mips.h 11 Nov 2010 10:23:38 -0000 1.68
+++ include/opcode/mips.h 19 Nov 2010 16:43:22 -0000
@@ -556,8 +556,6 @@ static const unsigned int mips_isa_table
#define INSN_DSP 0x00001000
#define INSN_DSP64 0x00002000
-/* 0x00004000 is unused. */
-
/* MIPS-3D ASE */
#define INSN_MIPS3D 0x00008000
@@ -595,7 +593,8 @@ static const unsigned int mips_isa_table
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
/* Loongson 3A. */
-#define INSN_LOONGSON_3A 0x80000400
+#define INSN_LOONGSON_3A 0x00004000
+
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
Ie making use of the one unused bit in the mask. Of course this does
mean that next time a new MIPS architecture is added, this whole problem
is going to have to be revisited.
Cheers
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-19 16:49 ` Nick Clifton
@ 2010-11-20 2:13 ` Maciej W. Rozycki
2010-11-23 3:50 ` Mingming Sun
2010-11-23 16:56 ` Nick Clifton
0 siblings, 2 replies; 14+ messages in thread
From: Maciej W. Rozycki @ 2010-11-20 2:13 UTC (permalink / raw)
To: Nick Clifton; +Cc: Mingming Sun, binutils
Hi Nick,
> My apologies for approving Mingming's patch without checking through your
> objections first.
No worry -- we all make mistakes from time to time and this one can be
fixed quite easily. :)
> I think that the placement of the loongson_3a entry in the elfxx-mips.c and
> tc-mips.c is not really that important, so I am inclined to let the patch
> stand as it is.
The sort order of these lists has been broken previously already. This
always brings up confusion. I'll post a separate change to clean them up.
> But your objections to the include/opcodes/mips.h patch is
> valid:
>
> > > > #define INSN_LOONGSON_2F 0x80000000
> > > > +/* Loongson 3A. */
> > > > +#define INSN_LOONGSON_3A 0x80000400
> > > > /* RMI Xlr instruction */
> > > > #define INSN_XLR 0x00000020
> >
> > one bit per CPU type and you need to update INSN_CHIP_MASK accordingly.
>
> How about this fix to correct the problem:
>
> Index: include/opcode/mips.h
> ===================================================================
> RCS file: /cvs/src/src/include/opcode/mips.h,v
> retrieving revision 1.68
> diff -u -3 -p -r1.68 mips.h
> --- include/opcode/mips.h 11 Nov 2010 10:23:38 -0000 1.68
> +++ include/opcode/mips.h 19 Nov 2010 16:43:22 -0000
> @@ -556,8 +556,6 @@ static const unsigned int mips_isa_table
> #define INSN_DSP 0x00001000
> #define INSN_DSP64 0x00002000
> -/* 0x00004000 is unused. */
> -
> /* MIPS-3D ASE */
> #define INSN_MIPS3D 0x00008000
>
> @@ -595,7 +593,8 @@ static const unsigned int mips_isa_table
> /* ST Microelectronics Loongson 2F. */
> #define INSN_LOONGSON_2F 0x80000000
> /* Loongson 3A. */
> -#define INSN_LOONGSON_3A 0x80000400
> +#define INSN_LOONGSON_3A 0x00004000
> +
> /* RMI Xlr instruction */
> #define INSN_XLR 0x00000020
>
>
> Ie making use of the one unused bit in the mask. Of course this does mean
> that next time a new MIPS architecture is added, this whole problem is going
> to have to be revisited.
Well, 0x00004000 has already been assigned to the ASE range
(INSN_ASE_MASK), so we'd have to deallocate it there to use it as a CPU
flag.
What I actually have in mind is this:
2010-11-20 Maciej W. Rozycki <macro@linux-mips.org>
include/opcode/
* mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
(INSN_LOONGSON_3A): Clear bit 31.
I have passed it though regression testing with the mips64-linux target
with no problems reported.
It looks like we still have got a couple of available bits left in the
mask as indicated by (INSN_CHIP_MASK | INSN_ASE_MASK | INSN_ISA_MASK), so
no need to worry about running short of them for a (short) while yet.
But this list begs for tidying up as well.
Maciej
binutils-2.20.51-20100925-3a-fix.patch
Index: binutils-2.20.51/include/opcode/mips.h
===================================================================
--- binutils-2.20.51.orig/include/opcode/mips.h
+++ binutils-2.20.51/include/opcode/mips.h
@@ -544,7 +544,7 @@ static const unsigned int mips_isa_table
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff0820
+#define INSN_CHIP_MASK 0xc3ff0c20
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
@@ -595,7 +595,7 @@ static const unsigned int mips_isa_table
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
/* Loongson 3A. */
-#define INSN_LOONGSON_3A 0x80000400
+#define INSN_LOONGSON_3A 0x00000400
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-20 2:13 ` Maciej W. Rozycki
@ 2010-11-23 3:50 ` Mingming Sun
2010-11-23 16:55 ` Nick Clifton
2010-11-23 16:56 ` Nick Clifton
1 sibling, 1 reply; 14+ messages in thread
From: Mingming Sun @ 2010-11-23 3:50 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Nick Clifton, binutils
[-- Attachment #1: Type: text/plain, Size: 4561 bytes --]
On Sat, Nov 20, 2010 at 10:13 AM, Maciej W. Rozycki
<macro@linux-mips.org> wrote:
> Hi Nick,
>
>> My apologies for approving Mingming's patch without checking through your
>> objections first.
>
> No worry -- we all make mistakes from time to time and this one can be
> fixed quite easily. :)
>
>> I think that the placement of the loongson_3a entry in the elfxx-mips.c and
>> tc-mips.c is not really that important, so I am inclined to let the patch
>> stand as it is.
>
> The sort order of these lists has been broken previously already. This
> always brings up confusion. I'll post a separate change to clean them up.
>
>> But your objections to the include/opcodes/mips.h patch is
>> valid:
>>
>> > > > #define INSN_LOONGSON_2F 0x80000000
>> > > > +/* Loongson 3A. */
>> > > > +#define INSN_LOONGSON_3A 0x80000400
>> > > > /* RMI Xlr instruction */
>> > > > #define INSN_XLR 0x00000020
>> >
>> > one bit per CPU type and you need to update INSN_CHIP_MASK accordingly.
>>
>> How about this fix to correct the problem:
>>
>> Index: include/opcode/mips.h
>> ===================================================================
>> RCS file: /cvs/src/src/include/opcode/mips.h,v
>> retrieving revision 1.68
>> diff -u -3 -p -r1.68 mips.h
>> --- include/opcode/mips.h 11 Nov 2010 10:23:38 -0000 1.68
>> +++ include/opcode/mips.h 19 Nov 2010 16:43:22 -0000
>> @@ -556,8 +556,6 @@ static const unsigned int mips_isa_table
>> #define INSN_DSP 0x00001000
>> #define INSN_DSP64 0x00002000
>> -/* 0x00004000 is unused. */
>> -
>> /* MIPS-3D ASE */
>> #define INSN_MIPS3D 0x00008000
>>
>> @@ -595,7 +593,8 @@ static const unsigned int mips_isa_table
>> /* ST Microelectronics Loongson 2F. */
>> #define INSN_LOONGSON_2F 0x80000000
>> /* Loongson 3A. */
>> -#define INSN_LOONGSON_3A 0x80000400
>> +#define INSN_LOONGSON_3A 0x00004000
>> +
>> /* RMI Xlr instruction */
>> #define INSN_XLR 0x00000020
>>
>>
>> Ie making use of the one unused bit in the mask. Of course this does mean
>> that next time a new MIPS architecture is added, this whole problem is going
>> to have to be revisited.
>
> Well, 0x00004000 has already been assigned to the ASE range
> (INSN_ASE_MASK), so we'd have to deallocate it there to use it as a CPU
> flag.
>
> What I actually have in mind is this:
>
> 2010-11-20 Maciej W. Rozycki <macro@linux-mips.org>
>
> include/opcode/
> * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
> (INSN_LOONGSON_3A): Clear bit 31.
>
> I have passed it though regression testing with the mips64-linux target
> with no problems reported.
>
> It looks like we still have got a couple of available bits left in the
> mask as indicated by (INSN_CHIP_MASK | INSN_ASE_MASK | INSN_ISA_MASK), so
> no need to worry about running short of them for a (short) while yet.
> But this list begs for tidying up as well.
>
> Maciej
>
> binutils-2.20.51-20100925-3a-fix.patch
> Index: binutils-2.20.51/include/opcode/mips.h
> ===================================================================
> --- binutils-2.20.51.orig/include/opcode/mips.h
> +++ binutils-2.20.51/include/opcode/mips.h
> @@ -544,7 +544,7 @@ static const unsigned int mips_isa_table
> { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
>
> /* Masks used for Chip specific instructions. */
> -#define INSN_CHIP_MASK 0xc3ff0820
> +#define INSN_CHIP_MASK 0xc3ff0c20
>
> /* Cavium Networks Octeon instructions. */
> #define INSN_OCTEON 0x00000800
> @@ -595,7 +595,7 @@ static const unsigned int mips_isa_table
> /* ST Microelectronics Loongson 2F. */
> #define INSN_LOONGSON_2F 0x80000000
> /* Loongson 3A. */
> -#define INSN_LOONGSON_3A 0x80000400
> +#define INSN_LOONGSON_3A 0x00000400
> /* RMI Xlr instruction */
> #define INSN_XLR 0x00000020
>
Apologies for placing the Loongosn3A entry in a wrong place. This patch fix the
problem in elfxx-mips.c and tc-mips.c.
Maciej's patch for mips.h is Ok to me, thanks :)
Thanks,
Mingming Sun
2010-11-23 Mingming Sun <mingm.sun@gmail.com>
bfd/
* elfxx-mips.c (mips_set_isa_flags): Move bfd_mach_loongson_3a
after bfd_mach_mips_sb1.
gas/
* config/tc-mips.c (mips_cpu_info_table): Move loongson3a after sb1.
[-- Attachment #2: patch.txt --]
[-- Type: text/plain, Size: 1871 bytes --]
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.280
diff -u -p -r1.280 elfxx-mips.c
--- bfd/elfxx-mips.c 11 Nov 2010 10:23:35 -0000 1.280
+++ bfd/elfxx-mips.c 22 Nov 2010 05:23:52 -0000
@@ -10559,14 +10559,14 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
break;
- case bfd_mach_mips_loongson_3a:
- val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
- break;
-
case bfd_mach_mips_sb1:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
+ case bfd_mach_mips_loongson_3a:
+ val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
+ break;
+
case bfd_mach_mips_octeon:
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
break;
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.433
diff -u -p -r1.433 tc-mips.c
--- gas/config/tc-mips.c 13 Nov 2010 11:59:20 -0000 1.433
+++ gas/config/tc-mips.c 22 Nov 2010 05:23:58 -0000
@@ -15358,7 +15358,6 @@ static const struct mips_cpu_info mips_c
{ "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
{ "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
{ "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
- { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
/* Broadcom SB-1 CPU core */
{ "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
@@ -15366,6 +15365,8 @@ static const struct mips_cpu_info mips_c
/* Broadcom SB-1A CPU core */
{ "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
ISA_MIPS64, CPU_SB1 },
+
+ { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
/* MIPS 64 Release 2 */
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-23 3:50 ` Mingming Sun
@ 2010-11-23 16:55 ` Nick Clifton
0 siblings, 0 replies; 14+ messages in thread
From: Nick Clifton @ 2010-11-23 16:55 UTC (permalink / raw)
To: Mingming Sun; +Cc: Maciej W. Rozycki, binutils
Hi Mingming,
> 2010-11-23 Mingming Sun<mingm.sun@gmail.com>
> bfd/
> * elfxx-mips.c (mips_set_isa_flags): Move bfd_mach_loongson_3a
> after bfd_mach_mips_sb1.
>
> gas/
> * config/tc-mips.c (mips_cpu_info_table): Move loongson3a after sb1.
Thanks - I have checked this patch in along with Maciej's patch.
Cheers
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-20 2:13 ` Maciej W. Rozycki
2010-11-23 3:50 ` Mingming Sun
@ 2010-11-23 16:56 ` Nick Clifton
1 sibling, 0 replies; 14+ messages in thread
From: Nick Clifton @ 2010-11-23 16:56 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Mingming Sun, binutils
Hi Maciej,
> 2010-11-20 Maciej W. Rozycki<macro@linux-mips.org>
>
> include/opcode/
> * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
> (INSN_LOONGSON_3A): Clear bit 31.
Thanks - I have checked this patch in along with Mingming's.
Cheers
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-11 13:47 ` Maciej W. Rozycki
@ 2010-11-23 17:53 ` Jan Kratochvil
2010-11-23 20:25 ` Richard Sandiford
0 siblings, 1 reply; 14+ messages in thread
From: Jan Kratochvil @ 2010-11-23 17:53 UTC (permalink / raw)
To: Maciej W. Rozycki; +Cc: Nick Clifton, Mingming Sun, binutils
On Thu, 11 Nov 2010 14:47:25 +0100, Maciej W. Rozycki wrote:
> On Thu, 11 Nov 2010, Nick Clifton wrote:
>
> > Approved and applied - thank you very much for creating this patch.
>
> Have you addressed any of the concerns I had, especially about changes to
> include/opcode/mips.h?
Getting now on Fedora 14 x86_64 ./configure --enable-targets=all (...):
make[4]: Entering directory `.../opcodes'
/bin/sh ./libtool --tag=CC --mode=compile gcc -DHAVE_CONFIG_H -I. -I. -I. -I../bfd -I./../include -I./../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -m64 -ggdb2 -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -MT mips-dis.lo -MD -MP -MF .deps/mips-dis.Tpo -c -o mips-dis.lo mips-dis.c
libtool: compile: gcc -DHAVE_CONFIG_H -I. -I. -I. -I../bfd -I./../include -I./../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -m64 -ggdb2 -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -MT mips-dis.lo -MD -MP -MF .deps/mips-dis.Tpo -c mips-dis.c -o mips-dis.o
cc1: warnings being treated as errors
In file included from mips-dis.c:27:0:
./../include/opcode/mips.h:598:0: error: "INSN_LOONGSON_3A" redefined
./../include/opcode/mips.h:596:0: note: this is the location of the previous definition
mips-dis.c:512:17: error: ‘INSN_LOONGSON_2F’ undeclared here (not in a function)
mips-dis.c: In function ‘print_insn_mips’:
mips-dis.c:1404:14: error: invalid operands to binary & (have ‘long unsigned int’ and ‘const struct mips_arch_choice *’)
make[4]: *** [mips-dis.lo] Error 1
Thanks,
Jan
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH MIPS][LS3A]Generic Support
2010-11-23 17:53 ` Jan Kratochvil
@ 2010-11-23 20:25 ` Richard Sandiford
0 siblings, 0 replies; 14+ messages in thread
From: Richard Sandiford @ 2010-11-23 20:25 UTC (permalink / raw)
To: Jan Kratochvil; +Cc: Maciej W. Rozycki, Nick Clifton, Mingming Sun, binutils
Jan Kratochvil <jan.kratochvil@redhat.com> writes:
> On Thu, 11 Nov 2010 14:47:25 +0100, Maciej W. Rozycki wrote:
>> On Thu, 11 Nov 2010, Nick Clifton wrote:
>>
>> > Approved and applied - thank you very much for creating this patch.
>>
>> Have you addressed any of the concerns I had, especially about changes to
>> include/opcode/mips.h?
>
> Getting now on Fedora 14 x86_64 ./configure --enable-targets=all (...):
>
> make[4]: Entering directory `.../opcodes'
> /bin/sh ./libtool --tag=CC --mode=compile gcc -DHAVE_CONFIG_H -I. -I. -I. -I../bfd -I./../include -I./../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -m64 -ggdb2 -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -MT mips-dis.lo -MD -MP -MF .deps/mips-dis.Tpo -c -o mips-dis.lo mips-dis.c
> libtool: compile: gcc -DHAVE_CONFIG_H -I. -I. -I. -I../bfd -I./../include -I./../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -m64 -ggdb2 -pipe -Wall -Wp,-D_FORTIFY_SOURCE=2 -fexceptions -fstack-protector --param=ssp-buffer-size=4 -MT mips-dis.lo -MD -MP -MF .deps/mips-dis.Tpo -c mips-dis.c -o mips-dis.o
> cc1: warnings being treated as errors
> In file included from mips-dis.c:27:0:
> ./../include/opcode/mips.h:598:0: error: "INSN_LOONGSON_3A" redefined
> ./../include/opcode/mips.h:596:0: note: this is the location of the previous definition
I've installed the patch below in Nick's absence. (Good luck Nick!)
Richard
include/opcode/
* mips.h: Fix previous commit.
Index: include/opcode/mips.h
===================================================================
--- include/opcode/mips.h 2010-11-23 20:20:46.000000000 +0000
+++ include/opcode/mips.h 2010-11-23 20:20:48.000000000 +0000
@@ -593,9 +593,9 @@ #define INSN_DSPR2 0x2000
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
-#define INSN_LOONGSON_3A 0x00000400
+#define INSN_LOONGSON_2F 0x80000000
/* Loongson 3A. */
-#define INSN_LOONGSON_3A 0x80000400
+#define INSN_LOONGSON_3A 0x00000400
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH MIPS][LS3A]Generic Support
@ 2010-09-24 5:58 Mingming Sun
0 siblings, 0 replies; 14+ messages in thread
From: Mingming Sun @ 2010-09-24 5:58 UTC (permalink / raw)
To: binutils
[-- Attachment #1: Type: text/plain, Size: 1140 bytes --]
Hello,
This patch adds generic support for Loongson 3A CPU.
It also makes some Loongson 2F instructions available for Loongson 3A.
Ok?
2010-09-21 Mingming Sun <mingm.sun@gmail.com>
bfd/
* archures.c (bfd_mach_mips_loongson_3a): Defined.
* bfd-in2.h (bfd_mach_mips_loongson_3a): Defined.
* cpu-mips.c (I_loongson_3a): New add.
(arch_info_struct): Add loongson_3a.
* elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a.
(mips_set_isa_flags): Add loongson_3a.
(mips_mach_extensions): Add loongson_3a in MIPS64 extensions.
binutils/
* readelf.c (get_machine_flags): Add loongson-3a.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64.
* doc/c-mips.texi (MIPS cpu): Add loongson3a.
include/
* elf/mips.h (E_MIPS_MACH_LS3A): Defined.
* opcode/mips.h (INSN_LOONGSON_3A): Defined.
(CPU_LOONGSON_3A): Defined.
(OPCODE_IS_MEMBER): Add LOONGSON_3A.
opcodes/
* mips-dis.c (mips_arch_choices): Add loongson3a.
* mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
(mips_builtin_opcodes): Modify some instructions' membership from
IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
[-- Attachment #2: binutils-3a.patch --]
[-- Type: application/octet-stream, Size: 23707 bytes --]
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.150
diff -u -p -r1.150 archures.c
--- bfd/archures.c 23 Jul 2010 14:52:46 -0000 1.150
+++ bfd/archures.c 21 Sep 2010 08:52:40 -0000
@@ -173,6 +173,7 @@ DESCRIPTION
.#define bfd_mach_mips5 5
.#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_loongson_2f 3002
+.#define bfd_mach_mips_loongson_3a 3003
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *}
Index: bfd/bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.517
diff -u -p -r1.517 bfd-in2.h
--- bfd/bfd-in2.h 18 Aug 2010 12:24:04 -0000 1.517
+++ bfd/bfd-in2.h 21 Sep 2010 08:52:44 -0000
@@ -1839,6 +1839,7 @@ enum bfd_architecture
#define bfd_mach_mips5 5
#define bfd_mach_mips_loongson_2e 3001
#define bfd_mach_mips_loongson_2f 3002
+#define bfd_mach_mips_loongson_3a 3003
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.34
diff -u -p -r1.34 cpu-mips.c
--- bfd/cpu-mips.c 6 May 2010 15:02:24 -0000 1.34
+++ bfd/cpu-mips.c 21 Sep 2010 08:52:44 -0000
@@ -91,6 +91,7 @@ enum
I_sb1,
I_loongson_2e,
I_loongson_2f,
+ I_loongson_3a,
I_mipsocteon,
I_xlr
};
@@ -130,6 +131,7 @@ static const bfd_arch_info_type arch_inf
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
+ N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, 0)
};
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.274
diff -u -p -r1.274 elfxx-mips.c
--- bfd/elfxx-mips.c 19 Sep 2010 10:52:17 -0000 1.274
+++ bfd/elfxx-mips.c 21 Sep 2010 08:52:49 -0000
@@ -5963,6 +5963,9 @@ _bfd_elf_mips_mach (flagword flags)
case E_MIPS_MACH_LS2F:
return bfd_mach_mips_loongson_2f;
+ case E_MIPS_MACH_LS3A:
+ return bfd_mach_mips_loongson_3a;
+
case E_MIPS_MACH_OCTEON:
return bfd_mach_mips_octeon;
@@ -10561,6 +10564,10 @@ mips_set_isa_flags (bfd *abfd)
val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
break;
+ case bfd_mach_mips_loongson_3a:
+ val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A;
+ break;
+
case bfd_mach_mips_sb1:
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
@@ -12263,6 +12270,7 @@ static const struct mips_mach_extension
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
{ bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
{ bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
+ { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64 },
/* MIPS V extensions. */
{ bfd_mach_mipsisa64, bfd_mach_mips5 },
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.515
diff -u -p -r1.515 readelf.c
--- binutils/readelf.c 7 Sep 2010 15:02:17 -0000 1.515
+++ binutils/readelf.c 21 Sep 2010 08:53:02 -0000
@@ -2426,6 +2426,7 @@ get_machine_flags (unsigned e_flags, uns
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
+ case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break;
case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.425
diff -u -p -r1.425 tc-mips.c
--- gas/config/tc-mips.c 27 Jul 2010 21:04:59 -0000 1.425
+++ gas/config/tc-mips.c 21 Sep 2010 08:53:08 -0000
@@ -15383,6 +15383,7 @@ static const struct mips_cpu_info mips_c
{ "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
{ "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
{ "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
+ { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
/* Broadcom SB-1 CPU core */
{ "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
Index: gas/doc/c-mips.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-mips.texi,v
retrieving revision 1.55
diff -u -p -r1.55 c-mips.texi
--- gas/doc/c-mips.texi 25 Feb 2010 11:15:47 -0000 1.55
+++ gas/doc/c-mips.texi 21 Sep 2010 08:53:09 -0000
@@ -298,6 +298,7 @@ sb1,
sb1a,
loongson2e,
loongson2f,
+loongson3a,
octeon,
xlr
@end quotation
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.43
diff -u -p -r1.43 mips.h
--- include/elf/mips.h 15 Apr 2010 10:26:08 -0000 1.43
+++ include/elf/mips.h 21 Sep 2010 08:53:11 -0000
@@ -222,6 +222,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_9000 0x00990000
#define E_MIPS_MACH_LS2E 0x00A00000
#define E_MIPS_MACH_LS2F 0x00A10000
+#define E_MIPS_MACH_LS3A 0x00A20000
\f
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.67
diff -u -p -r1.67 mips.h
--- include/opcode/mips.h 6 Jul 2010 00:02:44 -0000 1.67
+++ include/opcode/mips.h 21 Sep 2010 08:53:11 -0000
@@ -594,6 +594,8 @@ static const unsigned int mips_isa_table
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* Loongson 3A. */
+#define INSN_LOONGSON_3A 0x80000400
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
@@ -647,6 +649,7 @@ static const unsigned int mips_isa_table
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
+#define CPU_LOONGSON_3A 3003
#define CPU_OCTEON 6501
#define CPU_XLR 887682 /* decimal 'XLR' */
@@ -680,6 +683,8 @@ static const unsigned int mips_isa_table
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|| (cpu == CPU_LOONGSON_2F \
&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
+ || (cpu == CPU_LOONGSON_3A \
+ && ((insn)->membership & INSN_LOONGSON_3A) != 0) \
|| (cpu == CPU_OCTEON \
&& ((insn)->membership & INSN_OCTEON) != 0) \
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.81
diff -u -p -r1.81 mips-dis.c
--- opcodes/mips-dis.c 6 Jul 2010 00:06:04 -0000 1.81
+++ opcodes/mips-dis.c 21 Sep 2010 08:53:12 -0000
@@ -512,6 +512,10 @@ const struct mips_arch_choice mips_arch_
ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric,
NULL, 0, mips_hwr_names_numeric },
+ { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
+ ISA_MIPS64 | INSN_LOONGSON_3A, mips_cp0_names_numeric,
+ NULL, 0, mips_hwr_names_numeric },
+
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
mips_hwr_names_numeric },
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.78
diff -u -p -r1.78 mips-opc.c
--- opcodes/mips-opc.c 14 Sep 2010 23:49:04 -0000 1.78
+++ opcodes/mips-opc.c 21 Sep 2010 08:53:13 -0000
@@ -107,6 +107,7 @@
#define IL2E (INSN_LOONGSON_2E)
#define IL2F (INSN_LOONGSON_2F)
+#define IL3A (INSN_LOONGSON_3A)
#define P3 INSN_4650
#define L1 INSN_4010
@@ -1858,123 +1859,123 @@ const struct mips_opcode mips_builtin_op
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"packsswh", "D,S,T", 0x4b200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packushb", "D,S,T", 0x47600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"packushb", "D,S,T", 0x4b600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddb", "D,S,T", 0x47c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddb", "D,S,T", 0x4bc00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddh", "D,S,T", 0x47400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddh", "D,S,T", 0x4b400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddw", "D,S,T", 0x47600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddw", "D,S,T", 0x4b600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddd", "D,S,T", 0x47e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddd", "D,S,T", 0x4be00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddsb", "D,S,T", 0x47800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddsb", "D,S,T", 0x4b800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddsh", "D,S,T", 0x47000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddsh", "D,S,T", 0x4b000000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddusb", "D,S,T", 0x47a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddusb", "D,S,T", 0x4ba00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"paddush", "D,S,T", 0x47200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"paddush", "D,S,T", 0x4b200000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pandn", "D,S,T", 0x47e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pandn", "D,S,T", 0x4be00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pavgb", "D,S,T", 0x46600000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pavgb", "D,S,T", 0x4b200008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pavgh", "D,S,T", 0x46400000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pavgh", "D,S,T", 0x4b000008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpeqb", "D,S,T", 0x46c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpeqb", "D,S,T", 0x4b800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpeqh", "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpeqh", "D,S,T", 0x4b400009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpeqw", "D,S,T", 0x46400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpeqw", "D,S,T", 0x4b000009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpgtb", "D,S,T", 0x46e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpgtb", "D,S,T", 0x4ba00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpgth", "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpgth", "D,S,T", 0x4b600009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pcmpgtw", "D,S,T", 0x46600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pcmpgtw", "D,S,T", 0x4b200009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pextrh", "D,S,T", 0x45c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pextrh", "D,S,T", 0x4b40000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_0", "D,S,T", 0x47800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_0", "D,S,T", 0x4b800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_1", "D,S,T", 0x47a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_1", "D,S,T", 0x4ba00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_2", "D,S,T", 0x47c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_2", "D,S,T", 0x4bc00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pinsrh_3", "D,S,T", 0x47e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pinsrh_3", "D,S,T", 0x4be00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmaddhw", "D,S,T", 0x45e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmaddhw", "D,S,T", 0x4b60000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmaxsh", "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmaxsh", "D,S,T", 0x4b400008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmaxub", "D,S,T", 0x46c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmaxub", "D,S,T", 0x4b800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pminsh", "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pminsh", "D,S,T", 0x4b600008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pminub", "D,S,T", 0x46e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pminub", "D,S,T", 0x4ba00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmovmskb", "D,S", 0x46a00005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E },
-{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F },
+{"pmovmskb", "D,S", 0x4ba0000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A },
{"pmulhuh", "D,S,T", 0x46e00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmulhuh", "D,S,T", 0x4ba0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmulhh", "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmulhh", "D,S,T", 0x4b60000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmullh", "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmullh", "D,S,T", 0x4b40000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pmuluw", "D,S,T", 0x46c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pmuluw", "D,S,T", 0x4b80000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"pasubub", "D,S,T", 0x45a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pasubub", "D,S,T", 0x4b20000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"biadd", "D,S", 0x46800005, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2E },
-{"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F },
+{"biadd", "D,S", 0x4b80000f, 0xffff003f, RD_S|WR_D|FP_D, 0, IL2F|IL3A },
{"pshufh", "D,S,T", 0x47000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"pshufh", "D,S,T", 0x4b000002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psllh", "D,S,T", 0x46600002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psllh", "D,S,T", 0x4b20000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psllw", "D,S,T", 0x46400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psllw", "D,S,T", 0x4b00000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psrah", "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psrah", "D,S,T", 0x4b60000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psraw", "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psraw", "D,S,T", 0x4b40000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psrlh", "D,S,T", 0x46600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psrlh", "D,S,T", 0x4b20000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psrlw", "D,S,T", 0x46400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psrlw", "D,S,T", 0x4b00000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubb", "D,S,T", 0x47c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubb", "D,S,T", 0x4bc00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubh", "D,S,T", 0x47400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubh", "D,S,T", 0x4b400001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubw", "D,S,T", 0x47600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubw", "D,S,T", 0x4b600001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubd", "D,S,T", 0x47e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubd", "D,S,T", 0x4be00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubsb", "D,S,T", 0x47800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubsb", "D,S,T", 0x4b800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubsh", "D,S,T", 0x47000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubsh", "D,S,T", 0x4b000001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubusb", "D,S,T", 0x47a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubusb", "D,S,T", 0x4ba00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"psubush", "D,S,T", 0x47200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"psubush", "D,S,T", 0x4b200001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpckhbh", "D,S,T", 0x47600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpckhbh", "D,S,T", 0x4b600003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpckhhw", "D,S,T", 0x47200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpckhhw", "D,S,T", 0x4b200003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpckhwd", "D,S,T", 0x46e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpckhwd", "D,S,T", 0x4ba0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpcklbh", "D,S,T", 0x47400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpcklbh", "D,S,T", 0x4b400003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpcklhw", "D,S,T", 0x47000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpcklhw", "D,S,T", 0x4b000003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"punpcklwd", "D,S,T", 0x46c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
user to put in nops as necessary. These are at the end so that the
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2010-11-23 20:25 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <8762xu164h.fsf@firetop.home>
2010-09-27 12:55 ` [PATCH MIPS][LS3A]Generic Support Nick Clifton
2010-09-28 1:28 ` Mingming Sun
2010-11-10 11:12 ` Mingming Sun
2010-11-10 23:27 ` Maciej W. Rozycki
2010-11-19 16:49 ` Nick Clifton
2010-11-20 2:13 ` Maciej W. Rozycki
2010-11-23 3:50 ` Mingming Sun
2010-11-23 16:55 ` Nick Clifton
2010-11-23 16:56 ` Nick Clifton
2010-11-11 10:24 ` Nick Clifton
2010-11-11 13:47 ` Maciej W. Rozycki
2010-11-23 17:53 ` Jan Kratochvil
2010-11-23 20:25 ` Richard Sandiford
2010-09-24 5:58 Mingming Sun
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