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From: "Tsing" <lei.wang@oss.cipunited.com>
To: <macro@orcam.me.uk>
Cc: <binutils@sourceware.org>
Subject: Re: [PATCH] Add GINV(+VIRT) ASE for MIPSr6
Date: Thu, 01 Jun 2023 12:43:40 +0800	[thread overview]
Message-ID: <877d12b4-1b6d-61f0-0780-339c347b7973@oss.cipunited.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2305191944210.50034@angie.orcam.me.uk>

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Hi.
Thanks for the advise on formatting, I will review the code and keep you updated.

>I take it the encoding is correct, as I can't find it in published docs, 
>and the instruction itself is only mentioned once, in the context of SYNC.
>
>How did you verify your change?

The encoding is documented in the I6500 core programming guide and there is 
also a description of the `GINVGT` instruction in the MIPS64 I6500 System Instruction Guide. 
You can find the docs here:
page 176 of https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MIPS_ Warrior_I6500_ProgrammerGuide_MD01179_P_1.00.pdf

Thanks.
Tsing

      reply	other threads:[~2023-06-01  4:43 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-18  8:57 Tsing
2023-05-22 14:02 ` Maciej W. Rozycki
2023-06-01  4:43   ` Tsing [this message]

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