From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 115579 invoked by alias); 21 Apr 2017 12:27:42 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 115554 invoked by uid 89); 21 Apr 2017 12:27:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=ham version=3.3.2 spammy= X-HELO: aserp1040.oracle.com Received: from aserp1040.oracle.com (HELO aserp1040.oracle.com) (141.146.126.69) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 21 Apr 2017 12:27:40 +0000 Received: from aserv0021.oracle.com (aserv0021.oracle.com [141.146.126.233]) by aserp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id v3LCRdGK014595 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 21 Apr 2017 12:27:40 GMT Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by aserv0021.oracle.com (8.13.8/8.14.4) with ESMTP id v3LCRdM4016250 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Fri, 21 Apr 2017 12:27:39 GMT Received: from abhmp0003.oracle.com (abhmp0003.oracle.com [141.146.116.9]) by aserv0121.oracle.com (8.13.8/8.13.8) with ESMTP id v3LCRbCr009343 for ; Fri, 21 Apr 2017 12:27:38 GMT Received: from termi.oracle.com (/10.175.218.139) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 21 Apr 2017 05:27:37 -0700 From: jose.marchesi@oracle.com (Jose E. Marchesi) To: binutils@sourceware.org Subject: [PATCH][COMMITTED] opcodes: mark SPARC RETT instructions as v6notv9. Date: Fri, 21 Apr 2017 12:27:00 -0000 Message-ID: <878tmukkss.fsf@oracle.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-IsSubscribed: yes X-SW-Source: 2017-04/txt/msg00186.txt.bz2 This prevents the disassembler to show `return' instructions as `rett' in V9 and later architectures. 2017-04-21 Jose E. Marchesi * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c index c302d83..021a5d8 100644 --- a/opcodes/sparc-opc.c +++ b/opcodes/sparc-opc.c @@ -788,13 +788,13 @@ ldtxa (0xEB), /* #ASI_TWINX_SL */ { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, 0, v6 }, { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */ -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+rs2 */ -{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1,%g0 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X */ -{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+0 */ +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+rs2 */ +{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1,%g0 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X */ +{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+0 */ { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, 0, v6 },