From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32234 invoked by alias); 18 Oct 2013 08:04:59 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 32221 invoked by uid 89); 18 Oct 2013 08:04:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-we0-f171.google.com Received: from mail-we0-f171.google.com (HELO mail-we0-f171.google.com) (74.125.82.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 18 Oct 2013 08:04:57 +0000 Received: by mail-we0-f171.google.com with SMTP id t60so3304024wes.2 for ; Fri, 18 Oct 2013 01:04:54 -0700 (PDT) X-Received: by 10.180.100.33 with SMTP id ev1mr1823899wib.18.1382083493913; Fri, 18 Oct 2013 01:04:53 -0700 (PDT) Received: from localhost ([2.28.235.51]) by mx.google.com with ESMTPSA id b7sm830890wiz.8.2013.10.18.01.04.52 for (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128/128); Fri, 18 Oct 2013 01:04:53 -0700 (PDT) From: Richard Sandiford To: Chao-Ying Fu Mail-Followup-To: Chao-Ying Fu ,"'Maciej W. Rozycki'" , "'binutils\@sourceware.org'" , rdsandiford@googlemail.com Cc: "'Maciej W. Rozycki'" , "'binutils\@sourceware.org'" Subject: Re: [PATCH] Reorder MSA branches References: <81D57523CB07B24881D63DE650C6ED824C35B3F9@BADAG01.ba.imgtec.org> Date: Fri, 18 Oct 2013 08:04:00 -0000 In-Reply-To: <81D57523CB07B24881D63DE650C6ED824C35B3F9@BADAG01.ba.imgtec.org> (Chao-Ying Fu's message of "Fri, 18 Oct 2013 00:18:04 +0000") Message-ID: <878uxr6m3f.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2013-10/txt/msg00259.txt.bz2 Chao-Ying Fu writes: > Version 2. > Because the MSA registers share the FP registers (if the FPU is present), > we combine FP and MSA register dependences together. I think we should go for this one. The patch looks good with the testcase added to the testsuite. One very minor formatting nit though: > @@ -4161,7 +4161,8 @@ fpr_read_mask (const struct mips_cl_insn > unsigned long pinfo; > unsigned int mask; > > - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC), > + mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC) > + | (1 << OP_REG_MSA), > insn_read_mask (ip->insn_mo)); > pinfo = ip->insn_mo->pinfo; > /* Conservatively treat all operands to an FP_D instruction are doubles. > @@ -4179,7 +4180,8 @@ fpr_write_mask (const struct mips_cl_ins > unsigned long pinfo; > unsigned int mask; > > - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC), > + mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC) > + | (1 << OP_REG_MSA), > insn_write_mask (ip->insn_mo)); > pinfo = ip->insn_mo->pinfo; > /* Conservatively treat all operands to an FP_D instruction are doubles. In these two cases, please add an extra "(" (the GCC emacs indentation rule). mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) | (1 << OP_REG_MSA)), Thanks, Richard