* [PATCH, MIPS] Minor amendments to R6 opcode table
@ 2014-12-16 14:41 Matthew Fortune
2014-12-16 20:49 ` Richard Sandiford
0 siblings, 1 reply; 2+ messages in thread
From: Matthew Fortune @ 2014-12-16 14:41 UTC (permalink / raw)
To: binutils; +Cc: Richard Sandiford
The NAL alias for (BLTZAL $0, <imm>) introduced in R6 was not supposed
to have a displacement exposed to the user as the instruction will never
branch so a displacement is entirely redundant. Instead the instruction
just hard codes a zero displacement.
Also the JIALC instruction forms the basic form of a compact JALR so we
define an alias to make it easy to just add a 'C' to JALR to create a
compact form.
OK to commit (and backport to 2.25)?
Thanks,
Matthew
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC.
Remove the operand from NAL.
gas/testsuite/
* gas/mips/r6.s: Test JALRC and NAL
* gas/mips/r6-n32.d: Add expected output for JALRC and NAL.
* gas/mips/r6-n64.d: Likewise.
* gas/mips/r6.d: Likewise.
---
gas/testsuite/gas/mips/r6-n32.d | 3 +++
gas/testsuite/gas/mips/r6-n64.d | 3 +++
gas/testsuite/gas/mips/r6.d | 3 +++
gas/testsuite/gas/mips/r6.s | 3 +++
opcodes/mips-opc.c | 3 ++-
5 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/gas/testsuite/gas/mips/r6-n32.d b/gas/testsuite/gas/mips/r6-n32.d
index 4df4f31..d4e9859 100644
--- a/gas/testsuite/gas/mips/r6-n32.d
+++ b/gas/testsuite/gas/mips/r6-n32.d
@@ -490,4 +490,7 @@ Disassembly of section .text:
0+057c <[^>]*> ec8bffff lwpc a0,00100578 <[^>]*>
0+0580 <[^>]*> 00000000 nop
0+0584 <[^>]*> ec83ffff lapc a0,00100580 <[^>]*>
+0+0588 <[^>]*> f8040000 jalrc a0
+0+058c <[^>]*> 04100000 nal
+0+0590 <[^>]*> 00000000 nop
\.\.\.
diff --git a/gas/testsuite/gas/mips/r6-n64.d b/gas/testsuite/gas/mips/r6-n64.d
index d099988..e388e7a 100644
--- a/gas/testsuite/gas/mips/r6-n64.d
+++ b/gas/testsuite/gas/mips/r6-n64.d
@@ -746,4 +746,7 @@ Disassembly of section .text:
0+057c <[^>]*> ec8bffff lwpc a0,0000000000100578 <[^>]*>
0+0580 <[^>]*> 00000000 nop
0+0584 <[^>]*> ec83ffff lapc a0,0000000000100580 <[^>]*>
+0+0588 <[^>]*> f8040000 jalrc a0
+0+058c <[^>]*> 04100000 nal
+0+0590 <[^>]*> 00000000 nop
\.\.\.
diff --git a/gas/testsuite/gas/mips/r6.d b/gas/testsuite/gas/mips/r6.d
index 0cfccb8..94ab611 100644
--- a/gas/testsuite/gas/mips/r6.d
+++ b/gas/testsuite/gas/mips/r6.d
@@ -489,4 +489,7 @@ Disassembly of section .text:
0+057c <[^>]*> ec8bffff lwpc a0,00100578 <[^>]*>
0+0580 <[^>]*> 00000000 nop
0+0584 <[^>]*> ec83ffff lapc a0,00100580 <[^>]*>
+0+0588 <[^>]*> f8040000 jalrc a0
+0+058c <[^>]*> 04100000 nal
+0+0590 <[^>]*> 00000000 nop
\.\.\.
diff --git a/gas/testsuite/gas/mips/r6.s b/gas/testsuite/gas/mips/r6.s
index 73308ad..e4ee083 100644
--- a/gas/testsuite/gas/mips/r6.s
+++ b/gas/testsuite/gas/mips/r6.s
@@ -258,6 +258,9 @@ new: maddf.s $f0,$f1,$f2
nop
addiu $4, $pc, (262143 << 2)
+ jalrc $4
+ nal
+
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
.space 8
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 6e0299e..c4f67ad 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -430,7 +430,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */
{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */
{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */
-{"nal", "p", 0x04100000, 0xffff0000, WR_31|CBD, INSN2_ALIAS, I1, 0, 0 },/* bltzal 0 */
+{"nal", "", 0x04100000, 0xffffffff, WR_31|CBD, INSN2_ALIAS, I1, 0, 0 },/* bltzal 0 */
{"bal", "p", 0x04110000, 0xffff0000, WR_31|UBD, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/
{"bc", "+'", 0xc8000000, 0xfc000000, NODS, 0, I37, 0, 0 },
{"balc", "+'", 0xe8000000, 0xfc000000, WR_31|NODS, 0, I37, 0, 0 },
@@ -3254,6 +3254,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"jic", "t,j", 0xd8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 },
{"bnezc", "-s,+\"", 0xf8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 },
+{"jalrc", "t", 0xf8000000, 0xffe0ffff, RD_1|NODS, 0, I37, 0, 0 },
{"jialc", "t,j", 0xf8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 },
{"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
--
1.9.4
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH, MIPS] Minor amendments to R6 opcode table
2014-12-16 14:41 [PATCH, MIPS] Minor amendments to R6 opcode table Matthew Fortune
@ 2014-12-16 20:49 ` Richard Sandiford
0 siblings, 0 replies; 2+ messages in thread
From: Richard Sandiford @ 2014-12-16 20:49 UTC (permalink / raw)
To: Matthew Fortune; +Cc: binutils
Matthew Fortune <Matthew.Fortune@imgtec.com> writes:
> opcodes/
>
> * mips-opc.c (mips_builtin_opcodes): Add JALRC alias for JIALC.
> Remove the operand from NAL.
>
> gas/testsuite/
>
> * gas/mips/r6.s: Test JALRC and NAL
> * gas/mips/r6-n32.d: Add expected output for JALRC and NAL.
> * gas/mips/r6-n64.d: Likewise.
> * gas/mips/r6.d: Likewise.
OK, thanks.
Richard
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2014-12-16 14:41 [PATCH, MIPS] Minor amendments to R6 opcode table Matthew Fortune
2014-12-16 20:49 ` Richard Sandiford
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