From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15649 invoked by alias); 20 May 2014 18:00:17 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 15634 invoked by uid 89); 20 May 2014 18:00:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f46.google.com Received: from mail-wg0-f46.google.com (HELO mail-wg0-f46.google.com) (74.125.82.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 20 May 2014 18:00:16 +0000 Received: by mail-wg0-f46.google.com with SMTP id n12so886898wgh.29 for ; Tue, 20 May 2014 11:00:12 -0700 (PDT) X-Received: by 10.180.160.205 with SMTP id xm13mr5617361wib.13.1400608812815; Tue, 20 May 2014 11:00:12 -0700 (PDT) Received: from localhost ([2.26.169.52]) by mx.google.com with ESMTPSA id o9sm19241437wjo.1.2014.05.20.11.00.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 May 2014 11:00:12 -0700 (PDT) From: Richard Sandiford To: Matthew Fortune Mail-Followup-To: Matthew Fortune ,"binutils\@sourceware.org" , Rich Fuhler , rdsandiford@googlemail.com Cc: "binutils\@sourceware.org" , Rich Fuhler Subject: Re: [PATCH][MIPS] Implement .module directive References: <6D39441BF12EF246A7ABCE6654B02353538578@LEMAIL01.le.imgtec.org> Date: Tue, 20 May 2014 18:00:00 -0000 In-Reply-To: <6D39441BF12EF246A7ABCE6654B02353538578@LEMAIL01.le.imgtec.org> (Matthew Fortune's message of "Tue, 20 May 2014 14:07:28 +0000") Message-ID: <87tx8kib4k.fsf@talisman.default> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2014-05/txt/msg00182.txt.bz2 Matthew Fortune writes: > + if (file_mips_opts.fp < 0) > + { > + /* No user specified float register size. > + ??? GAS treats single-float processors as though they had 64-bit > + float registers (although it complains when double-precision > + instructions are used). As things stand, saying they have 32-bit > + registers would lead to spurious "register must be even" messages. > + So here we assume float registers are never smaller than the > + integer ones. */ > + if (file_mips_opts.gp == 64) > + /* 64-bit integer registers implies 64-bit float registers. */ > + file_mips_opts.fp = 64; > + else if ((file_mips_opts.ase & FP64_ASES) > + && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) > + /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ > + file_mips_opts.fp = 64; I assume you'll update this for the other patch. Or we could just make the comment vaguer: Handle ASEs that imply 64-bit float registers. > + /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those > + ASEs from being selected implicitly. */ > + if (file_mips_opts.fp != 64) > + file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; Same here. > @@ -787,7 +787,7 @@ if { [istarget mips*-*-vxworks*] } { > run_dump_test "relax-swap1-mips2" > run_dump_test "relax-swap2" > run_dump_test_arches "relax-swap3" [mips_arch_list_all] > - run_list_test_arches "relax-bc1any" "-mips3d -relax-branch" \ > + run_list_test_arches "relax-bc1any" "-mips3d -64 -relax-branch" \ > [mips_arch_list_matching mips64 \ > !micromips] > run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \ Not all targets compile in support for n32 and n64, so -mabi=o64 would be better than -64. OK otherwise, thanks. Richard