[PATCH] Add MIPS ufr macro instruction

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* [PATCH] Add MIPS ufr macro instruction
@ 2013-11-08 14:04 Andrew Bennett
  2013-11-08 17:33 ` David Daney
  2013-11-09 11:27 ` Richard Sandiford
  0 siblings, 2 replies; 16+ messages in thread
From: Andrew Bennett @ 2013-11-08 14:04 UTC (permalink / raw)
  To: binutils; +Cc: rdsandiford

[-- Attachment #1: Type: text/plain, Size: 1241 bytes --]

Hi,

This patch adds the ufr macro instruction.  The instruction allows user mode to change the value of the FR mode bit.  I have added a macro into the gas MIPS backend that translates the ufr instruction to the appropriate ctc1 instruction.  The patch is attached, and the ChangeLog entry is below.

This is my first patch to binutils, so I am unsure the protocol on committing.  Would someone be able to clarify?

Many thanks,


Andrew


2013-11-08  Andrew Bennett  <andrew.bennett@imgtec.com>
	gas/config/
	* tc-mips.c (macro): Added support for ufr.

	gas/testsuite/gas/mips/
	* mips.exp: Added ufr test.
	* ufr.d: New.
	* ufr.s: New.

	include/opcode/
	* mips.h: Added M_UFR_I to the list of macros and updated the arg 
	field character information for MIPS and microMIPS.  

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Added support for the ?
	character.
	(micromips_opcodes): Added the ufr macro instruction.
	* opcodes/mips-opc.c (decode_mips_operand): Added support for the ?
	character.
	(mips_builtin_opcodes): Added the ufr macro instruction.


Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814
www.imgtec.com


[-- Attachment #2: ufr.patch --]
[-- Type: application/octet-stream, Size: 5717 bytes --]

From eee30f3886a4f43cc38dc5ebd3993e9a3559ea11 Mon Sep 17 00:00:00 2001
From: Andrew Bennett <andrew.bennett@imgtec.com>
Date: Thu, 7 Nov 2013 14:57:22 +0000
Subject: [PATCH 1/2] Added MIPS UFR macro.

---
 gas/config/tc-mips.c            |    3 +++
 gas/testsuite/gas/mips/mips.exp |    1 +
 gas/testsuite/gas/mips/ufr.d    |   10 ++++++++++
 gas/testsuite/gas/mips/ufr.s    |    6 ++++++
 include/opcode/mips.h           |    7 +++++--
 opcodes/micromips-opc.c         |    2 ++
 opcodes/mips-opc.c              |    2 ++
 7 files changed, 29 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/mips/ufr.d
 create mode 100644 gas/testsuite/gas/mips/ufr.s

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 08ad7ba..d109095 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -12510,6 +12510,9 @@ macro (struct mips_cl_insn *ip, char *str)
       end_noreorder ();
       break;
 
+    case M_UFR_I:
+      macro_build (NULL, "ctc1", "t,S", 0, op[0] == 0 ? 1 : 4);
+      break;
     case M_ULH_AB:
       s = "lb";
       s2 = "lbu";
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index d632c4f..401184c 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1152,4 +1152,5 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "msa64"	[mips_arch_list_matching mips64r2]
     run_dump_test_arches "msa-relax"	[mips_arch_list_matching mips32r2]
     run_dump_test_arches "msa-branch"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "ufr"		[mips_arch_list_matching mips32r2]
 }
diff --git a/gas/testsuite/gas/mips/ufr.d b/gas/testsuite/gas/mips/ufr.d
new file mode 100644
index 0000000..d4a2716
--- /dev/null
+++ b/gas/testsuite/gas/mips/ufr.d
@@ -0,0 +1,10 @@
+#objdump: -d --prefix-addresses
+#name: MIPS ufr
+
+# Test the ufr macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> ctc1	zero,\$1
+0+0004 <[^>]*> ctc1	zero,\$4
diff --git a/gas/testsuite/gas/mips/ufr.s b/gas/testsuite/gas/mips/ufr.s
new file mode 100644
index 0000000..236328b
--- /dev/null
+++ b/gas/testsuite/gas/mips/ufr.s
@@ -0,0 +1,6 @@
+# Source file used to test the ufr macro.
+
+	.text
+foo:
+	ufr 0
+	ufr 1
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index cb16d2a..f478742 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -799,6 +799,7 @@ struct mips_opcode
    "R" 5 bit fr source 3 register (OP_*_FR)
    "V" 5 bit same register used as floating source and destination (OP_*_FS)
    "W" 5 bit same register used as floating target and destination (OP_*_FT)
+   "?" 1 bit to represent the FR mode
 
    Coprocessor instructions:
    "E" 5 bit target register (OP_*_RT)
@@ -936,7 +937,7 @@ struct mips_opcode
 
    Characters used so far, for quick reference when adding more:
    "1234567890"
-   "%[]<>(),+:'@!#$*&\~"
+   "%[]<>(),+:'@!#$*&\~?"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
 
@@ -1558,6 +1559,7 @@ enum
   M_TNE_I,
   M_TRUNCWD,
   M_TRUNCWS,
+  M_UFR_I,
   M_ULD_AB,
   M_ULH_AB,
   M_ULHU_AB,
@@ -2057,6 +2059,7 @@ extern const int bfd_mips16_num_opcodes;
    "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
    "V" 5-bit same register used as floating source and destination or target
        (MICROMIPSOP_*_FS)
+   "?" 1 bit to represent the FR mode
 
    Coprocessor instructions:
    "E" 5-bit target register (MICROMIPSOP_*_RT)
@@ -2121,7 +2124,7 @@ extern const int bfd_mips16_num_opcodes;
 
    Characters used so far, for quick reference when adding more:
    "12345678 0"
-   "<>(),+.@\^|~"
+   "<>(),+.@\^|~?"
    "ABCDEFGHI KLMN   RST V    "
    "abcd f hijklmnopqrstuvw yz"
 
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 390b243..b94c9b3 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -147,6 +147,7 @@ decode_micromips_operand (const char *p)
     case '~': SINT (12, 0);
     case '@': SINT (10, 16);
     case '^': HINT (5, 11);
+    case '?': UINT (1, 0);
 
     case '0': SINT (6, 16);
     case '1': HINT (5, 16);
@@ -1114,6 +1115,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"trunc.l.s",		"T,S",		0x5400233b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
 {"trunc.w.d",		"T,S",		0x54006b3b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
 {"trunc.w.s",		"T,S",		0x54002b3b, 0xfc00ffff,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
+{"ufr",			"?",		0,    (int) M_UFR_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"uld",			"t,A(b)",	0,    (int) M_ULD_AB,	INSN_MACRO,		0,		I3,		0,	0 },
 {"ulh",			"t,A(b)",	0,    (int) M_ULH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"ulhu",		"t,A(b)",	0,    (int) M_ULHU_AB,	INSN_MACRO,		0,		I1,		0,	0 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 4f72931..b0a8c6a 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -130,6 +130,7 @@ decode_mips_operand (const char *p)
     case '&': REG (2, 13, ACC);
     case '~': SINT (12, 0);
     case '\\': BIT (3, 12, 0);			/* (0 .. 7) */
+    case '?': UINT (1, 0);
 
     case '0': SINT (6, 20);
     case '1': HINT (5, 6);
@@ -1922,6 +1923,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"trunc.w.s",		"D,S",		0x4600000d, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"trunc.w.s",		"D,S,x",	0x4600000d, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"trunc.w.s",		"D,S,t",	0,    (int) M_TRUNCWS,	INSN_MACRO,		INSN2_M_FP_S,	I1,		0,	EE },
+{"ufr",			"?",		0,    (int) M_UFR_I,	INSN_MACRO,		0,		I33,		0,	0 },
 {"uld",			"t,A(b)",	0,    (int) M_ULD_AB,	INSN_MACRO,		0,		I3,		0,	0 },
 {"ulh",			"t,A(b)",	0,    (int) M_ULH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"ulhu",		"t,A(b)",	0,    (int) M_ULHU_AB,	INSN_MACRO,		0,		I1,		0,	0 },
-- 
1.7.10.1


^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-11-08 14:04 [PATCH] Add MIPS ufr macro instruction Andrew Bennett
@ 2013-11-08 17:33 ` David Daney
  2013-11-09 11:27 ` Richard Sandiford
  1 sibling, 0 replies; 16+ messages in thread
From: David Daney @ 2013-11-08 17:33 UTC (permalink / raw)
  To: Andrew Bennett; +Cc: binutils, rdsandiford

On 11/08/2013 06:03 AM, Andrew Bennett wrote:
> Hi,
>
> This patch adds the ufr macro instruction.  The instruction allows user mode to change the value of the FR mode bit.  I have added a macro into the gas MIPS backend that translates the ufr instruction to the appropriate ctc1 instruction.  The patch is attached, and the ChangeLog entry is below.
>

Can you explain why we need another magic code generation macro?

Why can't you just emit the real instructions to the .s file instead?


David Daney



> This is my first patch to binutils, so I am unsure the protocol on committing.  Would someone be able to clarify?
>
> Many thanks,
>
>
> Andrew
>
>
> 2013-11-08  Andrew Bennett  <andrew.bennett@imgtec.com>
> 	gas/config/
> 	* tc-mips.c (macro): Added support for ufr.
>
> 	gas/testsuite/gas/mips/
> 	* mips.exp: Added ufr test.
> 	* ufr.d: New.
> 	* ufr.s: New.
>
> 	include/opcode/
> 	* mips.h: Added M_UFR_I to the list of macros and updated the arg
> 	field character information for MIPS and microMIPS.
>
> 	opcodes/
> 	* micromips-opc.c (decode_micromips_operand): Added support for the ?
> 	character.
> 	(micromips_opcodes): Added the ufr macro instruction.
> 	* opcodes/mips-opc.c (decode_mips_operand): Added support for the ?
> 	character.
> 	(mips_builtin_opcodes): Added the ufr macro instruction.
>
>
> Andrew Bennett
> Software Design Engineer, MIPS Processor IP
> Imagination Technologies Limited
> t: +44 (0)113 2429814
> www.imgtec.com
>

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-11-08 14:04 [PATCH] Add MIPS ufr macro instruction Andrew Bennett
  2013-11-08 17:33 ` David Daney
@ 2013-11-09 11:27 ` Richard Sandiford
  2013-11-14  9:12   ` Richard Sandiford
  1 sibling, 1 reply; 16+ messages in thread
From: Richard Sandiford @ 2013-11-09 11:27 UTC (permalink / raw)
  To: Andrew Bennett; +Cc: binutils

Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> This patch adds the ufr macro instruction.  The instruction allows user
> mode to change the value of the FR mode bit.  I have added a macro into
> the gas MIPS backend that translates the ufr instruction to the
> appropriate ctc1 instruction.  The patch is attached, and the ChangeLog
> entry is below.

The patch looks good, thanks.  I personally don't mind adding macros
like these, but let's see where the thread with David goes.

> This is my first patch to binutils, so I am unsure the protocol on
> committing.  Would someone be able to clarify?

If you're going to be submitting other patches then please feel free
to apply for access: https://sourceware.org/cgi-bin/pdw/ps_form.cgi
Otherwise Steve or I could commit it.

Thanks,
Richard

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-11-09 11:27 ` Richard Sandiford
@ 2013-11-14  9:12   ` Richard Sandiford
  2013-11-14 12:42     ` Andrew Bennett
  0 siblings, 1 reply; 16+ messages in thread
From: Richard Sandiford @ 2013-11-14  9:12 UTC (permalink / raw)
  To: Andrew Bennett; +Cc: binutils

Richard Sandiford <rdsandiford@googlemail.com> writes:
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>> This patch adds the ufr macro instruction.  The instruction allows user
>> mode to change the value of the FR mode bit.  I have added a macro into
>> the gas MIPS backend that translates the ufr instruction to the
>> appropriate ctc1 instruction.  The patch is attached, and the ChangeLog
>> entry is below.
>
> The patch looks good, thanks.  I personally don't mind adding macros
> like these, but let's see where the thread with David goes.

Seems like this might have hit a log-jam, so just in case, what I really
meant was: please answer David's question first.

Thanks,
Richard

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH] Add MIPS ufr macro instruction
  2013-11-14  9:12   ` Richard Sandiford
@ 2013-11-14 12:42     ` Andrew Bennett
  2013-11-20 16:14       ` Andrew Bennett
  0 siblings, 1 reply; 16+ messages in thread
From: Andrew Bennett @ 2013-11-14 12:42 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: binutils

> Seems like this might have hit a log-jam, so just in case, what I really
> meant was: please answer David's question first.

Hi Richard,

Sorry for the delay in the replying I have been thinking about David's comments.
David, I agree with you, having ufr as an actual instruction, rather than a macro 
would make it much clearer to see it's use when disassembling a program.

I am currently changing the patch to reflect these changes, and will post it back
in the next few days.

Regards,

Andrew

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH] Add MIPS ufr macro instruction
  2013-11-14 12:42     ` Andrew Bennett
@ 2013-11-20 16:14       ` Andrew Bennett
  2013-11-24 18:32         ` Richard Sandiford
  0 siblings, 1 reply; 16+ messages in thread
From: Andrew Bennett @ 2013-11-20 16:14 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: binutils

>> Seems like this might have hit a log-jam, so just in case, what I really
>> meant was: please answer David's question first.

> Hi Richard,

> Sorry for the delay in the replying I have been thinking about David's comments.
> David, I agree with you, having ufr as an actual instruction, rather than a macro 
> would make it much clearer to see it's use when disassembling a program.

> I am currently changing the patch to reflect these changes, and will post it back
> in the next few days.

The updated patch and ChangeLog entry is below. 

Regards,


Andrew
 

2013-11-20  Andrew Bennett  <andrew.bennett@imgtec.com>
	gas/config/
	* tc-mips.c (operand_reg_mask): Add OP_UFR_INT case.
	(match_operand): Likewise.
	(match_ufr_operand): New function.

	gas/testsuite/gas/mips/
	* mips.exp: Added ufr test.
	* ufr.d: New test.
	* ufr.s: New test.

	include/opcode/
	* mips.h: Updated the arg field character information for MIPS and 
	microMIPS.  
	(mips_operand_type): Add OP_UFR_INT.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Added support for the ?
	character.
	(micromips_opcodes): Added the ufr instruction.
	* opcodes/mips-opc.c (decode_mips_operand): Added support for the ?
	character.
	(mips_builtin_opcodes): Added the ufr instruction.
	* opcodes/mips-dis.c (print_insn_arg): Add OP_UFR_INT case.
	(print_insn_mips): Don't try to disassemble ufr instruction 
	if the coprocessor register number is not 1 or 4.
	(print_insn_micromips): Likewise.



---
 gas/config/tc-mips.c            |   39 ++++++++++++++++++++++++++++++++++++
 gas/testsuite/gas/mips/mips.exp |    1 +
 gas/testsuite/gas/mips/ufr.d    |   42 +++++++++++++++++++++++++++++++++++++++
 gas/testsuite/gas/mips/ufr.s    |   38 +++++++++++++++++++++++++++++++++++
 include/opcode/mips.h           |   16 ++++++++++++---
 opcodes/micromips-opc.c         |    2 ++
 opcodes/mips-dis.c              |   30 ++++++++++++++++++++++++++++
 opcodes/mips-opc.c              |    2 ++
 8 files changed, 167 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/mips/ufr.d
 create mode 100644 gas/testsuite/gas/mips/ufr.s

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 34f1bf0..dab2889 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -4031,6 +4031,18 @@ operand_reg_mask (const struct mips_cl_insn *insn,
     case OP_IMM_INDEX:
       abort ();
 
+    case OP_UFR_INT:
+      {
+        if ((type_mask & (1 << OP_REG_GP)))
+          /* ufr implicitly uses the zero reg */
+          return 1;
+        else if ((type_mask & (1 << OP_REG_COPRO)))
+          /* ufr only works with control regs 1 and 4 */
+          return (1 << 1) | (1 << 4);
+        else
+          return 0;
+      }
+
     case OP_REG:
     case OP_OPTIONAL_REG:
       {
@@ -4796,6 +4808,30 @@ match_perf_reg_operand (struct mips_arg_info *arg,
   return TRUE;
 }
 
+/* OP_UFR matcher.  */
+
+static bfd_boolean
+match_ufr_operand (struct mips_arg_info *arg,
+                   const struct mips_operand *operand)
+{
+  offsetT sval;
+
+  if (!match_const_int (arg, &sval))
+    return FALSE;
+
+  switch (sval)
+    {
+    case 0:
+      insn_insert_operand (arg->insn, operand, 1);
+      return TRUE;
+    case 1:
+      insn_insert_operand (arg->insn, operand, 4);
+      return TRUE;
+    default:
+      match_out_of_range (arg);
+      return FALSE;
+    }
+}
 /* OP_ADDIUSP matcher.  */
 
 static bfd_boolean
@@ -5470,6 +5506,9 @@ match_operand (struct mips_arg_info *arg,
     case OP_PERF_REG:
       return match_perf_reg_operand (arg, operand);
 
+    case OP_UFR_INT:
+      return match_ufr_operand (arg, operand);
+
     case OP_ADDIUSP_INT:
       return match_addiusp_operand (arg, operand);
 
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 121566a..68514c5 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1156,4 +1156,5 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "msa64"	[mips_arch_list_matching mips64r2]
     run_dump_test_arches "msa-relax"	[mips_arch_list_matching mips32r2]
     run_dump_test_arches "msa-branch"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "ufr"		[mips_arch_list_matching mips32r2]
 }
diff --git a/gas/testsuite/gas/mips/ufr.d b/gas/testsuite/gas/mips/ufr.d
new file mode 100644
index 0000000..4fc1421
--- /dev/null
+++ b/gas/testsuite/gas/mips/ufr.d
@@ -0,0 +1,42 @@
+#objdump: -d --prefix-addresses
+#name: MIPS ufr
+
+# Test the ufr instruction.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> ufr	0
+0+0004 <[^>]*> ufr	1
+0+0008 <[^>]*> ctc1	zero,\$0
+0+000c <[^>]*> ufr	0
+0+0010 <[^>]*> ctc1	zero,\$2
+0+0014 <[^>]*> ctc1	zero,\$3
+0+0018 <[^>]*> ufr	1
+0+001c <[^>]*> ctc1	zero,\$5
+0+0020 <[^>]*> ctc1	zero,\$6
+0+0024 <[^>]*> ctc1	zero,\$7
+0+0028 <[^>]*> ctc1	zero,\$8
+0+002c <[^>]*> ctc1	zero,\$9
+0+0030 <[^>]*> ctc1	zero,\$10
+0+0034 <[^>]*> ctc1	zero,\$11
+0+0038 <[^>]*> ctc1	zero,\$12
+0+003c <[^>]*> ctc1	zero,\$13
+0+0040 <[^>]*> ctc1	zero,\$14
+0+0044 <[^>]*> ctc1	zero,\$15
+0+0048 <[^>]*> ctc1	zero,\$16
+0+004c <[^>]*> ctc1	zero,\$17
+0+0050 <[^>]*> ctc1	zero,\$18
+0+0054 <[^>]*> ctc1	zero,\$19
+0+0058 <[^>]*> ctc1	zero,\$20
+0+005c <[^>]*> ctc1	zero,\$21
+0+0060 <[^>]*> ctc1	zero,\$22
+0+0064 <[^>]*> ctc1	zero,\$23
+0+0068 <[^>]*> ctc1	zero,\$24
+0+006c <[^>]*> ctc1	zero,\$25
+0+0070 <[^>]*> ctc1	zero,\$26
+0+0074 <[^>]*> ctc1	zero,\$27
+0+0078 <[^>]*> ctc1	zero,\$28
+0+007c <[^>]*> ctc1	zero,\$29
+0+0080 <[^>]*> ctc1	zero,\$30
+0+0084 <[^>]*> ctc1	zero,\$31
diff --git a/gas/testsuite/gas/mips/ufr.s b/gas/testsuite/gas/mips/ufr.s
new file mode 100644
index 0000000..433e3f6
--- /dev/null
+++ b/gas/testsuite/gas/mips/ufr.s
@@ -0,0 +1,38 @@
+# Source file used to test the ufr instruction.
+
+       .text
+foo:
+       ufr 0
+       ufr 1
+       ctc1 $0,$f0
+       ctc1 $0,$f1
+       ctc1 $0,$f2
+       ctc1 $0,$f3
+       ctc1 $0,$f4
+       ctc1 $0,$f5
+       ctc1 $0,$f6
+       ctc1 $0,$f7
+       ctc1 $0,$f8
+       ctc1 $0,$f9
+       ctc1 $0,$f10
+       ctc1 $0,$f11
+       ctc1 $0,$f12
+       ctc1 $0,$f13
+       ctc1 $0,$f14
+       ctc1 $0,$f15
+       ctc1 $0,$f16
+       ctc1 $0,$f17
+       ctc1 $0,$f18
+       ctc1 $0,$f19
+       ctc1 $0,$f20
+       ctc1 $0,$f21
+       ctc1 $0,$f22
+       ctc1 $0,$f23
+       ctc1 $0,$f24
+       ctc1 $0,$f25
+       ctc1 $0,$f26
+       ctc1 $0,$f27
+       ctc1 $0,$f28
+       ctc1 $0,$f29
+       ctc1 $0,$f30
+       ctc1 $0,$f31
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index c9dc52b..80e85c7 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -419,7 +419,13 @@ enum mips_operand_type {
   OP_IMM_INDEX,
 
   /* An index selected by a register, e.g. [$2].  */
-  OP_REG_INDEX
+  OP_REG_INDEX,
+
+  /* An operand to the ufr instruction.  The only values that are allowed are 0 and 1.
+     They are mapped in the following manner:
+     0 => 1
+     1 => 4 */
+  OP_UFR_INT
 };
 
 /* Enumerates the types of MIPS register.  */
@@ -807,6 +813,8 @@ struct mips_opcode
    "P" 5 bit performance-monitor register (OP_*_PERFREG)
    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
+   "?" 5 bit destination register.  It is used to set the FR mode, only
+       allowed values are 1 (FR = 0) and 4 (FR = 1).
 
    Macro instructions:
    "A" General 32 bit expression
@@ -936,7 +944,7 @@ struct mips_opcode
 
    Characters used so far, for quick reference when adding more:
    "1234567890"
-   "%[]<>(),+:'@!#$*&\~"
+   "%[]<>(),+:'@!#$*&\~?"
    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
    "abcdefghijklopqrstuvwxz"
 
@@ -2062,6 +2070,8 @@ extern const int bfd_mips16_num_opcodes;
    "E" 5-bit target register (MICROMIPSOP_*_RT)
    "G" 5-bit source register (MICROMIPSOP_*_RS)
    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+   "?" 5 bit target register.  It is used to set the FR mode, only
+       allowed values are 1 (FR = 0) and 4 (FR = 1).
 
    Macro instructions:
    "A" general 32 bit expression
@@ -2121,7 +2131,7 @@ extern const int bfd_mips16_num_opcodes;
 
    Characters used so far, for quick reference when adding more:
    "12345678 0"
-   "<>(),+.@\^|~"
+   "<>(),+.@\^|~?"
    "ABCDEFGHI KLMN   RST V    "
    "abcd f hijklmnopqrstuvw yz"
 
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index a68916a..702e6c7 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -147,6 +147,7 @@ decode_micromips_operand (const char *p)
     case '~': SINT (12, 0);
     case '@': SINT (10, 16);
     case '^': HINT (5, 11);
+    case '?': SPECIAL (5, 16, UFR_INT);
 
     case '0': SINT (6, 16);
     case '1': HINT (5, 16);
@@ -546,6 +547,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"clo",			"t,s",		0x00004b3c, 0xfc00ffff,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"clz",			"t,s",		0x00005b3c, 0xfc00ffff,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"cop2",		"C",		0x00000002, 0xfc000007,	CP,			0,		I1,		0,	0 },
+{"ufr",			"?",		0x5400183b, 0xffe0ffff,	RD_1|WR_CC|FP_S,	0,		I1,		0,	0 },
 {"ctc1",		"t,G",		0x5400183b, 0xfc00ffff,	RD_1|WR_CC|FP_S,	0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x5400183b, 0xfc00ffff,	RD_1|WR_CC|FP_S,	0,		I1,		0,	0 },
 {"ctc2",		"t,G",		0x0000dd3c, 0xfc00ffff,	RD_1|WR_C2|WR_CC,	0,		I1,		0,	0 },
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1929ffc..a903b4e 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1114,6 +1114,22 @@ print_insn_arg (struct disassemble_info *info,
       infprintf (is, "%d", uval);
       break;
 
+    case OP_UFR_INT:
+      {
+        switch (uval)
+          {
+          case 1:
+            infprintf (is, "0");
+            break;
+          case 4:
+            infprintf (is, "1");
+            break;
+          default:
+            abort ();
+          }
+        break;
+      }
+
     case OP_ADDIUSP_INT:
       {
 	int sval;
@@ -1427,6 +1443,13 @@ print_insn_mips (bfd_vma memaddr,
 	      && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
 	      && (word & op->mask) == op->match)
 	    {
+	      if (strcmp (op->name, "ufr") == 0)
+                {
+                  unsigned int val = (word >> 11) & 0x1F;
+                  if (val != 1 && val != 4)
+                    continue;
+                }
+
 	      /* We always allow to disassemble the jalx instruction.  */
 	      if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
 		  && strcmp (op->name, "jalx"))
@@ -1974,6 +1997,13 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
 	  && ((length == 2 && (op->mask & 0xffff0000) == 0)
 	      || (length == 4 && (op->mask & 0xffff0000) != 0)))
 	{
+	  if (strcmp (op->name, "ufr") == 0)
+            {
+              unsigned int val = (insn >> 16) & 0x1F;
+              if (val != 1 && val != 4)
+                continue;
+            }
+
 	  infprintf (is, "%s", op->name);
 
 	  if (op->args[0])
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index cd43185..9f13702 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -130,6 +130,7 @@ decode_mips_operand (const char *p)
     case '&': REG (2, 13, ACC);
     case '~': SINT (12, 0);
     case '\\': BIT (3, 12, 0);			/* (0 .. 7) */
+    case '?': SPECIAL (5, 11, UFR_INT);
 
     case '0': SINT (6, 20);
     case '1': HINT (5, 6);
@@ -911,6 +912,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
 {"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2, 	0,		I32|N55,	0,	0 },
 {"ctc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_CC|COD,		0,		I1,		0,	IOCT|IOCTP|IOCT2 },
+{"ufr",			"?",		0x44c00000, 0xffff07ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
 {"ctc1",		"t,G",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
 {"ctc1",		"t,S",		0x44c00000, 0xffe007ff,	RD_1|WR_CC|COD|FP_S,	0,		I1,		0,	0 },
 /* ctc2 is at the bottom of the table.  */
-- 
1.7.10.1


^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-11-20 16:14       ` Andrew Bennett
@ 2013-11-24 18:32         ` Richard Sandiford
  2013-11-25  8:40           ` Maciej W. Rozycki
  0 siblings, 1 reply; 16+ messages in thread
From: Richard Sandiford @ 2013-11-24 18:32 UTC (permalink / raw)
  To: Andrew Bennett; +Cc: binutils

Hi Andrew,

Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>>> Seems like this might have hit a log-jam, so just in case, what I really
>>> meant was: please answer David's question first.
>
>> Hi Richard,
>
>> Sorry for the delay in the replying I have been thinking about David's
>> comments.
>> David, I agree with you, having ufr as an actual instruction, rather
>> than a macro
>> would make it much clearer to see it's use when disassembling a program.
>
>> I am currently changing the patch to reflect these changes, and will
>> post it back
>> in the next few days.
>
> The updated patch and ChangeLog entry is below. 

Sorry to mess you around, but I thought David was objecting more to the
macro existing at all.  I could be wrong though.

The problem with using ufr for disassembly is that AFAICT it isn't
mentioned in the manuals.  People disassembling pass-me-downs might
struggle to know what it means.  Maybe the ideal would be to disassemble
the CTC1 normally and add a comment "; ufr [01]" next to it.  But that's
probably make-work.

So TBH I preferred your original patch.

There haven't been any more objections, so if you're still OK with the
original version, I suggest we go with that.  I can apply it for you if so.

Thanks,
Richard

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-11-24 18:32         ` Richard Sandiford
@ 2013-11-25  8:40           ` Maciej W. Rozycki
  2013-12-09 15:38             ` Andrew Bennett
  0 siblings, 1 reply; 16+ messages in thread
From: Maciej W. Rozycki @ 2013-11-25  8:40 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: Andrew Bennett, binutils

On Sun, 24 Nov 2013, Richard Sandiford wrote:

> The problem with using ufr for disassembly is that AFAICT it isn't
> mentioned in the manuals.  People disassembling pass-me-downs might
> struggle to know what it means.  Maybe the ideal would be to disassemble
> the CTC1 normally and add a comment "; ufr [01]" next to it.  But that's
> probably make-work.
> 
> So TBH I preferred your original patch.
> 
> There haven't been any more objections, so if you're still OK with the
> original version, I suggest we go with that.  I can apply it for you if so.

 Apologies for late coming, I missed this thread.  I object.  I think it 
would make more sense if we followed the practice already established with 
CP0 register names and instead defined cooked names for CP1 control 
registers as well.  E.g.:

	ctc1	$0, $c1_ufr
	ctc1	$0, $c1_unfr
	cfc1	$2, $c1_ufr

or suchlike.  I think it would be more obvious, user friendly (including 
disassembly) and consistent.  If we wanted $0 implied for cases where 
applicable we could define single-argument aliases, e.g.:

	ctc1	$c1_ufr
	ctc1	$c1_unfr

preferably as macros as far as I'm concerned (although I'm not too
enthusiastic about such aliases in the first place).

 Of course we'd add the rest at the same time too, i.e. $c1_fir, $c1_fcsr, 
etc.

 Thoughts?

  Maciej

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH] Add MIPS ufr macro instruction
  2013-11-25  8:40           ` Maciej W. Rozycki
@ 2013-12-09 15:38             ` Andrew Bennett
  2013-12-10 12:38               ` Richard Sandiford
  0 siblings, 1 reply; 16+ messages in thread
From: Andrew Bennett @ 2013-12-09 15:38 UTC (permalink / raw)
  To: Maciej W. Rozycki, Richard Sandiford; +Cc: binutils

> On Sun, 24 Nov 2013, Richard Sandiford wrote:
> 
> > The problem with using ufr for disassembly is that AFAICT it isn't
> > mentioned in the manuals.  People disassembling pass-me-downs might
> > struggle to know what it means.  Maybe the ideal would be to disassemble
> > the CTC1 normally and add a comment "; ufr [01]" next to it.  But that's
> > probably make-work.
> > 
> > So TBH I preferred your original patch.
> > 
> > There haven't been any more objections, so if you're still OK with the
> > original version, I suggest we go with that.  I can apply it for you if so.
> 
>  Apologies for late coming, I missed this thread.  I object.  I think it 
> would make more sense if we followed the practice already established with 
> CP0 register names and instead defined cooked names for CP1 control 
> registers as well.  E.g.:
> 
> 	ctc1	$0, $c1_ufr
> 	ctc1	$0, $c1_unfr
> 	cfc1	$2, $c1_ufr
> 
> or suchlike.  I think it would be more obvious, user friendly (including 
> disassembly) and consistent.  If we wanted $0 implied for cases where 
> applicable we could define single-argument aliases, e.g.:
> 
> 	ctc1	$c1_ufr
> 	ctc1	$c1_unfr
> 
> preferably as macros as far as I'm concerned (although I'm not too
> enthusiastic about such aliases in the first place).
> 
>  Of course we'd add the rest at the same time too, i.e. $c1_fir, $c1_fcsr, 
> etc.
> 
>  Thoughts?

I like this solution.  Firstly, it makes it much easier to see what the c[ft]c1
instruction is actually doing when either assembling or disassembling.  Secondly, 
it is clear when a ufr instruction is being used, so I don't think it requires the 
need to have an explicit ufr macro.

If everyone is happy with this I will rework the patch, and post it back on to
the list.


Regards,



Andrew


Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814
www.imgtec.com

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-12-09 15:38             ` Andrew Bennett
@ 2013-12-10 12:38               ` Richard Sandiford
  2013-12-11 12:20                 ` Andrew Bennett
  0 siblings, 1 reply; 16+ messages in thread
From: Richard Sandiford @ 2013-12-10 12:38 UTC (permalink / raw)
  To: Andrew Bennett; +Cc: Maciej W. Rozycki, binutils

Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>> On Sun, 24 Nov 2013, Richard Sandiford wrote:
>> 
>> > The problem with using ufr for disassembly is that AFAICT it isn't
>> > mentioned in the manuals.  People disassembling pass-me-downs might
>> > struggle to know what it means.  Maybe the ideal would be to disassemble
>> > the CTC1 normally and add a comment "; ufr [01]" next to it.  But that's
>> > probably make-work.
>> > 
>> > So TBH I preferred your original patch.
>> > 
>> > There haven't been any more objections, so if you're still OK with the
>> > original version, I suggest we go with that.  I can apply it for you if so.
>> 
>>  Apologies for late coming, I missed this thread.  I object.  I think it 
>> would make more sense if we followed the practice already established with 
>> CP0 register names and instead defined cooked names for CP1 control 
>> registers as well.  E.g.:
>> 
>> 	ctc1	$0, $c1_ufr
>> 	ctc1	$0, $c1_unfr
>> 	cfc1	$2, $c1_ufr
>> 
>> or suchlike.  I think it would be more obvious, user friendly (including 
>> disassembly) and consistent.  If we wanted $0 implied for cases where 
>> applicable we could define single-argument aliases, e.g.:
>> 
>> 	ctc1	$c1_ufr
>> 	ctc1	$c1_unfr
>> 
>> preferably as macros as far as I'm concerned (although I'm not too
>> enthusiastic about such aliases in the first place).
>> 
>>  Of course we'd add the rest at the same time too, i.e. $c1_fir, $c1_fcsr, 
>> etc.
>> 
>>  Thoughts?
>
> I like this solution.  Firstly, it makes it much easier to see what the c[ft]c1
> instruction is actually doing when either assembling or disassembling.
> Secondly,
> it is clear when a ufr instruction is being used, so I don't think it
> requires the
> need to have an explicit ufr macro.
>
> If everyone is happy with this I will rework the patch, and post it back on to
> the list.

Thanks, soounds good to me too.

Richard

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH] Add MIPS ufr macro instruction
  2013-12-10 12:38               ` Richard Sandiford
@ 2013-12-11 12:20                 ` Andrew Bennett
  2013-12-13 16:39                   ` Richard Sandiford
  0 siblings, 1 reply; 16+ messages in thread
From: Andrew Bennett @ 2013-12-11 12:20 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: Maciej W. Rozycki, binutils

> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>>> On Sun, 24 Nov 2013, Richard Sandiford wrote:
>>> 
>>> > The problem with using ufr for disassembly is that AFAICT it isn't
>>> > mentioned in the manuals.  People disassembling pass-me-downs might
>>> > struggle to know what it means.  Maybe the ideal would be to disassemble
>>> > the CTC1 normally and add a comment "; ufr [01]" next to it.  But that's
>>> > probably make-work.
>>> > 
>>> > So TBH I preferred your original patch.
>>> > 
>>> > There haven't been any more objections, so if you're still OK with the
>>> > original version, I suggest we go with that.  I can apply it for you if so.
>>> 
>>>  Apologies for late coming, I missed this thread.  I object.  I think it 
>>> would make more sense if we followed the practice already established with 
>>> CP0 register names and instead defined cooked names for CP1 control 
>>> registers as well.  E.g.:
>>> 
>>> 	ctc1	$0, $c1_ufr
>>> 	ctc1	$0, $c1_unfr
>>> 	cfc1	$2, $c1_ufr
>>> 
>>> or suchlike.  I think it would be more obvious, user friendly (including 
>>> disassembly) and consistent.  If we wanted $0 implied for cases where 
>>> applicable we could define single-argument aliases, e.g.:
>>> 
>>> 	ctc1	$c1_ufr
>>> 	ctc1	$c1_unfr
>>> 
>>> preferably as macros as far as I'm concerned (although I'm not too
>>> enthusiastic about such aliases in the first place).
>>> 
>>>  Of course we'd add the rest at the same time too, i.e. $c1_fir, $c1_fcsr, 
>>> etc.
>>> 
>>>  Thoughts?
>>
>> I like this solution.  Firstly, it makes it much easier to see what the c[ft]c1
>> instruction is actually doing when either assembling or disassembling.
>> Secondly,
>> it is clear when a ufr instruction is being used, so I don't think it
>> requires the
>> need to have an explicit ufr macro.
>>
>> If everyone is happy with this I will rework the patch, and post it back on to
>> the list.
>
> Thanks, soounds good to me too.

The new patch and ChangeLog entry is shown below.

Regards,


Andrew


2013-12-10  Andrew Bennett  <andrew.bennett@imgtec.com>
	gas/testsuite/gas/mips/
	* mips.exp: Add cp1 register name tests.
	* cp1-names-mips32.d: New test.
	* cp1-names-mips32r2.d: New test.
	* cp1-names-mips64.d: New test.
	* cp1-names-mips64r2.d: New test.
	* cp1-names-numeric.d: New test.
	* cp1-names-r3000.d: New test.
	* cp1-names-r4000.d: New test.
	* cp1-names-sb1.d: New test.
	* cp1-names.s: New test.
	* micromips-insn32.d: Add the correct symbolic names for the CP1
	registers.
	* micromips-noinsn32.d: Likewise.
	* micromips-trap.d: Likewise.
	* micromips.d: Likewise

	opcodes/
	* mips-dis.c: Add mips_cp1_names pointer.
	(mips_cp1_names_numeric): New array.
	(mips_cp1_names_mips3264): New array.
	(mips_arch_choice): Add cp1_names.
	(mips_arch_choices): Add relevant cp1 register name array to each of 
	the elements.
	(set_default_mips_dis_options): Add support for setting up the 
	mips_cp1_names pointer.
	(parse_mips_dis_option): Add support for the cp1-names command line
	variable.  Also setup the mips_cp1_names pointer.
	(print_reg): Print out name of the cp1 register.



---
 gas/testsuite/gas/mips/cp1-names-mips32.d   |   74 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-mips32r2.d |   74 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-mips64.d   |   74 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-mips64r2.d |   74 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-numeric.d  |   74 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-r3000.d    |   75 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-r4000.d    |   75 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names-sb1.d      |   74 ++++++++++++++
 gas/testsuite/gas/mips/cp1-names.s          |   77 +++++++++++++++
 gas/testsuite/gas/mips/micromips-insn32.d   |   84 ++++++++--------
 gas/testsuite/gas/mips/micromips-noinsn32.d |   84 ++++++++--------
 gas/testsuite/gas/mips/micromips-trap.d     |   84 ++++++++--------
 gas/testsuite/gas/mips/micromips.d          |   84 ++++++++--------
 gas/testsuite/gas/mips/mips.exp             |   12 +++
 opcodes/mips-dis.c                          |  140 +++++++++++++++++++--------
 15 files changed, 952 insertions(+), 207 deletions(-)
 create mode 100644 gas/testsuite/gas/mips/cp1-names-mips32.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-mips32r2.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-mips64.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-mips64r2.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-numeric.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-r3000.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-r4000.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names-sb1.d
 create mode 100644 gas/testsuite/gas/mips/cp1-names.s

diff --git a/gas/testsuite/gas/mips/cp1-names-mips32.d b/gas/testsuite/gas/mips/cp1-names-mips32.d
new file mode 100644
index 0000000..93d3253
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-mips32.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips32
+#name: MIPS CP1 register disassembly (mips32)
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,c1_fir
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,c1_ufr
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,c1_unfr
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,c1_fccr
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,c1_fexr
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,c1_fenr
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,c1_fcsr
+0+0080 <[^>]*> 44400000 	cfc1	\$0,c1_fir
+0+0084 <[^>]*> 44400800 	cfc1	\$0,c1_ufr
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,c1_unfr
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,c1_fccr
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,c1_fexr
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,c1_fenr
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,c1_fcsr
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-mips32r2.d b/gas/testsuite/gas/mips/cp1-names-mips32r2.d
new file mode 100644
index 0000000..03d6a19
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-mips32r2.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips32r2
+#name: MIPS CP1 register disassembly (mips32r2)
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,c1_fir
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,c1_ufr
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,c1_unfr
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,c1_fccr
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,c1_fexr
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,c1_fenr
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,c1_fcsr
+0+0080 <[^>]*> 44400000 	cfc1	\$0,c1_fir
+0+0084 <[^>]*> 44400800 	cfc1	\$0,c1_ufr
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,c1_unfr
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,c1_fccr
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,c1_fexr
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,c1_fenr
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,c1_fcsr
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-mips64.d b/gas/testsuite/gas/mips/cp1-names-mips64.d
new file mode 100644
index 0000000..a7afaf1
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-mips64.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips64
+#name: MIPS CP1 register disassembly (mips64)
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,c1_fir
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,c1_ufr
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,c1_unfr
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,c1_fccr
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,c1_fexr
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,c1_fenr
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,c1_fcsr
+0+0080 <[^>]*> 44400000 	cfc1	\$0,c1_fir
+0+0084 <[^>]*> 44400800 	cfc1	\$0,c1_ufr
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,c1_unfr
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,c1_fccr
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,c1_fexr
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,c1_fenr
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,c1_fcsr
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-mips64r2.d b/gas/testsuite/gas/mips/cp1-names-mips64r2.d
new file mode 100644
index 0000000..45bc9d1
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-mips64r2.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips64r2
+#name: MIPS CP1 register disassembly (mips64r2)
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,c1_fir
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,c1_ufr
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,c1_unfr
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,c1_fccr
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,c1_fexr
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,c1_fenr
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,c1_fcsr
+0+0080 <[^>]*> 44400000 	cfc1	\$0,c1_fir
+0+0084 <[^>]*> 44400800 	cfc1	\$0,c1_ufr
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,c1_unfr
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,c1_fccr
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,c1_fexr
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,c1_fenr
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,c1_fcsr
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-numeric.d b/gas/testsuite/gas/mips/cp1-names-numeric.d
new file mode 100644
index 0000000..e0ab337
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-numeric.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=numeric
+#name: MIPS CP1 register disassembly (numeric)
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,\$0
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,\$1
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,\$4
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,\$25
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,\$26
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,\$28
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,\$31
+0+0080 <[^>]*> 44400000 	cfc1	\$0,\$0
+0+0084 <[^>]*> 44400800 	cfc1	\$0,\$1
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,\$4
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,\$25
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,\$26
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,\$28
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,\$31
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-r3000.d b/gas/testsuite/gas/mips/cp1-names-r3000.d
new file mode 100644
index 0000000..25b5bfb
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-r3000.d
@@ -0,0 +1,75 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=r3000
+#name: MIPS CP1 register disassembly (r3000)
+#as: -32 -march=r3000
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,\$0
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,\$1
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,\$4
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,\$25
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,\$26
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,\$28
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,\$31
+0+0080 <[^>]*> 44400000 	cfc1	\$0,\$0
+0+0084 <[^>]*> 44400800 	cfc1	\$0,\$1
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,\$4
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,\$25
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,\$26
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,\$28
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,\$31
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-r4000.d b/gas/testsuite/gas/mips/cp1-names-r4000.d
new file mode 100644
index 0000000..a1030a2
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-r4000.d
@@ -0,0 +1,75 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric
+#name: MIPS CP1 register disassembly
+#as: -32 -march=r4000
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,\$0
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,\$1
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,\$4
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,\$25
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,\$26
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,\$28
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,\$31
+0+0080 <[^>]*> 44400000 	cfc1	\$0,\$0
+0+0084 <[^>]*> 44400800 	cfc1	\$0,\$1
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,\$4
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,\$25
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,\$26
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,\$28
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,\$31
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names-sb1.d b/gas/testsuite/gas/mips/cp1-names-sb1.d
new file mode 100644
index 0000000..d378400
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names-sb1.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=sb1
+#name: MIPS CP1 register disassembly (sb1)
+#source: cp1-names.s
+
+# Check objdump's handling of -M cp1-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 44c00000 	ctc1	\$0,\$0
+0+0004 <[^>]*> 44c00800 	ctc1	\$0,\$1
+0+0008 <[^>]*> 44c01000 	ctc1	\$0,\$2
+0+000c <[^>]*> 44c01800 	ctc1	\$0,\$3
+0+0010 <[^>]*> 44c02000 	ctc1	\$0,\$4
+0+0014 <[^>]*> 44c02800 	ctc1	\$0,\$5
+0+0018 <[^>]*> 44c03000 	ctc1	\$0,\$6
+0+001c <[^>]*> 44c03800 	ctc1	\$0,\$7
+0+0020 <[^>]*> 44c04000 	ctc1	\$0,\$8
+0+0024 <[^>]*> 44c04800 	ctc1	\$0,\$9
+0+0028 <[^>]*> 44c05000 	ctc1	\$0,\$10
+0+002c <[^>]*> 44c05800 	ctc1	\$0,\$11
+0+0030 <[^>]*> 44c06000 	ctc1	\$0,\$12
+0+0034 <[^>]*> 44c06800 	ctc1	\$0,\$13
+0+0038 <[^>]*> 44c07000 	ctc1	\$0,\$14
+0+003c <[^>]*> 44c07800 	ctc1	\$0,\$15
+0+0040 <[^>]*> 44c08000 	ctc1	\$0,\$16
+0+0044 <[^>]*> 44c08800 	ctc1	\$0,\$17
+0+0048 <[^>]*> 44c09000 	ctc1	\$0,\$18
+0+004c <[^>]*> 44c09800 	ctc1	\$0,\$19
+0+0050 <[^>]*> 44c0a000 	ctc1	\$0,\$20
+0+0054 <[^>]*> 44c0a800 	ctc1	\$0,\$21
+0+0058 <[^>]*> 44c0b000 	ctc1	\$0,\$22
+0+005c <[^>]*> 44c0b800 	ctc1	\$0,\$23
+0+0060 <[^>]*> 44c0c000 	ctc1	\$0,\$24
+0+0064 <[^>]*> 44c0c800 	ctc1	\$0,\$25
+0+0068 <[^>]*> 44c0d000 	ctc1	\$0,\$26
+0+006c <[^>]*> 44c0d800 	ctc1	\$0,\$27
+0+0070 <[^>]*> 44c0e000 	ctc1	\$0,\$28
+0+0074 <[^>]*> 44c0e800 	ctc1	\$0,\$29
+0+0078 <[^>]*> 44c0f000 	ctc1	\$0,\$30
+0+007c <[^>]*> 44c0f800 	ctc1	\$0,\$31
+0+0080 <[^>]*> 44400000 	cfc1	\$0,\$0
+0+0084 <[^>]*> 44400800 	cfc1	\$0,\$1
+0+0088 <[^>]*> 44401000 	cfc1	\$0,\$2
+0+008c <[^>]*> 44401800 	cfc1	\$0,\$3
+0+0090 <[^>]*> 44402000 	cfc1	\$0,\$4
+0+0094 <[^>]*> 44402800 	cfc1	\$0,\$5
+0+0098 <[^>]*> 44403000 	cfc1	\$0,\$6
+0+009c <[^>]*> 44403800 	cfc1	\$0,\$7
+0+00a0 <[^>]*> 44404000 	cfc1	\$0,\$8
+0+00a4 <[^>]*> 44404800 	cfc1	\$0,\$9
+0+00a8 <[^>]*> 44405000 	cfc1	\$0,\$10
+0+00ac <[^>]*> 44405800 	cfc1	\$0,\$11
+0+00b0 <[^>]*> 44406000 	cfc1	\$0,\$12
+0+00b4 <[^>]*> 44406800 	cfc1	\$0,\$13
+0+00b8 <[^>]*> 44407000 	cfc1	\$0,\$14
+0+00bc <[^>]*> 44407800 	cfc1	\$0,\$15
+0+00c0 <[^>]*> 44408000 	cfc1	\$0,\$16
+0+00c4 <[^>]*> 44408800 	cfc1	\$0,\$17
+0+00c8 <[^>]*> 44409000 	cfc1	\$0,\$18
+0+00cc <[^>]*> 44409800 	cfc1	\$0,\$19
+0+00d0 <[^>]*> 4440a000 	cfc1	\$0,\$20
+0+00d4 <[^>]*> 4440a800 	cfc1	\$0,\$21
+0+00d8 <[^>]*> 4440b000 	cfc1	\$0,\$22
+0+00dc <[^>]*> 4440b800 	cfc1	\$0,\$23
+0+00e0 <[^>]*> 4440c000 	cfc1	\$0,\$24
+0+00e4 <[^>]*> 4440c800 	cfc1	\$0,\$25
+0+00e8 <[^>]*> 4440d000 	cfc1	\$0,\$26
+0+00ec <[^>]*> 4440d800 	cfc1	\$0,\$27
+0+00f0 <[^>]*> 4440e000 	cfc1	\$0,\$28
+0+00f4 <[^>]*> 4440e800 	cfc1	\$0,\$29
+0+00f8 <[^>]*> 4440f000 	cfc1	\$0,\$30
+0+00fc <[^>]*> 4440f800 	cfc1	\$0,\$31
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/cp1-names.s b/gas/testsuite/gas/mips/cp1-names.s
new file mode 100644
index 0000000..7572354
--- /dev/null
+++ b/gas/testsuite/gas/mips/cp1-names.s
@@ -0,0 +1,77 @@
+# source file to test objdump's disassembly using various styles of
+# CP1 register names.
+
+	.set noreorder
+	.set noat
+
+	.globl text_label .text
+text_label:
+
+	ctc1	$0, $0
+	ctc1	$0, $1
+	ctc1	$0, $2
+	ctc1	$0, $3
+	ctc1	$0, $4
+	ctc1	$0, $5
+	ctc1	$0, $6
+	ctc1	$0, $7
+	ctc1	$0, $8
+	ctc1	$0, $9
+	ctc1	$0, $10
+	ctc1	$0, $11
+	ctc1	$0, $12
+	ctc1	$0, $13
+	ctc1	$0, $14
+	ctc1	$0, $15
+	ctc1	$0, $16
+	ctc1	$0, $17
+	ctc1	$0, $18
+	ctc1	$0, $19
+	ctc1	$0, $20
+	ctc1	$0, $21
+	ctc1	$0, $22
+	ctc1	$0, $23
+	ctc1	$0, $24
+	ctc1	$0, $25
+	ctc1	$0, $26
+	ctc1	$0, $27
+	ctc1	$0, $28
+	ctc1	$0, $29
+	ctc1	$0, $30
+	ctc1	$0, $31
+
+	cfc1	$0, $0
+	cfc1	$0, $1
+	cfc1	$0, $2
+	cfc1	$0, $3
+	cfc1	$0, $4
+	cfc1	$0, $5
+	cfc1	$0, $6
+	cfc1	$0, $7
+	cfc1	$0, $8
+	cfc1	$0, $9
+	cfc1	$0, $10
+	cfc1	$0, $11
+	cfc1	$0, $12
+	cfc1	$0, $13
+	cfc1	$0, $14
+	cfc1	$0, $15
+	cfc1	$0, $16
+	cfc1	$0, $17
+	cfc1	$0, $18
+	cfc1	$0, $19
+	cfc1	$0, $20
+	cfc1	$0, $21
+	cfc1	$0, $22
+	cfc1	$0, $23
+	cfc1	$0, $24
+	cfc1	$0, $25
+	cfc1	$0, $26
+	cfc1	$0, $27
+	cfc1	$0, $28
+	cfc1	$0, $29
+	cfc1	$0, $30
+	cfc1	$0, $31
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+      .space  8
diff --git a/gas/testsuite/gas/mips/micromips-insn32.d b/gas/testsuite/gas/mips/micromips-insn32.d
index a28c519..c0ff2db 100644
--- a/gas/testsuite/gas/mips/micromips-insn32.d
+++ b/gas/testsuite/gas/mips/micromips-insn32.d
@@ -5412,11 +5412,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	5401 1b3b 	ceil\.w\.s	\$f0,\$f1
 [ 0-9a-f]+:	57df 1b3b 	ceil\.w\.s	\$f30,\$f31
 [ 0-9a-f]+:	5442 1b3b 	ceil\.w\.s	\$f2,\$f2
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5437,18 +5437,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5469,13 +5469,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 cd3c 	cfc2	a1,\$0
 [ 0-9a-f]+:	00a1 cd3c 	cfc2	a1,\$1
 [ 0-9a-f]+:	00a2 cd3c 	cfc2	a1,\$2
@@ -5508,11 +5508,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	00bd cd3c 	cfc2	a1,\$29
 [ 0-9a-f]+:	00be cd3c 	cfc2	a1,\$30
 [ 0-9a-f]+:	00bf cd3c 	cfc2	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5533,18 +5533,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5565,13 +5565,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 dd3c 	ctc2	a1,\$0
 [ 0-9a-f]+:	00a1 dd3c 	ctc2	a1,\$1
 [ 0-9a-f]+:	00a2 dd3c 	ctc2	a1,\$2
@@ -6787,11 +6787,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54bd 243b 	dmfc1	a1,\$f29
 [ 0-9a-f]+:	54be 243b 	dmfc1	a1,\$f30
 [ 0-9a-f]+:	54bf 243b 	dmfc1	a1,\$f31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6812,18 +6812,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6844,13 +6844,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
 [ 0-9a-f]+:	0040 6d3c 	dmfc2	v0,\$0
 [ 0-9a-f]+:	0041 6d3c 	dmfc2	v0,\$1
 [ 0-9a-f]+:	0042 6d3c 	dmfc2	v0,\$2
diff --git a/gas/testsuite/gas/mips/micromips-noinsn32.d b/gas/testsuite/gas/mips/micromips-noinsn32.d
index 520c9cb..5bbaab1 100644
--- a/gas/testsuite/gas/mips/micromips-noinsn32.d
+++ b/gas/testsuite/gas/mips/micromips-noinsn32.d
@@ -5391,11 +5391,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	5401 1b3b 	ceil\.w\.s	\$f0,\$f1
 [ 0-9a-f]+:	57df 1b3b 	ceil\.w\.s	\$f30,\$f31
 [ 0-9a-f]+:	5442 1b3b 	ceil\.w\.s	\$f2,\$f2
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5416,18 +5416,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5448,13 +5448,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 cd3c 	cfc2	a1,\$0
 [ 0-9a-f]+:	00a1 cd3c 	cfc2	a1,\$1
 [ 0-9a-f]+:	00a2 cd3c 	cfc2	a1,\$2
@@ -5487,11 +5487,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	00bd cd3c 	cfc2	a1,\$29
 [ 0-9a-f]+:	00be cd3c 	cfc2	a1,\$30
 [ 0-9a-f]+:	00bf cd3c 	cfc2	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5512,18 +5512,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5544,13 +5544,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 dd3c 	ctc2	a1,\$0
 [ 0-9a-f]+:	00a1 dd3c 	ctc2	a1,\$1
 [ 0-9a-f]+:	00a2 dd3c 	ctc2	a1,\$2
@@ -6766,11 +6766,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54bd 243b 	dmfc1	a1,\$f29
 [ 0-9a-f]+:	54be 243b 	dmfc1	a1,\$f30
 [ 0-9a-f]+:	54bf 243b 	dmfc1	a1,\$f31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6791,18 +6791,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6823,13 +6823,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
 [ 0-9a-f]+:	0040 6d3c 	dmfc2	v0,\$0
 [ 0-9a-f]+:	0041 6d3c 	dmfc2	v0,\$1
 [ 0-9a-f]+:	0042 6d3c 	dmfc2	v0,\$2
diff --git a/gas/testsuite/gas/mips/micromips-trap.d b/gas/testsuite/gas/mips/micromips-trap.d
index f1167a0..cfb0979 100644
--- a/gas/testsuite/gas/mips/micromips-trap.d
+++ b/gas/testsuite/gas/mips/micromips-trap.d
@@ -5397,11 +5397,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	5401 1b3b 	ceil\.w\.s	\$f0,\$f1
 [ 0-9a-f]+:	57df 1b3b 	ceil\.w\.s	\$f30,\$f31
 [ 0-9a-f]+:	5442 1b3b 	ceil\.w\.s	\$f2,\$f2
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5422,18 +5422,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5454,13 +5454,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 cd3c 	cfc2	a1,\$0
 [ 0-9a-f]+:	00a1 cd3c 	cfc2	a1,\$1
 [ 0-9a-f]+:	00a2 cd3c 	cfc2	a1,\$2
@@ -5493,11 +5493,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	00bd cd3c 	cfc2	a1,\$29
 [ 0-9a-f]+:	00be cd3c 	cfc2	a1,\$30
 [ 0-9a-f]+:	00bf cd3c 	cfc2	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5518,18 +5518,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5550,13 +5550,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 dd3c 	ctc2	a1,\$0
 [ 0-9a-f]+:	00a1 dd3c 	ctc2	a1,\$1
 [ 0-9a-f]+:	00a2 dd3c 	ctc2	a1,\$2
@@ -6757,11 +6757,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54bd 243b 	dmfc1	a1,\$f29
 [ 0-9a-f]+:	54be 243b 	dmfc1	a1,\$f30
 [ 0-9a-f]+:	54bf 243b 	dmfc1	a1,\$f31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6782,18 +6782,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6814,13 +6814,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
 [ 0-9a-f]+:	0040 6d3c 	dmfc2	v0,\$0
 [ 0-9a-f]+:	0041 6d3c 	dmfc2	v0,\$1
 [ 0-9a-f]+:	0042 6d3c 	dmfc2	v0,\$2
diff --git a/gas/testsuite/gas/mips/micromips.d b/gas/testsuite/gas/mips/micromips.d
index 4821d09..e262663 100644
--- a/gas/testsuite/gas/mips/micromips.d
+++ b/gas/testsuite/gas/mips/micromips.d
@@ -5469,11 +5469,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	5401 1b3b 	ceil\.w\.s	\$f0,\$f1
 [ 0-9a-f]+:	57df 1b3b 	ceil\.w\.s	\$f30,\$f31
 [ 0-9a-f]+:	5442 1b3b 	ceil\.w\.s	\$f2,\$f2
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5494,18 +5494,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
-[ 0-9a-f]+:	54a0 103b 	cfc1	a1,\$0
-[ 0-9a-f]+:	54a1 103b 	cfc1	a1,\$1
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 103b 	cfc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 103b 	cfc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 103b 	cfc1	a1,\$2
 [ 0-9a-f]+:	54a3 103b 	cfc1	a1,\$3
-[ 0-9a-f]+:	54a4 103b 	cfc1	a1,\$4
+[ 0-9a-f]+:	54a4 103b 	cfc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 103b 	cfc1	a1,\$5
 [ 0-9a-f]+:	54a6 103b 	cfc1	a1,\$6
 [ 0-9a-f]+:	54a7 103b 	cfc1	a1,\$7
@@ -5526,13 +5526,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 103b 	cfc1	a1,\$22
 [ 0-9a-f]+:	54b7 103b 	cfc1	a1,\$23
 [ 0-9a-f]+:	54b8 103b 	cfc1	a1,\$24
-[ 0-9a-f]+:	54b9 103b 	cfc1	a1,\$25
-[ 0-9a-f]+:	54ba 103b 	cfc1	a1,\$26
+[ 0-9a-f]+:	54b9 103b 	cfc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 103b 	cfc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 103b 	cfc1	a1,\$27
-[ 0-9a-f]+:	54bc 103b 	cfc1	a1,\$28
+[ 0-9a-f]+:	54bc 103b 	cfc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 103b 	cfc1	a1,\$29
 [ 0-9a-f]+:	54be 103b 	cfc1	a1,\$30
-[ 0-9a-f]+:	54bf 103b 	cfc1	a1,\$31
+[ 0-9a-f]+:	54bf 103b 	cfc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 cd3c 	cfc2	a1,\$0
 [ 0-9a-f]+:	00a1 cd3c 	cfc2	a1,\$1
 [ 0-9a-f]+:	00a2 cd3c 	cfc2	a1,\$2
@@ -5565,11 +5565,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	00bd cd3c 	cfc2	a1,\$29
 [ 0-9a-f]+:	00be cd3c 	cfc2	a1,\$30
 [ 0-9a-f]+:	00bf cd3c 	cfc2	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5590,18 +5590,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
-[ 0-9a-f]+:	54a0 183b 	ctc1	a1,\$0
-[ 0-9a-f]+:	54a1 183b 	ctc1	a1,\$1
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 183b 	ctc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 183b 	ctc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 183b 	ctc1	a1,\$2
 [ 0-9a-f]+:	54a3 183b 	ctc1	a1,\$3
-[ 0-9a-f]+:	54a4 183b 	ctc1	a1,\$4
+[ 0-9a-f]+:	54a4 183b 	ctc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 183b 	ctc1	a1,\$5
 [ 0-9a-f]+:	54a6 183b 	ctc1	a1,\$6
 [ 0-9a-f]+:	54a7 183b 	ctc1	a1,\$7
@@ -5622,13 +5622,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 183b 	ctc1	a1,\$22
 [ 0-9a-f]+:	54b7 183b 	ctc1	a1,\$23
 [ 0-9a-f]+:	54b8 183b 	ctc1	a1,\$24
-[ 0-9a-f]+:	54b9 183b 	ctc1	a1,\$25
-[ 0-9a-f]+:	54ba 183b 	ctc1	a1,\$26
+[ 0-9a-f]+:	54b9 183b 	ctc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 183b 	ctc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 183b 	ctc1	a1,\$27
-[ 0-9a-f]+:	54bc 183b 	ctc1	a1,\$28
+[ 0-9a-f]+:	54bc 183b 	ctc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 183b 	ctc1	a1,\$29
 [ 0-9a-f]+:	54be 183b 	ctc1	a1,\$30
-[ 0-9a-f]+:	54bf 183b 	ctc1	a1,\$31
+[ 0-9a-f]+:	54bf 183b 	ctc1	a1,c1_fcsr
 [ 0-9a-f]+:	00a0 dd3c 	ctc2	a1,\$0
 [ 0-9a-f]+:	00a1 dd3c 	ctc2	a1,\$1
 [ 0-9a-f]+:	00a2 dd3c 	ctc2	a1,\$2
@@ -6844,11 +6844,11 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54bd 243b 	dmfc1	a1,\$f29
 [ 0-9a-f]+:	54be 243b 	dmfc1	a1,\$f30
 [ 0-9a-f]+:	54bf 243b 	dmfc1	a1,\$f31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6869,18 +6869,18 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
-[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,\$0
-[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,\$1
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
+[ 0-9a-f]+:	54a0 2c3b 	dmtc1	a1,c1_fir
+[ 0-9a-f]+:	54a1 2c3b 	dmtc1	a1,c1_ufr
 [ 0-9a-f]+:	54a2 2c3b 	dmtc1	a1,\$2
 [ 0-9a-f]+:	54a3 2c3b 	dmtc1	a1,\$3
-[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,\$4
+[ 0-9a-f]+:	54a4 2c3b 	dmtc1	a1,c1_unfr
 [ 0-9a-f]+:	54a5 2c3b 	dmtc1	a1,\$5
 [ 0-9a-f]+:	54a6 2c3b 	dmtc1	a1,\$6
 [ 0-9a-f]+:	54a7 2c3b 	dmtc1	a1,\$7
@@ -6901,13 +6901,13 @@ Disassembly of section \.text:
 [ 0-9a-f]+:	54b6 2c3b 	dmtc1	a1,\$22
 [ 0-9a-f]+:	54b7 2c3b 	dmtc1	a1,\$23
 [ 0-9a-f]+:	54b8 2c3b 	dmtc1	a1,\$24
-[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,\$25
-[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,\$26
+[ 0-9a-f]+:	54b9 2c3b 	dmtc1	a1,c1_fccr
+[ 0-9a-f]+:	54ba 2c3b 	dmtc1	a1,c1_fexr
 [ 0-9a-f]+:	54bb 2c3b 	dmtc1	a1,\$27
-[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,\$28
+[ 0-9a-f]+:	54bc 2c3b 	dmtc1	a1,c1_fenr
 [ 0-9a-f]+:	54bd 2c3b 	dmtc1	a1,\$29
 [ 0-9a-f]+:	54be 2c3b 	dmtc1	a1,\$30
-[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,\$31
+[ 0-9a-f]+:	54bf 2c3b 	dmtc1	a1,c1_fcsr
 [ 0-9a-f]+:	0040 6d3c 	dmfc2	v0,\$0
 [ 0-9a-f]+:	0041 6d3c 	dmfc2	v0,\$1
 [ 0-9a-f]+:	0042 6d3c 	dmfc2	v0,\$2
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 121566a..c07c24d 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -969,6 +969,18 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "cp0sel-names-mips64r2"
     run_dump_test "cp0sel-names-sb1"
 
+    run_dump_test "cp1-names-numeric"
+    run_dump_test "cp1-names-r3000"
+    run_dump_test "cp1-names-r4000" \
+		  { { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } }
+    run_dump_test "cp1-names-r4000" \
+		  { { {name} {(r4400)} } { {objdump} {-M cp0-names=r4400} } }
+    run_dump_test "cp1-names-mips32"
+    run_dump_test "cp1-names-mips32r2"
+    run_dump_test "cp1-names-mips64"
+    run_dump_test "cp1-names-mips64r2"
+    run_dump_test "cp1-names-sb1"
+
     run_dump_test "hwr-names-numeric"
     run_dump_test "hwr-names-mips32r2"
     run_dump_test "hwr-names-mips64r2"
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1929ffc..d22011b 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -115,6 +115,14 @@ static const char * const mips_cp0_names_numeric[32] =
   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
 };
 
+static const char * const mips_cp1_names_numeric[32] =
+{
+  "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
+  "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
+  "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
+  "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
+};
+
 static const char * const mips_cp0_names_r3000[32] =
 {
   "c0_index",     "c0_random",    "c0_entrylo",   "$3",
@@ -175,6 +183,18 @@ static const char * const mips_cp0_names_mips3264[32] =
   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
 };
 
+static const char * const mips_cp1_names_mips3264[32] =
+{
+  "c1_fir",       "c1_ufr",       "$2",           "$3",
+  "c1_unfr",      "$5",           "$6",           "$7",
+  "$8",           "$9",           "$10",          "$11",
+  "$12",          "$13",          "$14",          "$15",
+  "$16",          "$17",          "$18",          "$19",
+  "$20",          "$21",          "$22",          "$23",
+  "$24",          "c1_fccr",      "c1_fexr",      "$27",
+  "c1_fenr",      "$29",          "$30",          "c1_fcsr"
+};
+
 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
 {
   { 16, 1, "c0_config1"		},
@@ -436,62 +456,88 @@ struct mips_arch_choice
   const char * const *cp0_names;
   const struct mips_cp0sel_name *cp0sel_names;
   unsigned int cp0sel_names_len;
+  const char * const *cp1_names;
   const char * const *hwr_names;
 };
 
 const struct mips_arch_choice mips_arch_choices[] =
 {
   { "numeric",	0, 0, 0, 0, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
 
   { "r3000",	1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0,
-    mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r3900",	1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r4000",	1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0,
-    mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r4010",	1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "vr4100",	1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "vr4111",	1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "vr4120",	1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r4300",	1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r4400",	1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0,
-    mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r4600",	1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r4650",	1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r5000",	1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "vr5400",	1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "vr5500",	1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r5900",	1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0,
-    mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r6000",	1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "rm7000",	1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "rm9000",	1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r8000",	1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r10000",	1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r12000",	1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r14000",	1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "r16000",	1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
   { "mips5",	1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
 
   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
@@ -502,7 +548,7 @@ const struct mips_arch_choice mips_arch_choices[] =
     ISA_MIPS32,  ASE_SMARTMIPS,
     mips_cp0_names_mips3264,
     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
-    mips_hwr_names_numeric },
+    mips_cp1_names_mips3264, mips_hwr_names_numeric },
 
   { "mips32r2",	1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     ISA_MIPS32R2,
@@ -510,14 +556,14 @@ const struct mips_arch_choice mips_arch_choices[] =
      | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
-    mips_hwr_names_mips3264r2 },
+    mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
 
   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
   { "mips64",	1, bfd_mach_mipsisa64, CPU_MIPS64,
     ISA_MIPS64,  ASE_MIPS3D | ASE_MDMX,
     mips_cp0_names_mips3264,
     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
-    mips_hwr_names_numeric },
+    mips_cp1_names_mips3264, mips_hwr_names_numeric },
 
   { "mips64r2",	1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
     ISA_MIPS64R2,
@@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
      | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
-    mips_hwr_names_mips3264r2 },
+    mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
 
   { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
     ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
     mips_cp0_names_sb1,
     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
-    mips_hwr_names_numeric },
+    mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson2e",   1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
     ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric,
-    NULL, 0, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
     ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric,
-    NULL, 0, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "loongson3a",   1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
     ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric,
-    NULL, 0, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "octeon",   1, bfd_mach_mips_octeon, CPU_OCTEON,
     ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
-    mips_hwr_names_numeric },
+    mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "octeon+",   1, bfd_mach_mips_octeonp, CPU_OCTEONP,
     ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric,
-    NULL, 0, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "octeon2",   1, bfd_mach_mips_octeon2, CPU_OCTEON2,
     ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric,
-    NULL, 0, mips_hwr_names_numeric },
+    NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
     ISA_MIPS64 | INSN_XLR, 0,
     mips_cp0_names_xlr,
     mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
-    mips_hwr_names_numeric },
+    mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   /* XLP is mostly like XLR, with the prominent exception it is being
      MIPS64R2.  */
@@ -569,12 +615,13 @@ const struct mips_arch_choice mips_arch_choices[] =
     ISA_MIPS64R2 | INSN_XLR, 0,
     mips_cp0_names_xlr,
     mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
-    mips_hwr_names_numeric },
+    mips_cp1_names_numeric, mips_hwr_names_numeric },
 
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
   { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0,
-    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+    mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
+    mips_hwr_names_numeric },
 };
 
 /* ISA and processor type to disassemble for, and register names to use.
@@ -589,6 +636,7 @@ static const char * const *mips_fpr_names;
 static const char * const *mips_cp0_names;
 static const struct mips_cp0sel_name *mips_cp0sel_names;
 static int mips_cp0sel_names_len;
+static const char * const *mips_cp1_names;
 static const char * const *mips_hwr_names;
 
 /* Other options */
@@ -694,6 +742,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
   mips_cp0_names = mips_cp0_names_numeric;
   mips_cp0sel_names = NULL;
   mips_cp0sel_names_len = 0;
+  mips_cp1_names = mips_cp1_names_numeric;
   mips_hwr_names = mips_hwr_names_numeric;
   no_aliases = 0;
 
@@ -727,6 +776,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
       mips_cp0_names = chosen_arch->cp0_names;
       mips_cp0sel_names = chosen_arch->cp0sel_names;
       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+      mips_cp1_names = chosen_arch->cp1_names;
       mips_hwr_names = chosen_arch->hwr_names;
     }
 #endif
@@ -810,6 +860,15 @@ parse_mips_dis_option (const char *option, unsigned int len)
       return;
     }
 
+  if (strncmp ("cp1-names", option, optionlen) == 0
+      && strlen ("cp1-names") == optionlen)
+    {
+      chosen_arch = choose_arch_by_name (val, vallen);
+      if (chosen_arch != NULL)
+	mips_cp1_names = chosen_arch->cp1_names;
+      return;
+    }
+
   if (strncmp ("hwr-names", option, optionlen) == 0
       && strlen ("hwr-names") == optionlen)
     {
@@ -838,6 +897,7 @@ parse_mips_dis_option (const char *option, unsigned int len)
 	  mips_cp0_names = chosen_arch->cp0_names;
 	  mips_cp0sel_names = chosen_arch->cp0sel_names;
 	  mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
+	  mips_cp1_names = chosen_arch->cp1_names;
 	  mips_hwr_names = chosen_arch->hwr_names;
 	}
       return;
@@ -927,6 +987,8 @@ print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
     case OP_REG_COPRO:
       if (opcode->name[strlen (opcode->name) - 1] == '0')
 	info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]);
+      else if (opcode->name[strlen (opcode->name) - 1] == '1')
+	info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]);
       else
 	info->fprintf_func (info->stream, "$%d", regno);
       break;
-- 
1.7.10.1

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-12-11 12:20                 ` Andrew Bennett
@ 2013-12-13 16:39                   ` Richard Sandiford
  2013-12-13 18:36                     ` Maciej W. Rozycki
  2013-12-14 18:51                     ` Andrew Bennett
  0 siblings, 2 replies; 16+ messages in thread
From: Richard Sandiford @ 2013-12-13 16:39 UTC (permalink / raw)
  To: Andrew Bennett; +Cc: Maciej W. Rozycki, binutils

Hi Andrew,

Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
for all MIPS32 and MIPS64 targets?  I realise some of them don't have an FPU,
but if we see (presumably emulated) FPU instructions anyway, then I think we
might as well follow the architecture names for the registers.

E.g.:

Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
>    { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
>      ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
>      mips_cp0_names_sb1,
>      mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
> -    mips_hwr_names_numeric },
> +    mips_cp1_names_numeric, mips_hwr_names_numeric },

SB1 did have an FPU.

If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
entry having mips_cp1_names_mips3264.  If not then let me know :-)

If you don't have commit access yet then please feel to sign up using:
https://sourceware.org/cgi-bin/pdw/ps_form.cgi listing me as approver.

Thanks,
Richard

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-12-13 16:39                   ` Richard Sandiford
@ 2013-12-13 18:36                     ` Maciej W. Rozycki
  2013-12-14 10:13                       ` Richard Sandiford
  2013-12-14 18:51                     ` Andrew Bennett
  1 sibling, 1 reply; 16+ messages in thread
From: Maciej W. Rozycki @ 2013-12-13 18:36 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: Andrew Bennett, binutils

On Fri, 13 Dec 2013, Richard Sandiford wrote:

> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
> for all MIPS32 and MIPS64 targets?  I realise some of them don't have an FPU,
> but if we see (presumably emulated) FPU instructions anyway, then I think we
> might as well follow the architecture names for the registers.

 Rev. 1 FPUs only had the FIR, FCCR, FEXR, FENR and FCSR registers.  Older 
ISAs only had the FIR and FCSR registers.  How about we have separate 
lists just as with CP0?  Furthermore I don't think these additional lists 
should be a prerequisite for the acceptance of this patch.

> E.g.:
> 
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> > @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
> >    { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
> >      ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
> >      mips_cp0_names_sb1,
> >      mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
> > -    mips_hwr_names_numeric },
> > +    mips_cp1_names_numeric, mips_hwr_names_numeric },
> 
> SB1 did have an FPU.

 It was rev. 1 however.

> If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
> entry having mips_cp1_names_mips3264.  If not then let me know :-)

 Shouldn't there be a complementing GAS part though?

  Maciej

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-12-13 18:36                     ` Maciej W. Rozycki
@ 2013-12-14 10:13                       ` Richard Sandiford
  2014-01-10 18:12                         ` Maciej W. Rozycki
  0 siblings, 1 reply; 16+ messages in thread
From: Richard Sandiford @ 2013-12-14 10:13 UTC (permalink / raw)
  To: Maciej W. Rozycki; +Cc: Andrew Bennett, binutils

"Maciej W. Rozycki" <macro@codesourcery.com> writes:
> On Fri, 13 Dec 2013, Richard Sandiford wrote:
>
>> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
>> for all MIPS32 and MIPS64 targets?  I realise some of them don't have an FPU,
>> but if we see (presumably emulated) FPU instructions anyway, then I think we
>> might as well follow the architecture names for the registers.
>
>  Rev. 1 FPUs only had the FIR, FCCR, FEXR, FENR and FCSR registers.  Older 
> ISAs only had the FIR and FCSR registers.  How about we have separate 
> lists just as with CP0?  Furthermore I don't think these additional lists 
> should be a prerequisite for the acceptance of this patch.

I agree extra lists shouldn't be a requirement.  And until more are
added I think the pragmatic thing to do is to use the full list for
"mips32" and "mips64" too, which is what Andrew's patch did.  But if
we do that then I think we should also use the full list for specific
ISA_MIPS32 and ISA_MIPS64 processors as well the generic ISA.

>> If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
>> entry having mips_cp1_names_mips3264.  If not then let me know :-)
>
>  Shouldn't there be a complementing GAS part though?

I think that's future work too.  There's no corresponding gas support
for CP0 registers (or any notion of ".set arch"-specific registers really),
so it wouldn't be a trivial patch.

Thanks,
Richard

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH] Add MIPS ufr macro instruction
  2013-12-13 16:39                   ` Richard Sandiford
  2013-12-13 18:36                     ` Maciej W. Rozycki
@ 2013-12-14 18:51                     ` Andrew Bennett
  1 sibling, 0 replies; 16+ messages in thread
From: Andrew Bennett @ 2013-12-14 18:51 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: Maciej W. Rozycki, binutils

> Hi Andrew,
> 
> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
> for all MIPS32 and MIPS64 targets?  I realise some of them don't have an FPU,
> but if we see (presumably emulated) FPU instructions anyway, then I think we
> might as well follow the architecture names for the registers.
>
> E.g.:
>
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>> @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
>>    { "sb1",   1, bfd_mach_mips_sb1, CPU_SB1,
>>     ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
>>      mips_cp0_names_sb1,
>>      mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
>> -    mips_hwr_names_numeric },
>> +    mips_cp1_names_numeric, mips_hwr_names_numeric },
>
>SB1 did have an FPU.
>
>If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
>entry having mips_cp1_names_mips3264.  If not then let me know :-)

Yes that is fine.

Regards,


Andrew

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH] Add MIPS ufr macro instruction
  2013-12-14 10:13                       ` Richard Sandiford
@ 2014-01-10 18:12                         ` Maciej W. Rozycki
  0 siblings, 0 replies; 16+ messages in thread
From: Maciej W. Rozycki @ 2014-01-10 18:12 UTC (permalink / raw)
  To: Richard Sandiford; +Cc: Andrew Bennett, binutils

On Sat, 14 Dec 2013, Richard Sandiford wrote:

> >> If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
> >> entry having mips_cp1_names_mips3264.  If not then let me know :-)
> >
> >  Shouldn't there be a complementing GAS part though?
> 
> I think that's future work too.  There's no corresponding gas support
> for CP0 registers (or any notion of ".set arch"-specific registers really),
> so it wouldn't be a trivial patch.

 Hmm, I thought the original intent of this change was to extend GAS to 
support a more readable form of COP1 instructions accessing CP0.Status.FR 
and now this replacement change has dropped the original proposal in 
favour to one that affects the disassembler only.  FAOD I'm perfectly fine 
with that move, just a little bit surprised.

 FWIW, UFR as originally proposed can be trivially implemented with .macro 
if required.

  Maciej

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2014-01-10 18:12 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-11-08 14:04 [PATCH] Add MIPS ufr macro instruction Andrew Bennett
2013-11-08 17:33 ` David Daney
2013-11-09 11:27 ` Richard Sandiford
2013-11-14  9:12   ` Richard Sandiford
2013-11-14 12:42     ` Andrew Bennett
2013-11-20 16:14       ` Andrew Bennett
2013-11-24 18:32         ` Richard Sandiford
2013-11-25  8:40           ` Maciej W. Rozycki
2013-12-09 15:38             ` Andrew Bennett
2013-12-10 12:38               ` Richard Sandiford
2013-12-11 12:20                 ` Andrew Bennett
2013-12-13 16:39                   ` Richard Sandiford
2013-12-13 18:36                     ` Maciej W. Rozycki
2013-12-14 10:13                       ` Richard Sandiford
2014-01-10 18:12                         ` Maciej W. Rozycki
2013-12-14 18:51                     ` Andrew Bennett

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