From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8597 invoked by alias); 1 Apr 2012 19:39:07 -0000 Received: (qmail 8589 invoked by uid 22791); 1 Apr 2012 19:39:06 -0000 X-SWARE-Spam-Status: No, hits=-4.1 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-wg0-f43.google.com (HELO mail-wg0-f43.google.com) (74.125.82.43) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 01 Apr 2012 19:38:53 +0000 Received: by wgbdr12 with SMTP id dr12so1649119wgb.12 for ; Sun, 01 Apr 2012 12:38:52 -0700 (PDT) Received: by 10.180.78.40 with SMTP id y8mr12497950wiw.15.1333309131978; Sun, 01 Apr 2012 12:38:51 -0700 (PDT) Received: from localhost (rsandifo.gotadsl.co.uk. [82.133.89.107]) by mx.google.com with ESMTPS id 6sm27870427wiz.1.2012.04.01.12.38.50 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 01 Apr 2012 12:38:51 -0700 (PDT) From: Richard Sandiford To: Jia Liu Mail-Followup-To: Jia Liu ,binutils@sourceware.org, rdsandiford@googlemail.com Cc: binutils@sourceware.org Subject: Re: [PATCH] [MIPS] add MIPS64DSPR2 support. References: <87zkcvrayn.fsf@firetop.home> Date: Sun, 01 Apr 2012 19:39:00 -0000 In-Reply-To: (Jia Liu's message of "Tue, 27 Mar 2012 15:45:46 +0800") Message-ID: <87vcljjl88.fsf@talisman.home> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2012-04/txt/msg00001.txt.bz2 Hi Jia, Jia Liu writes: > On Tue, Feb 7, 2012 at 3:57 AM, Richard Sandiford > wrote: >> Thanks for the patch. >> >> Liu writes: >>> I've added MIPS64DSPR2 support to binutils. >>> Please review. >> >> Following on from Chao-ying's question on the GCC list: what target >> are you using? =C2=A0Is it an emulated implementation of MIPS64 DSPr2 >> (e.g. QEMU)? =C2=A0Or do you have a real hardware implementation? >> Just curious :-) >> >> Chao-ying, just to check: it sounded from your message on the GCC list >> that some instructions had been removed from the ASE. =C2=A0Is that righ= t? >> If so, is the latest document on the MIPS website up-to-date, >> or have there been changes since then? >> >> Liu: In the meantime, a patch of this size will need a copyright >> assignment. =C2=A0Do you already have one on file? =C2=A0If not, please = send >> a note to me privately and I can send you the form. >> >> Thanks, >> Richard > > Hi Richard > > Thank you. > I've got and signed the FSF Assignment, and posted them to FSF. > Please checkin my patch. Thanks for your patience. I'm really sorry about the confusion here, which is entirely my fault. My understanding from Chao-Ying's message was that MIPS had effectively withdrawn the current MIPS64 DSP r1/r2 spec. They are starting the MIPS64 DSP spec from scratch for r3. This means that no processor has, and I assume never will, support those extra MIPS64 DSP r1 and r2 instructions. It seems MIPS64 DSP r1/r2 is effectively dead. So I think Chao-Ying's suggestion was that we should treat MIPS64 DSP r1/r2 the same as MIPS32 DSP r1/r2. We should pretend that the separate MIPS64 DSP r1 and r2 specs never existed: > MIPS has an internal MIPS64 DSP spec verison 3.00, but hasn't released > yet. The version 3.00 spec is quite different from the previous > version. The best for now is to assume all MIPS32 DSP r1/DSP r2 > instructions appear in the MIPS64 DSP r1/DSP r2 spec, and to not > support any new instructions in GCC/Binutils. So my hope was that once version 3 is released, we'll see which instructions are in MIPS64 DSP r3 and not in MIPS32 DSP r3. Probably some of them will overlap r1 and r2 (but I'm just speculating there). So I was hoping we could add DSP r3 support at that stage, using your patch as a starting point. Sorry again about this :-( Richard