* [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
@ 2010-11-29 11:58 Mingming Sun
[not found] ` <87oc96wj7m.fsf@firetop.home>
0 siblings, 1 reply; 7+ messages in thread
From: Mingming Sun @ 2010-11-29 11:58 UTC (permalink / raw)
To: binutils
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Hello,
This patch adds Loongson3A mul/div instructions.
Is it OK?
Thanks,
Mingming Sun
2010-11-29 Mingming Sun <mingm.sun@gmail.com>
gas/ChangeLog
* config/tc-mips.c (macro_build): Add loongson3a-specific instructions support.
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
include/ChangeLog
* opcode/mips.h: Define OP_SH_MINUS_A, OP_MASK_MINUS_A, OP_SH_MINUS_B,
OP_MASK_MINUS_B, OP_SH_MINUS_F, OP_MASK_MINUS_F, OP_SH_RY, OP_MASK_RY,
OP_SH_FZ, OP_MASK_FZ, INSN_WRITE_GPR_Y, INSN_WRITE_FPR_Z,
INSN_READ_GPR_D, INSN_READ_GPR_Y, INSN_READ_FPR_Z.
opcodes/ChangeLog
* mips-dis.c (print_insn_args): Add loongson3a-specific instructions support.
* mips-opc.c: Define WR_z, RD_y, RD_z, RD_d.
(mips_builtin_opcodes): Add loongson3a-specific instructions.
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Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.434
diff -u -p -r1.434 tc-mips.c
--- gas/config/tc-mips.c 23 Nov 2010 17:04:10 -0000 1.434
+++ gas/config/tc-mips.c 26 Nov 2010 06:56:52 -0000
@@ -3698,6 +3698,11 @@ macro_build (expressionS *ep, const char
INSERT_OPERAND (BP, insn, va_arg (args, int));
continue;
+ /* Loongson-3A */
+ case 'y':
+ INSERT_OPERAND (RY, insn, va_arg (args, int));
+ continue;
+
case 't':
case 'w':
case 'E':
@@ -3713,6 +3718,11 @@ macro_build (expressionS *ep, const char
INSERT_OPERAND (FT, insn, va_arg (args, int));
continue;
+ /* Loongson-3A */
+ case '^':
+ INSERT_OPERAND (FZ, insn, va_arg (args, int));
+ continue;
+
case 'd':
case 'G':
case 'K':
@@ -8476,6 +8486,20 @@ validate_mips_insn (const struct mips_op
return 0;
}
break;
+ case '-': /* Loongson-3A */
+ switch (c = *p++)
+ {
+ case 'A': USE_BITS (OP_MASK_MINUS_A, OP_SH_MINUS_A); break;
+ case 'B': USE_BITS (OP_MASK_MINUS_B, OP_SH_MINUS_B); break;
+ case 'F': USE_BITS (OP_MASK_MINUS_F, OP_SH_MINUS_F); break;
+
+ default:
+ as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
+ c, opc->name, opc->args);
+ return 0;
+ }
+ break;
+
case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break;
@@ -8495,6 +8519,7 @@ validate_mips_insn (const struct mips_op
case 'O': USE_BITS (OP_MASK_ALN, OP_SH_ALN); break;
case 'Q': USE_BITS (OP_MASK_VSEL, OP_SH_VSEL);
USE_BITS (OP_MASK_FT, OP_SH_FT); break;
+ case '^': USE_BITS (OP_MASK_FZ, OP_SH_FZ); break;
case 'R': USE_BITS (OP_MASK_FR, OP_SH_FR); break;
case 'S': USE_BITS (OP_MASK_FS, OP_SH_FS); break;
case 'T': USE_BITS (OP_MASK_FT, OP_SH_FT); break;
@@ -8522,6 +8547,7 @@ validate_mips_insn (const struct mips_op
case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
+ case 'y': USE_BITS (OP_MASK_RY, OP_SH_RY); break;
case 'x': break;
case 'z': break;
case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
@@ -8742,6 +8768,62 @@ mips_ip (char *str, struct mips_cl_insn
if (*s == '\0')
return;
break;
+ /* Loongson-3A */
+ case '-':
+ switch (*++args)
+ {
+ case 'A': /* 8-bit signed offset in bit 6 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ min_range = -((OP_MASK_MINUS_A + 1) >> 1);
+ max_range = ((OP_MASK_MINUS_A + 1) >> 1) - 1;
+ if (imm_expr.X_add_number < min_range
+ || imm_expr.X_add_number > max_range)
+ {
+ as_bad (_("immediate not in range %ld..%ld (%ld)"),
+ (long) min_range, (long) max_range,
+ (long) imm_expr.X_add_number);
+ }
+ INSERT_OPERAND (MINUS_A, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case 'B': /* 8-bit signed offset in bit 3 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ min_range = -((OP_MASK_MINUS_B + 1) >> 1);
+ max_range = ((OP_MASK_MINUS_B + 1) >> 1) - 1;
+ if (imm_expr.X_add_number < min_range
+ || imm_expr.X_add_number > max_range)
+ {
+ as_bad (_("immediate not in range %ld..%ld (%ld)"),
+ (long) min_range, (long) max_range,
+ (long) imm_expr.X_add_number);
+ }
+ INSERT_OPERAND (MINUS_B, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
+ case 'F': /* 9-bit signed offset in bit 6 */
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ min_range = -((OP_MASK_MINUS_F + 1) >> 1);
+ max_range = ((OP_MASK_MINUS_F + 1) >> 1) - 1;
+ if (imm_expr.X_add_number < min_range
+ || imm_expr.X_add_number > max_range)
+ {
+ as_bad (_("immediate not in range %ld..%ld (%ld)"),
+ (long) min_range, (long) max_range,
+ (long) imm_expr.X_add_number);
+ }
+ INSERT_OPERAND (MINUS_F, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+ }
+ break;
case '2': /* dsp 2-bit unsigned immediate in bit 11 */
my_getExpression (&imm_expr, s);
@@ -9444,6 +9526,7 @@ do_msbd:
else
break;
+ case 'y': /* Loongson-3A: for offset 0 register */
case 'b': /* base register */
case 'd': /* destination register */
case 's': /* source register */
@@ -9528,6 +9611,9 @@ do_msbd:
case 'E':
INSERT_OPERAND (RT, *ip, regno);
break;
+ case 'y': /* Loongson-3A */
+ INSERT_OPERAND (RY, *ip, regno);
+ break;
case 'x':
/* This case exists because on the r3000 trunc
expands into a macro which requires a gp
@@ -9602,6 +9688,7 @@ do_msbd:
case 'S': /* floating point source register */
case 'T': /* floating point target register */
case 'R': /* floating point source register */
+ case '^': /* Loongson-3A: floating point register */
case 'V':
case 'W':
rtype = RTYPE_FPU;
@@ -9641,6 +9728,10 @@ do_msbd:
case 'X':
INSERT_OPERAND (FD, *ip, regno);
break;
+ /* Loongson-3A */
+ case '^':
+ INSERT_OPERAND (FZ, *ip, regno);
+ break;
case 'V':
case 'S':
case 'Y':
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.70
diff -u -p -r1.70 mips.h
--- include/opcode/mips.h 23 Nov 2010 20:24:32 -0000 1.70
+++ include/opcode/mips.h 26 Nov 2010 06:56:55 -0000
@@ -226,6 +226,18 @@
#define OP_SH_SEQI 6
#define OP_MASK_SEQI 0x3ff
+/* Loongson 3A */
+#define OP_SH_MINUS_A 6
+#define OP_MASK_MINUS_A 0xff
+#define OP_SH_MINUS_B 3
+#define OP_MASK_MINUS_B 0xff
+#define OP_SH_MINUS_F 6
+#define OP_MASK_MINUS_F 0x1ff
+#define OP_SH_RY 0
+#define OP_MASK_RY 0x1f
+#define OP_SH_FZ 0
+#define OP_MASK_FZ 0x1f
+
/* This structure holds information for a particular instruction. */
struct mips_opcode
@@ -430,6 +442,12 @@ struct mips_opcode
#define INSN_WRITE_FPR_S 0x00000010
/* Modifies the floating point register in OP_*_FT. */
#define INSN_WRITE_FPR_T 0x00000020
+/* Loongson-3A: Modifies the general purpose register in OP_*_RY. */
+#define INSN_WRITE_GPR_Y 0x00000009
+/* Loongson-3A: Modifies the floating point register in OP_*_FZ. */
+#define INSN_WRITE_FPR_Z 0x00000090
+/* Loongson-3A: Reads the general purpose register in OP_*_RD. */
+#define INSN_READ_GPR_D 0x0000000c
/* Reads the general purpose register in OP_*_RS. */
#define INSN_READ_GPR_S 0x00000040
/* Reads the general purpose register in OP_*_RT. */
@@ -440,6 +458,11 @@ struct mips_opcode
#define INSN_READ_FPR_T 0x00000200
/* Reads the floating point register in OP_*_FR. */
#define INSN_READ_FPR_R 0x00000400
+/* Loongson-3A: Reads the general purpose register in OP_*_RY. */
+#define INSN_READ_GPR_Y 0x00000030
+/* Loongson-3A: Reads the floating point register in OP_*_FZ. */
+#define INSN_READ_FPR_Z 0x00000900
+
/* Modifies coprocessor condition code. */
#define INSN_WRITE_COND_CODE 0x00000800
/* Reads coprocessor condition code. */
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.82
diff -u -p -r1.82 mips-dis.c
--- opcodes/mips-dis.c 11 Nov 2010 10:23:39 -0000 1.82
+++ opcodes/mips-dis.c 26 Nov 2010 06:56:56 -0000
@@ -834,6 +834,40 @@ print_insn_args (const char *d,
(*info->fprintf_func) (info->stream, "%c", *d);
break;
+ case '-': /* Loongson-3A */
+ /* Extension character; switch for second char. */
+ d++;
+ switch (*d)
+ {
+ case '\0':
+ (*info->fprintf_func) (info->stream,
+ _("# internal error, incomplete extension sequence (-)"));
+ return;
+
+ case 'A': /* 8-bit signed offset in bit 6 */
+ /* Sign extend the offset. */
+ delta = (l >> OP_SH_MINUS_A) & OP_MASK_MINUS_A;
+ if (delta & 0x80)
+ delta |= ~OP_MASK_MINUS_A;
+ (*info->fprintf_func) (info->stream, "%d", delta);
+ break;
+ case 'B': /* 8-bit signed offset in bit 3 */
+ /* Sign extend the offset. */
+ delta = (l >> OP_SH_MINUS_B) & OP_MASK_MINUS_B;
+ if (delta & 0x80)
+ delta |= ~OP_MASK_MINUS_B;
+ (*info->fprintf_func) (info->stream, "%d", delta);
+ break;
+ case 'F': /* 9-bit signed offset in bit 6 */
+ /* Sign extend the offset. */
+ delta = (l >> OP_SH_MINUS_F) & OP_MASK_MINUS_F;
+ if (delta & 0x100)
+ delta |= ~OP_MASK_MINUS_F;
+ (*info->fprintf_func) (info->stream, "%d", delta);
+ break;
+ }
+ break;
+
case '+':
/* Extension character; switch for second char. */
d++;
@@ -1087,6 +1121,11 @@ print_insn_args (const char *d,
(*info->fprintf_func) (info->stream, "%s",
mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
break;
+ /* Loongson-3A */
+ case 'y':
+ (*info->fprintf_func) (info->stream, "%s",
+ mips_gpr_names[(l >> OP_SH_RY) & OP_MASK_RY]);
+ break;
case 'i':
case 'u':
@@ -1199,6 +1238,12 @@ print_insn_args (const char *d,
(l >> OP_SH_CODE19) & OP_MASK_CODE19);
break;
+ /* Loongson-3A */
+ case '^':
+ (*info->fprintf_func) (info->stream, "%s",
+ mips_fpr_names[(l >> OP_SH_FZ) & OP_MASK_FZ]);
+ break;
+
case 'S':
case 'V':
(*info->fprintf_func) (info->stream, "%s",
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.82
diff -u -p -r1.82 mips-opc.c
--- opcodes/mips-opc.c 11 Nov 2010 10:23:39 -0000 1.82
+++ opcodes/mips-opc.c 26 Nov 2010 06:56:57 -0000
@@ -164,6 +164,13 @@
/* MIPS MT ASE support. */
#define MT32 INSN_MT
+/* Loongson-3A support */
+#define WR_y INSN_WRITE_GPR_Y
+#define WR_z INSN_WRITE_FPR_Z
+#define RD_y INSN_READ_GPR_Y
+#define RD_z INSN_READ_FPR_Z
+#define RD_d INSN_READ_GPR_D
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -199,6 +206,76 @@ const struct mips_opcode mips_builtin_op
{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
+/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2
+ instructions. Put them here so that disassembler will find them first.
+ The assemblers uses a hash table based on the instruction name anyhow. */
+{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_d|RD_s, 0, IL3A },
+{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_d|RD_s, 0, IL3A },
+{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
+{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_d|RD_s, 0, IL3A },
+{"gslbgt", "d,b,t", 0xc8000011, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslble", "d,b,t", 0xc8000010, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gsldle", "d,b,t", 0xc8000016, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gsldgt", "d,b,t", 0xc8000017, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslhgt", "d,b,t", 0xc8000013, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslhle", "d,b,t", 0xc8000012, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslwgt", "d,b,t", 0xc8000015, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslwle", "d,b,t", 0xc8000014, 0xfc0007ff, WR_d|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gsgt", "s,t", 0x70000027, 0xfc00ffff, 0, 0, IL3A },
+{"gsle", "s,t", 0x70000026, 0xfc00ffff, 0, 0, IL3A },
+{"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsshgt", "t,b,d", 0xe8000013, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsswle", "t,b,d", 0xe8000014, 0xfc0007ff, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsldlc1", "T,-A(b)", 0xc8000006, 0xfc00c03f, LDD|WR_T|RD_b, 0, IL3A },
+{"gsldrc1", "T,-A(b)", 0xc8000007, 0xfc00c03f, LDD|WR_T|RD_b, 0, IL3A },
+{"gslwlc1", "T,-A(b)", 0xc8000004, 0xfc00c03f, LDD|WR_T|RD_b, 0, IL3A },
+{"gslwrc1", "T,-A(b)", 0xc8000005, 0xfc00c03f, LDD|WR_T|RD_b, 0, IL3A },
+{"gssdlc1", "T,-A(b)", 0xe8000006, 0xfc00c03f, SM|RD_T|RD_b, 0, IL3A },
+{"gssdrc1", "T,-A(b)", 0xe8000007, 0xfc00c03f, SM|RD_T|RD_b, 0, IL3A },
+{"gsswlc1", "T,-A(b)", 0xe8000004, 0xfc00c03f, SM|RD_T|RD_b|RD_CC, 0, IL3A },
+{"gsswrc1", "T,-A(b)", 0xe8000005, 0xfc00c03f, SM|RD_T|RD_b|RD_CC, 0, IL3A },
+{"gslbx", "t,-B(b,d)", 0xd8000000, 0xfc000007, WR_t|RD_b|RD_d|WR_CC|LDD|RD_CC, 0, IL3A },
+{"gsldx", "t,-B(b,d)", 0xd8000003, 0xfc000007, WR_t|RD_b|RD_d|WR_CC|LDD|RD_CC, 0, IL3A },
+{"gslhx", "t,-B(b,d)", 0xd8000001, 0xfc000007, WR_t|RD_b|RD_d|WR_CC|LDD|RD_CC, 0, IL3A },
+{"gslwx", "t,-B(b,d)", 0xd8000002, 0xfc000007, WR_t|RD_b|RD_d|WR_CC|LDD|RD_CC, 0, IL3A },
+{"gssbx", "t,-B(b,d)", 0xf8000000, 0xfc000007, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gssdx", "t,-B(b,d)", 0xf8000003, 0xfc000007, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsshx", "t,-B(b,d)", 0xf8000001, 0xfc000007, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsswx", "t,-B(b,d)", 0xf8000002, 0xfc000007, SM|RD_d|RD_b|RD_t|WR_CC, 0, IL3A },
+{"gsldxc1", "T,-B(b,d)", 0xd8000003, 0xfc000007, WR_T|RD_b|RD_d|WR_CC|LDD|RD_CC, 0, IL3A },
+{"gslwxc1", "T,-B(b,d)", 0xd8000003, 0xfc000007, WR_T|RD_b|RD_d|WR_CC|LDD|RD_CC, 0, IL3A },
+{"gssdxc1", "T,-B(b,d)", 0xf8000007, 0xfc000007, SM|RD_T|RD_b|RD_d|WR_CC, 0, IL3A },
+{"gsswxc1", "T,-B(b,d)", 0xf8000006, 0xfc000007, SM|RD_T|RD_b|RD_d|WR_CC, 0, IL3A },
+{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_D|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_D|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_D|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_D|RD_b|RD_s|WR_CC|LDD, 0, IL3A },
+{"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, SM|RD_T|RD_b|RD_d|WR_CC, 0, IL3A },
+{"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, SM|RD_T|RD_b|RD_d|WR_CC, 0, IL3A },
+{"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, SM|RD_T|RD_b|RD_d|WR_CC, 0, IL3A },
+{"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, SM|RD_T|RD_b|RD_d|WR_CC, 0, IL3A },
+{"gslq", "y,t,-F(b)", 0xc8000020, 0xfc008020, LDD|WR_t|WR_y|RD_b|WR_CC, 0, IL3A },
+{"gssq", "y,t,-F(b)", 0xe8000020, 0xfc008020, SM|WR_t|RD_y|RD_b|RD_CC, 0, IL3A },
+{"gslqc1", "^,T,-F(b)", 0xc8008020, 0xfc008020, LDD|WR_T|WR_z|RD_b|WR_CC, 0, IL3A },
+{"gssqc1", "^,T,-F(b)", 0xe8008020, 0xfc008020, SM|RD_T|RD_z|RD_b|RD_CC, 0, IL3A },
+
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
[not found] ` <87oc96wj7m.fsf@firetop.home>
@ 2010-12-01 5:55 ` Mingming Sun
2010-12-01 21:54 ` Richard Sandiford
0 siblings, 1 reply; 7+ messages in thread
From: Mingming Sun @ 2010-12-01 5:55 UTC (permalink / raw)
To: Mingming Sun, binutils, rdsandiford
[-- Attachment #1: Type: text/plain, Size: 3590 bytes --]
On Wed, Dec 1, 2010 at 6:16 AM, Richard Sandiford
<rdsandiford@googlemail.com> wrote:
> Mingming Sun <mingm.sun@gmail.com> writes:
>> 2010-11-29 Mingming Sun <mingm.sun@gmail.com>
>> gas/ChangeLog
>> * config/tc-mips.c (macro_build): Add loongson3a-specific instructions support.
>> (validate_mips_insn): Likewise.
>> (mips_ip): Likewise.
>>
>> include/ChangeLog
>> * opcode/mips.h: Define OP_SH_MINUS_A, OP_MASK_MINUS_A, OP_SH_MINUS_B,
>> OP_MASK_MINUS_B, OP_SH_MINUS_F, OP_MASK_MINUS_F, OP_SH_RY, OP_MASK_RY,
>> OP_SH_FZ, OP_MASK_FZ, INSN_WRITE_GPR_Y, INSN_WRITE_FPR_Z,
>> INSN_READ_GPR_D, INSN_READ_GPR_Y, INSN_READ_FPR_Z.
>>
>> opcodes/ChangeLog
>> * mips-dis.c (print_insn_args): Add loongson3a-specific instructions support.
>> * mips-opc.c: Define WR_z, RD_y, RD_z, RD_d.
>> (mips_builtin_opcodes): Add loongson3a-specific instructions.
>
> There's a big comment in include/opcode/mips.h that explains what
> the format characters mean, and which ones have been used. You need
> to update that as well.
>
> Is there any need for a new extension character, "-"? Many characters
> in the "+" group are still free, and they aren't set aside for a
> particular purpose. I'd also prefer "+Z" over "^" for the FZ fields.
>
>> @@ -430,6 +442,12 @@ struct mips_opcode
>> #define INSN_WRITE_FPR_S 0x00000010
>> /* Modifies the floating point register in OP_*_FT. */
>> #define INSN_WRITE_FPR_T 0x00000020
>> +/* Loongson-3A: Modifies the general purpose register in OP_*_RY. */
>> +#define INSN_WRITE_GPR_Y 0x00000009
>> +/* Loongson-3A: Modifies the floating point register in OP_*_FZ. */
>> +#define INSN_WRITE_FPR_Z 0x00000090
>> +/* Loongson-3A: Reads the general purpose register in OP_*_RD. */
>> +#define INSN_READ_GPR_D 0x0000000c
>> /* Reads the general purpose register in OP_*_RS. */
>> #define INSN_READ_GPR_S 0x00000040
>> /* Reads the general purpose register in OP_*_RT. */
>> @@ -440,6 +458,11 @@ struct mips_opcode
>> #define INSN_READ_FPR_T 0x00000200
>> /* Reads the floating point register in OP_*_FR. */
>> #define INSN_READ_FPR_R 0x00000400
>> +/* Loongson-3A: Reads the general purpose register in OP_*_RY. */
>> +#define INSN_READ_GPR_Y 0x00000030
>> +/* Loongson-3A: Reads the floating point register in OP_*_FZ. */
>> +#define INSN_READ_FPR_Z 0x00000900
>
> These INSN_*s values are supposed to be bitflags, so (to take an example),
> 0x900 already means "reads the FPR in the FS field and modifies the
> condition codes". You should be using new INSN2_* flags instead.
>
> You should also be checking these flags in tc-mips.c, in the same
> way that existing read and write flags are set. This controls things
> like automatic delay-slot filling. For example, at the moment:
>
> gslq $4,$5,0($6)
> beq $4,$0,1f
> nop
> 1:
>
> produces:
>
> 0: 10800002 beqz a0,0xc
> 4: c8c50024 gslq a0,a1,0(a2)
> 8: 00000000 nop
>
> which looks wrong.
>
> There needs to be some gas testcases too.
>
> Richard
>
Thanks, Richard.
This new patch only adds mul/div instructions support in opcode/mips-opt.c.
I'm checking other problems you've mentioned.
Thanks,
Mingming Sun
2010-12-01 Mingming Sun <mingm.sun@gmail.com>
opcodes/
* mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div instructions.
[-- Attachment #2: patch.txt --]
[-- Type: text/plain, Size: 3306 bytes --]
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.82
diff -u -p -r1.82 mips-opc.c
--- opcodes/mips-opc.c 11 Nov 2010 10:23:39 -0000 1.82
+++ opcodes/mips-opc.c 1 Dec 2010 02:54:33 -0000
@@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_op
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
2010-12-01 5:55 ` Mingming Sun
@ 2010-12-01 21:54 ` Richard Sandiford
2010-12-03 6:49 ` Mingming Sun
0 siblings, 1 reply; 7+ messages in thread
From: Richard Sandiford @ 2010-12-01 21:54 UTC (permalink / raw)
To: Mingming Sun; +Cc: binutils
Mingming Sun <mingm.sun@gmail.com> writes:
> Index: opcodes/mips-opc.c
> ===================================================================
> RCS file: /cvs/src/src/opcodes/mips-opc.c,v
> retrieving revision 1.82
> diff -u -p -r1.82 mips-opc.c
> --- opcodes/mips-opc.c 11 Nov 2010 10:23:39 -0000 1.82
> +++ opcodes/mips-opc.c 1 Dec 2010 02:54:33 -0000
> @@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_op
> /* ST Microelectronics Loongson-2E and -2F. */
> {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
> {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
> +{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
> {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
> {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
[...]
I can see why you listed the read and write flags in the same order as the
operands, but please follow the existing order (RD_s|RD_t|WR_d) instead.
Consistency is more important than logic here :-) Same goes for the
other instructions.
The patch is otherwise OK as far as it goes, but I'm afraid even this
change needs a test in the gas testsuite.
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
2010-12-01 21:54 ` Richard Sandiford
@ 2010-12-03 6:49 ` Mingming Sun
2010-12-07 11:52 ` Richard Sandiford
0 siblings, 1 reply; 7+ messages in thread
From: Mingming Sun @ 2010-12-03 6:49 UTC (permalink / raw)
To: Mingming Sun, binutils, rdsandiford
[-- Attachment #1: Type: text/plain, Size: 1912 bytes --]
On Thu, Dec 2, 2010 at 5:54 AM, Richard Sandiford
<rdsandiford@googlemail.com> wrote:
> Mingming Sun <mingm.sun@gmail.com> writes:
>> Index: opcodes/mips-opc.c
>> ===================================================================
>> RCS file: /cvs/src/src/opcodes/mips-opc.c,v
>> retrieving revision 1.82
>> diff -u -p -r1.82 mips-opc.c
>> --- opcodes/mips-opc.c 11 Nov 2010 10:23:39 -0000 1.82
>> +++ opcodes/mips-opc.c 1 Dec 2010 02:54:33 -0000
>> @@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_op
>> /* ST Microelectronics Loongson-2E and -2F. */
>> {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
>> {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
>> +{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL3A },
>> {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
>> {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
>
> [...]
>
> I can see why you listed the read and write flags in the same order as the
> operands, but please follow the existing order (RD_s|RD_t|WR_d) instead.
> Consistency is more important than logic here :-) Same goes for the
> other instructions.
>
> The patch is otherwise OK as far as it goes, but I'm afraid even this
> change needs a test in the gas testsuite.
>
> Richard
>
Thanks, Richard.
This new patch changes the read and write order of the pinfo.
Also a testsuite is added.
Thanks,
Mingming Sun
2010-12-03 Mingming Sun <mingm.sun@gmail.com>
opcodes/
* mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
fixed point instructions.
gas/testsuite/
* gas/mips/loongson-3a.s, gas/mips/loongson-3a.d: New test.
* gas/mips/mips.exp: Run it.
[-- Attachment #2: new-patch.txt --]
[-- Type: text/plain, Size: 17566 bytes --]
? gas/testsuite/gas/mips/loongson-3a.d
? gas/testsuite/gas/mips/loongson-3a.s
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.175
diff -u -p -r1.175 mips.exp
--- gas/testsuite/gas/mips/mips.exp 13 Nov 2010 11:59:20 -0000 1.175
+++ gas/testsuite/gas/mips/mips.exp 3 Dec 2010 05:35:31 -0000
@@ -912,6 +912,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "loongson-2f-2"
run_dump_test "loongson-2f-3"
+ run_dump_test "loongson-3a"
+
run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
run_list_test_arches "octeon-ill" "" \
[mips_arch_list_matching octeon]
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.82
diff -u -p -r1.82 mips-opc.c
--- opcodes/mips-opc.c 11 Nov 2010 10:23:39 -0000 1.82
+++ opcodes/mips-opc.c 3 Dec 2010 05:35:34 -0000
@@ -207,7 +207,7 @@ const struct mips_opcode mips_builtin_op
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
@@ -227,7 +227,7 @@ const struct mips_opcode mips_builtin_op
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
{"addu", "D,S,T", 0x45800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"addu", "D,S,T", 0x4b00000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
@@ -237,7 +237,7 @@ const struct mips_opcode mips_builtin_op
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
{"and", "D,S,T", 0x47c00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"and", "D,S,T", 0x4bc00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -553,7 +553,7 @@ const struct mips_opcode mips_builtin_op
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
@@ -670,25 +670,25 @@ const struct mips_opcode mips_builtin_op
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsll", "D,S,T", 0x45a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsll", "D,S,T", 0x4b20000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsra", "D,S,T", 0x45e00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsra", "D,S,T", 0x4b60000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
{"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
{"dsub", "D,S,T", 0x45e00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
@@ -902,7 +902,7 @@ const struct mips_opcode mips_builtin_op
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
-{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F },
+{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
@@ -1071,7 +1071,7 @@ const struct mips_opcode mips_builtin_op
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
{"nor", "D,S,T", 0x47a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"nor", "D,S,T", 0x4ba00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1081,7 +1081,7 @@ const struct mips_opcode mips_builtin_op
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
{"or", "D,S,T", 0x45a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"or", "D,S,T", 0x4b20000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1208,7 +1208,7 @@ const struct mips_opcode mips_builtin_op
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
{"seq", "S,T", 0x46a00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"seq", "S,T", 0x4ba0000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"seqi", "t,r,+Q", 0x7000002e, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
@@ -1237,16 +1237,16 @@ const struct mips_opcode mips_builtin_op
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
{"sle", "S,T", 0x46a0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sle", "S,T", 0x4ba0000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
{"sleu", "S,T", 0x4680003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sleu", "S,T", 0x4b80000e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
{"sll", "D,S,T", 0x45800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"sll", "D,S,T", 0x4b00000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1254,13 +1254,13 @@ const struct mips_opcode mips_builtin_op
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
{"slt", "S,T", 0x46a0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"slt", "S,T", 0x4ba0000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
{"sltu", "S,T", 0x4680003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E },
-{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F },
+{"sltu", "S,T", 0x4b80000d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A },
{"sne", "d,v,t", 0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
@@ -1272,13 +1272,13 @@ const struct mips_opcode mips_builtin_op
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
{"sra", "D,S,T", 0x45c00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"sra", "D,S,T", 0x4b40000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
{"srl", "D,S,T", 0x45800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"srl", "D,S,T", 0x4b00000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1288,7 +1288,7 @@ const struct mips_opcode mips_builtin_op
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
{"sub", "D,S,T", 0x45c00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"sub", "D,S,T", 0x4b40000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
@@ -1305,7 +1305,7 @@ const struct mips_opcode mips_builtin_op
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
{"subu", "D,S,T", 0x45800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
-{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F },
+{"subu", "D,S,T", 0x4b00000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
@@ -1423,7 +1423,7 @@ const struct mips_opcode mips_builtin_op
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
+{"xor", "D,S,T", 0x4b800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -1838,28 +1838,40 @@ const struct mips_opcode mips_builtin_op
/* ST Microelectronics Loongson-2E and -2F. */
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmult", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmultu", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmult", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmultu", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdiv", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdivu", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsddiv", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsddivu", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmod", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsmodu", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmod", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
{"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
+{"gsdmodu", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL3A },
{"packsshb", "D,S,T", 0x47400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
{"packsshb", "D,S,T", 0x4b400002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"packsswh", "D,S,T", 0x47200002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
[-- Attachment #3: loongson-3a.s --]
[-- Type: application/octet-stream, Size: 2386 bytes --]
.text
.set noreorder
movz_insns:
movnz $2, $3, $4
integer_insns:
gsmult $2, $3, $4
gsmultu $5, $6, $7
gsdmult $8, $9, $10
gsdmultu $11, $12, $13
gsdiv $14, $15, $16
gsdivu $17, $18, $19
gsddiv $20, $21, $22
gsddivu $23, $24, $25
gsmod $26, $27, $28
gsmodu $29, $30, $31
gsdmod $2, $3, $4
gsdmodu $5, $6, $7
simd_insns:
packsshb $f0, $f1, $f2
packsswh $f3, $f4, $f5
packushb $f6, $f7, $f8
paddb $f9, $f10, $f11
paddh $f12, $f13, $f14
paddw $f15, $f16, $f17
paddd $f18, $f19, $f20
paddsb $f21, $f22, $f23
paddsh $f24, $f25, $f26
paddusb $f27, $f28, $f29
paddush $f0, $f1, $f2
pandn $f3, $f4, $f5
pavgb $f6, $f7, $f8
pavgh $f9, $f10, $f11
pcmpeqb $f12, $f13, $f14
pcmpeqh $f15, $f16, $f17
pcmpeqw $f18, $f19, $f20
pcmpgtb $f21, $f22, $f23
pcmpgth $f24, $f25, $f26
pcmpgtw $f27, $f28, $f29
pextrh $f0, $f1, $f2
pinsrh_0 $f3, $f4, $f5
pinsrh_1 $f6, $f7, $f8
pinsrh_2 $f9, $f10, $f11
pinsrh_3 $f12, $f13, $f14
pmaddhw $f15, $f16, $f17
pmaxsh $f18, $f19, $f20
pmaxub $f21, $f22, $f23
pminsh $f24, $f25, $f26
pminub $f27, $f28, $f29
pmovmskb $f0, $f1
pmulhuh $f2, $f3, $f4
pmulhh $f5, $f6, $f7
pmullh $f8, $f9, $f10
pmuluw $f11, $f12, $f13
pasubub $f14, $f15, $f16
biadd $f17, $f18
pshufh $f19, $f20, $f21
psllh $f22, $f23, $f24
psllw $f25, $f26, $f27
psrah $f28, $f29, $f30
psraw $f0, $f1, $f2
psrlh $f3, $f4, $f5
psrlw $f6, $f7, $f8
psubb $f9, $f10, $f11
psubh $f12, $f13, $f14
psubw $f15, $f16, $f17
psubd $f18, $f19, $f20
psubsb $f21, $f22, $f23
psubsh $f24, $f25, $f26
psubusb $f27, $f28, $f29
psubush $f0, $f1, $f2
punpckhbh $f3, $f4, $f5
punpckhhw $f6, $f7, $f8
punpckhwd $f9, $f10, $f11
punpcklbh $f12, $f13, $f14
punpcklhw $f15, $f16, $f17
punpcklwd $f18, $f19, $f20
fixed_point_insns:
add $f0, $f1, $f2
addu $f3, $f4, $f5
dadd $f6, $f7, $f8
sub $f9, $f10, $f11
subu $f12, $f13, $f14
dsub $f15, $f16, $f17
or $f18, $f19, $f20
sll $f21, $f22, $f23
dsll $f24, $f25, $f26
xor $f27, $f28, $f29
nor $f0, $f1, $f2
and $f3, $f4, $f5
srl $f6, $f7, $f8
dsrl $f9, $f10, $f11
sra $f12, $f13, $f14
dsra $f15, $f16, $f17
sequ $f18, $f19
sltu $f20, $f21
sleu $f22, $f23
seq $f24, $f25
slt $f26, $f27
sle $f28, $f29
[-- Attachment #4: loongson-3a.d --]
[-- Type: application/octet-stream, Size: 3794 bytes --]
#as: -march=loongson3a -mabi=n32
#objdump: -M reg-names=numeric -dr
#name: Loongson-3A tests
.*: file format .*
Disassembly of section .text:
[0-9a-f]+ <movz_insns>:
.*: 0064100b movn \$2,\$3,\$4
[0-9a-f]+ <integer_insns>:
.*: 70641010 gsmult \$2,\$3,\$4
.*: 70c72812 gsmultu \$5,\$6,\$7
.*: 712a4011 gsdmult \$8,\$9,\$10
.*: 718d5813 gsdmultu \$11,\$12,\$13
.*: 71f07014 gsdiv \$14,\$15,\$16
.*: 72538816 gsdivu \$17,\$18,\$19
.*: 72b6a015 gsddiv \$20,\$21,\$22
.*: 7319b817 gsddivu \$23,\$24,\$25
.*: 737cd01c gsmod \$26,\$27,\$28
.*: 73dfe81e gsmodu \$29,\$30,\$31
.*: 7064101d gsdmod \$2,\$3,\$4
.*: 70c7281f gsdmodu \$5,\$6,\$7
[0-9a-f]+ <simd_insns>:
.*: 4b420802 packsshb \$f0,\$f1,\$f2
.*: 4b2520c2 packsswh \$f3,\$f4,\$f5
.*: 4b683982 packushb \$f6,\$f7,\$f8
.*: 4bcb5240 paddb \$f9,\$f10,\$f11
.*: 4b4e6b00 paddh \$f12,\$f13,\$f14
.*: 4b7183c0 paddw \$f15,\$f16,\$f17
.*: 4bf49c80 paddd \$f18,\$f19,\$f20
.*: 4b97b540 paddsb \$f21,\$f22,\$f23
.*: 4b1ace00 paddsh \$f24,\$f25,\$f26
.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29
.*: 4b220800 paddush \$f0,\$f1,\$f2
.*: 4be520c2 pandn \$f3,\$f4,\$f5
.*: 4b283988 pavgb \$f6,\$f7,\$f8
.*: 4b0b5248 pavgh \$f9,\$f10,\$f11
.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14
.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17
.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20
.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23
.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26
.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29
.*: 4b42080e pextrh \$f0,\$f1,\$f2
.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5
.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8
.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11
.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14
.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17
.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20
.*: 4b97b548 pmaxub \$f21,\$f22,\$f23
.*: 4b7ace08 pminsh \$f24,\$f25,\$f26
.*: 4bbde6c8 pminub \$f27,\$f28,\$f29
.*: 4ba0080f pmovmskb \$f0,\$f1
.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4
.*: 4b67314a pmulhh \$f5,\$f6,\$f7
.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10
.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13
.*: 4b307b8d pasubub \$f14,\$f15,\$f16
.*: 4b80944f biadd \$f17,\$f18
.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21
.*: 4b38bd8a psllh \$f22,\$f23,\$f24
.*: 4b1bd64a psllw \$f25,\$f26,\$f27
.*: 4b7eef0b psrah \$f28,\$f29,\$f30
.*: 4b42080b psraw \$f0,\$f1,\$f2
.*: 4b2520cb psrlh \$f3,\$f4,\$f5
.*: 4b08398b psrlw \$f6,\$f7,\$f8
.*: 4bcb5241 psubb \$f9,\$f10,\$f11
.*: 4b4e6b01 psubh \$f12,\$f13,\$f14
.*: 4b7183c1 psubw \$f15,\$f16,\$f17
.*: 4bf49c81 psubd \$f18,\$f19,\$f20
.*: 4b97b541 psubsb \$f21,\$f22,\$f23
.*: 4b1ace01 psubsh \$f24,\$f25,\$f26
.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29
.*: 4b220801 psubush \$f0,\$f1,\$f2
.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5
.*: 4b283983 punpckhhw \$f6,\$f7,\$f8
.*: 4bab524b punpckhwd \$f9,\$f10,\$f11
.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14
.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17
.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20
[0-9a-f]+ <fixed_point_insns>:
.*: 4b42080c add \$f0,\$f1,\$f2
.*: 4b0520cc addu \$f3,\$f4,\$f5
.*: 4b68398c dadd \$f6,\$f7,\$f8
.*: 4b4b524d sub \$f9,\$f10,\$f11
.*: 4b0e6b0d subu \$f12,\$f13,\$f14
.*: 4b7183cd dsub \$f15,\$f16,\$f17
.*: 4b349c8c or \$f18,\$f19,\$f20
.*: 4b17b54e sll \$f21,\$f22,\$f23
.*: 4b3ace0e dsll \$f24,\$f25,\$f26
.*: 4b9de6c2 xor \$f27,\$f28,\$f29
.*: 4ba20802 nor \$f0,\$f1,\$f2
.*: 4bc520c2 and \$f3,\$f4,\$f5
.*: 4b08398f srl \$f6,\$f7,\$f8
.*: 4b2b524f dsrl \$f9,\$f10,\$f11
.*: 4b4e6b0f sra \$f12,\$f13,\$f14
.*: 4b7183cf dsra \$f15,\$f16,\$f17
.*: 4b93900c sequ \$f18,\$f19
.*: 4b95a00d sltu \$f20,\$f21
.*: 4b97b00e sleu \$f22,\$f23
.*: 4bb9c00c seq \$f24,\$f25
.*: 4bbbd00d slt \$f26,\$f27
.*: 4bbde00e sle \$f28,\$f29
#pass
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
2010-12-03 6:49 ` Mingming Sun
@ 2010-12-07 11:52 ` Richard Sandiford
2010-12-10 10:50 ` Mingjie Xing
0 siblings, 1 reply; 7+ messages in thread
From: Richard Sandiford @ 2010-12-07 11:52 UTC (permalink / raw)
To: Mingming Sun; +Cc: binutils
Thanks, this looks good.
Mingming Sun <mingm.sun@gmail.com> writes:
> 2010-12-03 Mingming Sun <mingm.sun@gmail.com>
> opcodes/
> * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
> fixed point instructions.
It might just be your mailer mangling things, but the formatting should be:
* mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
fixed point instructions.
OK with that change.
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
2010-12-07 11:52 ` Richard Sandiford
@ 2010-12-10 10:50 ` Mingjie Xing
2010-12-11 10:49 ` Richard Sandiford
0 siblings, 1 reply; 7+ messages in thread
From: Mingjie Xing @ 2010-12-10 10:50 UTC (permalink / raw)
To: Mingming Sun, binutils, rdsandiford
2010/12/7 Richard Sandiford <rdsandiford@googlemail.com>:
> Thanks, this looks good.
>
> Mingming Sun <mingm.sun@gmail.com> writes:
>> 2010-12-03 Mingming Sun <mingm.sun@gmail.com>
>> opcodes/
>> * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
>> fixed point instructions.
>
> It might just be your mailer mangling things, but the formatting should be:
>
> * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
> fixed point instructions.
>
> OK with that change.
>
> Richard
>
Hello,
Could anyone help check this patch in since it has get approval?
Thanks,
Mingjie
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions
2010-12-10 10:50 ` Mingjie Xing
@ 2010-12-11 10:49 ` Richard Sandiford
0 siblings, 0 replies; 7+ messages in thread
From: Richard Sandiford @ 2010-12-11 10:49 UTC (permalink / raw)
To: Mingjie Xing; +Cc: Mingming Sun, binutils
Mingjie Xing <mingjie.xing@gmail.com> writes:
> 2010/12/7 Richard Sandiford <rdsandiford@googlemail.com>:
>> Thanks, this looks good.
>>
>> Mingming Sun <mingm.sun@gmail.com> writes:
>>> 2010-12-03 Mingming Sun <mingm.sun@gmail.com>
>>> opcodes/
>>> * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
>>> fixed point instructions.
>>
>> It might just be your mailer mangling things, but the formatting should be:
>>
>> * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and
>> fixed point instructions.
>>
>> OK with that change.
>>
>> Richard
>>
>
> Hello,
>
> Could anyone help check this patch in since it has get approval?
Oops, sorry, I forgot that Mingming didn't have write access yet.
Now applied. I also changed the test abi from n32 to o64 so that
the tests run on a wider range of targets.
Richard
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2010-12-11 10:49 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-11-29 11:58 [PATCH MIPS][LS3A] Add Loongson3A mul/div instructions Mingming Sun
[not found] ` <87oc96wj7m.fsf@firetop.home>
2010-12-01 5:55 ` Mingming Sun
2010-12-01 21:54 ` Richard Sandiford
2010-12-03 6:49 ` Mingming Sun
2010-12-07 11:52 ` Richard Sandiford
2010-12-10 10:50 ` Mingjie Xing
2010-12-11 10:49 ` Richard Sandiford
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