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From: Andrew Burgess <aburgess@redhat.com>
To: Nelson Chu <nelson@rivosinc.com>
Cc: binutils@sourceware.org
Subject: Re: [PATCH] opcodes/riscv: style csr names as registers
Date: Tue, 04 Oct 2022 09:53:00 +0100	[thread overview]
Message-ID: <87zgecezrn.fsf@redhat.com> (raw)
In-Reply-To: <CAPpQWtDENj1hhVBkFnWW-_r8Ze4tOKEH0eA-gVJz2iapUgT_ZA@mail.gmail.com>

Nelson Chu <nelson@rivosinc.com> writes:

> Please commit, thanks.
>

Pushed.

Thanks,
Andrew

> Nelson
>
> On Mon, Oct 3, 2022 at 6:14 PM Andrew Burgess via Binutils
> <binutils@sourceware.org> wrote:
>>
>> While reviewing another patch I noticed that RISC-V CSR names are
>> given the text style, not the register style.  This patch fixes this
>> mistake.
>> ---
>>  opcodes/riscv-dis.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
>> index 6ac69490b78..031c19334fa 100644
>> --- a/opcodes/riscv-dis.c
>> +++ b/opcodes/riscv-dis.c
>> @@ -547,7 +547,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>>               }
>>
>>             if (riscv_csr_hash[csr] != NULL)
>> -             print (info->stream, dis_style_text, "%s", riscv_csr_hash[csr]);
>> +             print (info->stream, dis_style_register, "%s",
>> +                    riscv_csr_hash[csr]);
>>             else
>>               print (info->stream, dis_style_text, "0x%x", csr);
>>             break;
>> --
>> 2.25.4
>>


      reply	other threads:[~2022-10-04  8:53 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-03 10:13 Andrew Burgess
2022-10-03 10:52 ` Tsukasa OI
2022-10-04  1:10 ` Nelson Chu
2022-10-04  8:53   ` Andrew Burgess [this message]

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