From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5416 invoked by alias); 12 Aug 2012 18:32:53 -0000 Received: (qmail 5406 invoked by uid 22791); 12 Aug 2012 18:32:52 -0000 X-SWARE-Spam-Status: No, hits=-4.2 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE X-Spam-Check-By: sourceware.org Received: from mail-wi0-f177.google.com (HELO mail-wi0-f177.google.com) (209.85.212.177) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 12 Aug 2012 18:32:39 +0000 Received: by wibhn17 with SMTP id hn17so1517819wib.12 for ; Sun, 12 Aug 2012 11:32:37 -0700 (PDT) Received: by 10.216.144.234 with SMTP id n84mr4996362wej.78.1344796357400; Sun, 12 Aug 2012 11:32:37 -0700 (PDT) Received: from localhost ([2.26.188.227]) by mx.google.com with ESMTPS id t7sm17164790wix.6.2012.08.12.11.32.34 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 12 Aug 2012 11:32:35 -0700 (PDT) From: Richard Sandiford To: "Maciej W. Rozycki" Mail-Followup-To: "Maciej W. Rozycki" ,David Daney , Andrew Pinski , , rdsandiford@googlemail.com Cc: David Daney , Andrew Pinski , Subject: Re: [PATCH] MIPS: Opcode membership proposal References: <87obway4f5.fsf@firetop.home> Date: Sun, 12 Aug 2012 18:33:00 -0000 In-Reply-To: (Maciej W. Rozycki's message of "Fri, 10 Aug 2012 12:07:11 +0100") Message-ID: <87zk60t0zd.fsf@talisman.home> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2012-08/txt/msg00205.txt.bz2 "Maciej W. Rozycki" writes: > On Thu, 17 Nov 2011, Richard Sandiford wrote: > >> > @@ -830,37 +833,38 @@ static const unsigned int mips_isa_table >> > ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to >> > test, or zero if no CPU specific ISA test is desired. */ >> > >> > -#define OPCODE_IS_MEMBER(insn, isa, cpu) \ >> > - (((isa & INSN_ISA_MASK) != 0 \ >> > - && ((insn)->membership & INSN_ISA_MASK) != 0 \ >> > - && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \ >> > - (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \ >> > - || ((isa & ~INSN_ISA_MASK) \ >> > - & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \ >> > - || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ >> > - || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ >> > - || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ >> > - || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ >> > - || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ >> > - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ >> > - || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \ >> > - || cpu == CPU_R16000) \ >> > - && ((insn)->membership & INSN_10000) != 0) \ >> > - || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ >> > - || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ >> > - || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ >> > - || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ >> > - || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ >> > - || (cpu == CPU_LOONGSON_2E \ >> > - && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ >> > - || (cpu == CPU_LOONGSON_2F \ >> > - && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ >> > - || (cpu == CPU_LOONGSON_3A \ >> > - && ((insn)->membership & INSN_LOONGSON_3A) != 0) \ >> > - || (cpu == CPU_OCTEON \ >> > - && ((insn)->membership & INSN_OCTEON) != 0) \ >> > - || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ >> > - || 0) /* Please keep this term for easier source merging. */ >> > +#define OPCODE_IS_MEMBER(insn, isa, cpu) \ >> > + ((((isa & INSN_ISA_MASK) != 0 \ >> > + && ((insn)->membership & INSN_ISA_MASK) != 0 \ >> > + && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \ >> > + (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \ >> > + || ((isa & ~INSN_ISA_MASK) \ >> > + & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \ >> > + || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ >> > + || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ >> > + || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ >> > + || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ >> > + || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ >> > + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ >> > + || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \ >> > + || cpu == CPU_R16000) \ >> > + && ((insn)->membership & INSN_10000) != 0) \ >> > + || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ >> > + || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ >> > + || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ >> > + || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ >> > + || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ >> > + || (cpu == CPU_LOONGSON_2E \ >> > + && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ >> > + || (cpu == CPU_LOONGSON_2F \ >> > + && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ >> > + || (cpu == CPU_LOONGSON_3A \ >> > + && ((insn)->membership & INSN_LOONGSON_3A) != 0) \ >> > + || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \ >> > + || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ >> > + || 0) /* Please keep this term for easier source merging. */ \ >> > + && ((cpu != CPU_OCTEON || ((insn)->exclusions & CPU_OCTEON) == 0) \ >> >> Looks like a typo for "((insn)->exclusions & INSN_OCTEON) == 0". > > Hmm, where's the typo? That's supposed to be true as long as the CPU is > other than Octeon or the Octeon exclusion bit is zero. Did I get that > wrong? The typo is in the last line I quoted: >> > + && ((cpu != CPU_OCTEON || ((insn)->exclusions & CPU_OCTEON) == 0) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ CPU_OCTEON is an enum value (6501), not a bitmask value. As I say, it looked like it should be "((insn)->exclusions & INSN_OCTEON) == 0" instead. Patch is OK. Richard