From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 03A53385C335; Tue, 4 Oct 2022 08:59:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 03A53385C335 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 4294A300089; Tue, 4 Oct 2022 08:59:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1664873982; bh=10RJpob7TsEpqZgz/da2hq7jdcBrovdJT3P2jfK5qUs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=ofsnP8EsHWWcwcGbBZMUSI3PmmHkVRFMTeFB5+tW0nCK2T8eI39h7vpe7w4446kSa +WH1LB75UYE5hX9RN6zPeLNPuf7ZGUGYX8BlQalmKqBsv4wyw36YkuBNcjUI7Soi+o AOmTeLTgOBLSy4t9sBxil+TdQVzFCar8bDIX15BE= From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt , Andrew Burgess , Jan Beulich Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH 2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction Date: Tue, 4 Oct 2022 08:59:08 +0000 Message-Id: <89612fe01d902007bf84a7dfb0df5f85d5c166e4.1664873933.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,KAM_MANYTO,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Because riscv_insn_length started to support instructions up to 176-bit, we need to increase packet buffer size to 176-bit in size. Note that this change will make the result of riscv_insn::fetch_instruction partial when the instruction is longer than 64-bits. To really support instructions longer than 64-bit, we need something more. --- gdb/riscv-tdep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 47d8f9e601b..99307bd2de1 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr, int *len) { enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); - gdb_byte buf[8]; + gdb_byte buf[22]; int instlen, status; /* All insns are at least 16 bits. */ -- 2.34.1