From: "Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>
To: binutils@sourceware.org
Subject: [PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh
Date: Wed, 01 May 2019 17:30:00 -0000 [thread overview]
Message-ID: <8a75e8e1-7415-92d7-e715-23d0180e64b6@arm.com> (raw)
In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com>
[-- Attachment #1: Type: text/plain, Size: 700 bytes --]
(resending this one because I forgot to change the subject so its easier
to find, ignore the duplicate one!)
Hi,
This patch adds support for MVE instructions VQDMLADH, VQRDMLADH,
VQDMLSDH, and VQRDMLSDH.
gas/ChangeLog:
2019-05-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
[-- Attachment #2: 27.patch --]
[-- Type: text/x-patch, Size: 15386 bytes --]
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b5c263688134bcd733c5ba8f93fe003268859abd..abe37b72eacd9c2b4ea2fae113dcd9ab339cb2f5 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -17308,6 +17308,28 @@ do_mve_vmulh (void)
mve_encode_qqq (et.type == NT_unsigned, et.size);
}
+
+static void
+do_mve_vqdmladh (void)
+{
+ enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ if (et.size == 32
+ && (inst.operands[0].reg == inst.operands[1].reg
+ || inst.operands[0].reg == inst.operands[2].reg))
+ as_tsktsk (BAD_MVE_SRCDEST);
+
+ mve_encode_qqq (0, et.size);
+}
+
+
static void
do_mve_vmull (void)
{
@@ -24746,6 +24768,15 @@ static const struct asm_opcode insns[] =
mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
+ mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+ mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
+
#undef THUMB_VARIANT
#define THUMB_VARIANT & mve_fp_ext
mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.d b/gas/testsuite/gas/arm/mve-vqdmladh-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..5d37855f075011e8c19deab4e42007cb9e15ad3f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQDMLADH and VQRDMLADH instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqdmladh-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.l b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..96057b8daf64b113188c4b1411372d71d4606f97
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqdmladh.u32 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqdmladh.s64 q0,q1,q2'
+[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:14: Error: bad type in SIMD instruction -- `vqdmladhx.u32 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqdmladhx.s64 q0,q1,q2'
+[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmladh.u32 q0,q1,q2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmladh.s64 q0,q1,q2'
+[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmladhx.u32 q0,q1,q2'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmladhx.s64 q0,q1,q2'
+[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:32: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:34: Error: syntax error -- `vqdmladheq.s32 q0,q1,q2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladht.s32 q0,q1,q2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmladh.s32 q0,q1,q2'
+[^:]*:39: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqdmladhxeq.s32 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmladhxt.s32 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmladhx.s32 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:48: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqrdmladheq.s32 q0,q1,q2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladht.s32 q0,q1,q2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmladh.s32 q0,q1,q2'
+[^:]*:55: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:56: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:58: Error: syntax error -- `vqrdmladhxeq.s32 q0,q1,q2'
+[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmladhxt.s32 q0,q1,q2'
+[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmladhx.s32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqdmladh-bad.s b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..7cedb3934b7247e336695caddd792509099073fd
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmladh-bad.s
@@ -0,0 +1,61 @@
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqdmladh.u32 q0, q1, q2
+vqdmladh.s64 q0, q1, q2
+vqdmladh.s32 q0, q0, q2
+vqdmladh.s32 q0, q1, q0
+vqdmladhx.u32 q0, q1, q2
+vqdmladhx.s64 q0, q1, q2
+vqdmladhx.s32 q0, q0, q2
+vqdmladhx.s32 q0, q1, q0
+vqrdmladh.u32 q0, q1, q2
+vqrdmladh.s64 q0, q1, q2
+vqrdmladh.s32 q0, q0, q2
+vqrdmladh.s32 q0, q1, q0
+vqrdmladhx.u32 q0, q1, q2
+vqrdmladhx.s64 q0, q1, q2
+vqrdmladhx.s32 q0, q0, q2
+vqrdmladhx.s32 q0, q1, q0
+cond vqdmladh
+cond vqdmladhx
+cond vqrdmladh
+cond vqrdmladhx
+it eq
+vqdmladheq.s32 q0, q1, q2
+vqdmladheq.s32 q0, q1, q2
+vpst
+vqdmladheq.s32 q0, q1, q2
+vqdmladht.s32 q0, q1, q2
+vpst
+vqdmladh.s32 q0, q1, q2
+it eq
+vqdmladhxeq.s32 q0, q1, q2
+vqdmladhxeq.s32 q0, q1, q2
+vpst
+vqdmladhxeq.s32 q0, q1, q2
+vqdmladhxt.s32 q0, q1, q2
+vpst
+vqdmladhx.s32 q0, q1, q2
+it eq
+vqrdmladheq.s32 q0, q1, q2
+vqrdmladheq.s32 q0, q1, q2
+vpst
+vqrdmladheq.s32 q0, q1, q2
+vqrdmladht.s32 q0, q1, q2
+vpst
+vqrdmladh.s32 q0, q1, q2
+it eq
+vqrdmladhxeq.s32 q0, q1, q2
+vqrdmladhxeq.s32 q0, q1, q2
+vpst
+vqrdmladhxeq.s32 q0, q1, q2
+vqrdmladhxt.s32 q0, q1, q2
+vpst
+vqrdmladhx.s32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..6da0050fa526bf150830e1f70ee41b6df1413dd0
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQDMLSDH and VQRDMLSDH instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqdmlsdh-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..465476ccc1377d71aea25e42154cb87c6ac9e863
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqdmlsdh.u32 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqdmlsdh.s64 q0,q1,q2'
+[^:]*:12: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:13: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:14: Error: bad type in SIMD instruction -- `vqdmlsdhx.u32 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqdmlsdhx.s64 q0,q1,q2'
+[^:]*:16: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:17: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:18: Error: bad type in SIMD instruction -- `vqrdmlsdh.u32 q0,q1,q2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqrdmlsdh.s64 q0,q1,q2'
+[^:]*:20: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:21: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:22: Error: bad type in SIMD instruction -- `vqrdmlsdhx.u32 q0,q1,q2'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqrdmlsdhx.s64 q0,q1,q2'
+[^:]*:24: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:25: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:32: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:34: Error: syntax error -- `vqdmlsdheq.s32 q0,q1,q2'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdht.s32 q0,q1,q2'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vqdmlsdh.s32 q0,q1,q2'
+[^:]*:39: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:40: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmlsdhxt.s32 q0,q1,q2'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vqdmlsdhx.s32 q0,q1,q2'
+[^:]*:47: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:48: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqrdmlsdheq.s32 q0,q1,q2'
+[^:]*:51: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdht.s32 q0,q1,q2'
+[^:]*:53: Error: instruction missing MVE vector predication code -- `vqrdmlsdh.s32 q0,q1,q2'
+[^:]*:55: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:56: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:58: Error: syntax error -- `vqrdmlsdhxeq.s32 q0,q1,q2'
+[^:]*:59: Error: vector predicated instruction should be in VPT/VPST block -- `vqrdmlsdhxt.s32 q0,q1,q2'
+[^:]*:61: Error: instruction missing MVE vector predication code -- `vqrdmlsdhx.s32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..4c047a9373aa4b2e6195f0de932117becefde092
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmlsdh-bad.s
@@ -0,0 +1,61 @@
+.macro cond op
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, q2
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqdmlsdh.u32 q0, q1, q2
+vqdmlsdh.s64 q0, q1, q2
+vqdmlsdh.s32 q0, q0, q2
+vqdmlsdh.s32 q0, q1, q0
+vqdmlsdhx.u32 q0, q1, q2
+vqdmlsdhx.s64 q0, q1, q2
+vqdmlsdhx.s32 q0, q0, q2
+vqdmlsdhx.s32 q0, q1, q0
+vqrdmlsdh.u32 q0, q1, q2
+vqrdmlsdh.s64 q0, q1, q2
+vqrdmlsdh.s32 q0, q0, q2
+vqrdmlsdh.s32 q0, q1, q0
+vqrdmlsdhx.u32 q0, q1, q2
+vqrdmlsdhx.s64 q0, q1, q2
+vqrdmlsdhx.s32 q0, q0, q2
+vqrdmlsdhx.s32 q0, q1, q0
+cond vqdmlsdh
+cond vqdmlsdhx
+cond vqrdmlsdh
+cond vqrdmlsdhx
+it eq
+vqdmlsdheq.s32 q0, q1, q2
+vqdmlsdheq.s32 q0, q1, q2
+vpst
+vqdmlsdheq.s32 q0, q1, q2
+vqdmlsdht.s32 q0, q1, q2
+vpst
+vqdmlsdh.s32 q0, q1, q2
+it eq
+vqdmlsdhxeq.s32 q0, q1, q2
+vqdmlsdhxeq.s32 q0, q1, q2
+vpst
+vqdmlsdhxeq.s32 q0, q1, q2
+vqdmlsdhxt.s32 q0, q1, q2
+vpst
+vqdmlsdhx.s32 q0, q1, q2
+it eq
+vqrdmlsdheq.s32 q0, q1, q2
+vqrdmlsdheq.s32 q0, q1, q2
+vpst
+vqrdmlsdheq.s32 q0, q1, q2
+vqrdmlsdht.s32 q0, q1, q2
+vpst
+vqrdmlsdh.s32 q0, q1, q2
+it eq
+vqrdmlsdhxeq.s32 q0, q1, q2
+vqrdmlsdhxeq.s32 q0, q1, q2
+vpst
+vqrdmlsdhxeq.s32 q0, q1, q2
+vqrdmlsdhxt.s32 q0, q1, q2
+vpst
+vqrdmlsdhx.s32 q0, q1, q2
next prev parent reply other threads:[~2019-05-01 17:30 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-01 16:51 [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 16:53 ` [PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp Andre Vieira (lists)
2019-05-01 16:55 ` [PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd Andre Vieira (lists)
2019-05-02 10:56 ` Nick Clifton
2019-05-13 13:42 ` Andre Vieira (lists)
[not found] ` <98e50dc4-7b0e-d727-0c20-34711be86533@redhat.com>
[not found] ` <4e56a5f3-bcde-f4cd-21d4-35cc3f11b5e8@arm.com>
2019-05-14 16:53 ` Nick Clifton
2019-05-14 16:54 ` Nick Clifton
2019-05-01 16:56 ` [PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg Andre Vieira (lists)
2019-05-01 16:57 ` [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav Andre Vieira (lists)
2019-05-01 16:59 ` [PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} Andre Vieira (lists)
2019-05-01 17:00 ` [PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} Andre Vieira (lists)
2019-05-01 17:01 ` [PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr Andre Vieira (lists)
2019-05-01 17:02 ` [PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt Andre Vieira (lists)
2019-05-01 17:03 ` [PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov Andre Vieira (lists)
2019-05-01 17:05 ` [PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr Andre Vieira (lists)
2019-05-01 17:06 ` [PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv Andre Vieira (lists)
2019-05-01 17:07 ` [PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor Andre Vieira (lists)
2019-05-01 17:08 ` [PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas Andre Vieira (lists)
2019-05-01 17:09 ` [PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:11 ` [PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a] Andre Vieira (lists)
2019-05-01 17:12 ` [PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav Andre Vieira (lists)
2019-05-01 17:13 ` [PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub Andre Vieira (lists)
2019-05-01 17:15 ` [PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh Andre Vieira (lists)
2019-05-01 17:16 ` [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg Andre Vieira (lists)
2019-05-01 17:17 ` [PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel Andre Vieira (lists)
2019-05-01 17:18 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:19 ` [PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:30 ` Andre Vieira (lists) [this message]
2019-05-01 17:31 ` [PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] Andre Vieira (lists)
2019-05-01 17:32 ` [PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl Andre Vieira (lists)
2019-05-01 17:33 ` [PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 Andre Vieira (lists)
2019-05-01 17:34 ` [PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp Andre Vieira (lists)
2019-05-01 17:36 ` [PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 38/57][Arm][OBJDUMP] Disable the use of MVE reserved coproc numbers in coprocessor instructions Andre Vieira (lists)
2019-05-01 17:38 ` [PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions Andre Vieira (lists)
2019-05-01 17:39 ` [PATCH 39/57][Arm][OBJDUMP] Add support for MVE instructions: vpt, vpst and vcmp Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 41/57][Arm][OBJDUMP] Add support for MVE instructions: vld[24] and vst[24] Andre Vieira (lists)
2019-05-01 17:40 ` [PATCH 40/57][Arm][OBJDUMP] Add support for MVE instructions: vdup, veor, vfma, vfms, vhadd, vhsub and vrhadd Andre Vieira (lists)
2019-05-01 17:41 ` [PATCH 42/57][Arm][OBJDUMP] Add support for MVE instructions: vldr[bhw] and vstr[bhw] Andre Vieira (lists)
2019-05-01 17:42 ` [PATCH 43/57][Arm][OBJDUMP] Add support for MVE instructions: scatter stores and gather loads Andre Vieira (lists)
2019-05-01 17:43 ` [PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrint Andre Vieira (lists)
2019-05-02 9:54 ` Nick Clifton
2019-05-13 13:38 ` Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 45/57][Arm][OBJDUMP] Add support for MVE instructions: vmov, vmvn, vorr, vorn, vmovx and vbic Andre Vieira (lists)
2019-05-01 17:44 ` [PATCH 46/57][Arm][OBJDUMP] Add support for MVE instructions: vmovl, vmull, vqdmull, vqmovn, vqmovun and vmovn Andre Vieira (lists)
2019-05-01 17:45 ` [PATCH 47/57][Arm][OBJDUMP] Add support for MVE instructions: vaddv, vmlaldav, vmladav, vmlas, vrmlsldavh, vmlsldav, vmlsdav, vrmlaldavh, vqdmlah, vqrdmlash, vqrdmlash, vqdmlsdh, vqrdmlsdh, vqdmulh and vqrdmulh Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 48/57][Arm][OBJDUMP] Add support for MVE instructions: vddup, vdwdup, vidup and viwdup Andre Vieira (lists)
2019-05-01 17:46 ` [PATCH 49/57][Arm][OBJDUMP] Add support for MVE complex number instructions Andre Vieira (lists)
2019-05-01 17:47 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp Andre Vieira (lists)
2019-05-01 17:48 ` [PATCH 52/57][Arm][OBJDUMP] Add support for MVE instructions: vadc, vabav, vabd, vabs, vadd, vsbc and vsub Andre Vieira (lists)
2019-05-01 17:49 ` [PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls, vclz and vctp Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 55/57][Arm][OBJDUMP] Add support for MVE instructions: vmul, vmulh, vrmulh and vneg Andre Vieira (lists)
2019-05-01 17:50 ` [PATCH 54/57][Arm][OBJDUMP] Add support for MVE instructions: vmax(a), vmax(a)v, vmaxnm(a), vmaxnm(a)v, vmin(a), vmin(a)v, vminnm(a), vminnm(a)v and vmla Andre Vieira (lists)
2019-05-01 17:51 ` [PATCH 56/57][Arm][OBJDUMP] Add support for MVE instructions: vpnot, vpsel, vqabs, vqadd, vqsub, vqneg and vrev Andre Vieira (lists)
2019-05-01 18:23 ` [PATCH 57/57][Arm][GAS] MVE Tests Andre Vieira (lists)
2019-05-01 18:24 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-01 18:25 ` Andre Vieira (lists)
2019-05-02 10:03 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
2019-05-02 10:18 ` Nick Clifton
2019-05-13 13:39 ` [PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS Andre Vieira (lists)
2019-05-02 13:39 ` [PATCH 0/57][Arm][binutils]: Add support for Armv8.1-M Mainline MVE instructions Nick Clifton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8a75e8e1-7415-92d7-e715-23d0180e64b6@arm.com \
--to=andre.simoesdiasvieira@arm.com \
--cc=binutils@sourceware.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).