From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) by sourceware.org (Postfix) with ESMTPS id AE69B3858D37 for ; Thu, 30 Nov 2023 19:08:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AE69B3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xen0n.name ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AE69B3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.28.160.31 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701371338; cv=none; b=ppzuTzDvnCye8wwglu1lLuKP8L9VZvC1xiI+cbNPMpQM6uqKTltDh5tX6P7OinvJoYbi5C8pFwALPLh2/r9bibzNYz7mWq6d9321f0yO0CMn73WqCErOm4LZwW72Qg3Gt71v2KBLkjGJ6f4UeTjiTDl1/UVwCqQZCq2AA31N8V8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701371338; c=relaxed/simple; bh=ugOsXyg3b2078s0HJgcWMu0YNWnQXQtCMDNw6O/xpdw=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From; b=AdePGBI4vh2Sv5FzMlLwrZEJumR9fkLCsBvCSBtBh9LaYW1t3hX+fvmC4wbByRLAVQ47/M3+wwYSaAM0lCUWFdQhriU8oH/qHn3DcPqMaN1kxepXY5VyDW79u5iTRxWtvimvMCRxjk1EuRV63bExFCiR5jQnPTNJLXfArM5y4PY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1701371333; bh=ugOsXyg3b2078s0HJgcWMu0YNWnQXQtCMDNw6O/xpdw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=wQD9bolGSONc+8Gt9+pCtzfy7wYp2BzCFXzYW3HjdAWMJH5oNifftSYDDshmi3Yen 8qYf6Eih8n1hJuzqV4qrlq8Ph5KxWX7Yz9sBPH9oU8NTZjCAsWMK7JfeODQHffOzbm 0BJPK7OUGV05ijYDdt+m9iHl7GrSqaN4OhLg/+5I= Received: from [IPV6:240e:388:8d18:c00:7323:7fde:a97f:4d87] (unknown [IPv6:240e:388:8d18:c00:7323:7fde:a97f:4d87]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 49ED26006F; Fri, 1 Dec 2023 03:08:53 +0800 (CST) Message-ID: <8c14f84b-5c80-4f9f-863f-8e876c875e89@xen0n.name> Date: Fri, 1 Dec 2023 03:08:52 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] LoongArch: Add call and tail pseudo instructions Content-Language: en-US To: Xi Ruoyao , mengqinggang , binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, i.swmail@xen0n.name, maskray@google.com, cailulu@loongson.cn, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn References: <20231130111328.3236602-1-mengqinggang@loongson.cn> <20231130111328.3236602-3-mengqinggang@loongson.cn> From: WANG Xuerui In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 12/1/23 00:10, Xi Ruoyao wrote: > I'd not use a plain "call" or "tail" as the pseudo name. The problem is > people not very familiar with LoongArch may use them instead of "bl" or > "b" everywhere and regress the code. > > Esp. the programmers know some RISC-V: in Aug 28 we've noticed several > RISC-V developers were attending Loongson user conference and they may > contribute some LoongArch code too in the future. In RISC-V assembly > call/tail are aliases of jal with rd = ra/r0. > > Maybe "call_medium"? "call_36"? "call_far"? > > Or if we can relax call/tail into b/bl it would be even better. I'd suggest making "call"/"tail" context-dependent and/or relaxable, and maybe providing unambiguous "{call,tail}.{16,36}" for explicit control. > > On Thu, 2023-11-30 at 19:13 +0800, mengqinggang wrote: >> --- >>  gas/testsuite/gas/loongarch/medium-call.d   | 10 ++++++++-- >>  gas/testsuite/gas/loongarch/medium-call.s   |  2 ++ >>  ld/testsuite/ld-loongarch-elf/medium-call.s |  2 ++ >>  opcodes/loongarch-opc.c                     | 11 +++++++++++ >>  4 files changed, 23 insertions(+), 2 deletions(-) >> >> diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d >> index 4183818cb4f..3491760b96a 100644 >> --- a/gas/testsuite/gas/loongarch/medium-call.d >> +++ b/gas/testsuite/gas/loongarch/medium-call.d >> @@ -10,6 +10,12 @@ Disassembly of section .text: >>  [  ]+0:[  ]+1e000001[  ]+pcaddu18i[  ]+\$ra, 0 >>  [  ]+0: R_LARCH_CALL36[  ]+a >>  [  ]+4:[  ]+4c000021[  ]+jirl[  ]+\$ra, \$ra, 0 >> -[  ]+8:[  ]+1e00000c[  ]+pcaddu18i[  ]+\$t0, 0 >> +[  ]+8:[  ]+1e000001[  ]+pcaddu18i[  ]+\$ra, 0 >>  [  ]+8: R_LARCH_CALL36[  ]+a >> -[  ]+c:[  ]+4c000180[  ]+jr[  ]+\$t0 >> +[  ]+c:[  ]+4c000021[  ]+jirl[  ]+\$ra, \$ra, 0 >> +[  ]+10:[  ]+1e00000c[  ]+pcaddu18i[  ]+\$t0, 0 >> +[  ]+10: R_LARCH_CALL36[  ]+a >> +[  ]+14:[  ]+4c000180[  ]+jr[  ]+\$t0 >> +[  ]+18:[  ]+1e00000c[  ]+pcaddu18i[  ]+\$t0, 0 >> +[  ]+18: R_LARCH_CALL36[  ]+a >> +[  ]+1c:[  ]+4c000180[  ]+jr[  ]+\$t0 >> diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s >> index f2977d1c6d7..55a2fc6ffff 100644 >> --- a/gas/testsuite/gas/loongarch/medium-call.s >> +++ b/gas/testsuite/gas/loongarch/medium-call.s >> @@ -1,6 +1,8 @@ >>    # call .L1, r1(ra) temp register, r1(ra) return register. >> +  call a >>    pcaddu18i $r1, %call36(a) >>    jirl     $r1, $r1, 0 >>    # tail .L1, r12(t0) temp register, r0(zero) return register. >> +  tail a >>    pcaddu18i $r12, %call36(a) >>    jirl     $r0, $r12, 0 >> diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s >> index 4d1888b76a0..31d4c2c1c75 100644 >> --- a/ld/testsuite/ld-loongarch-elf/medium-call.s >> +++ b/ld/testsuite/ld-loongarch-elf/medium-call.s >> @@ -1,7 +1,9 @@ >>  .L1: >>    # call .L1, r1(ra) temp register, r1(ra) return register. >> +  call .L1 >>    pcaddu18i $r1, %call36(.L1) >>    jirl     $r1, $r1, 0 >>    # tail .L1, r12(t0) temp register, r0(zero) return register. >> +  tail .L1 >>    pcaddu18i $r12, %call36(.L1) >>    jirl     $r0, $r12, 0 >> diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c >> index 15c7da6340c..1d02f020686 100644 >> --- a/opcodes/loongarch-opc.c >> +++ b/opcodes/loongarch-opc.c >> @@ -293,6 +293,15 @@ const char *const loongarch_x_normal_name[32] = >>    &LARCH_opts.ase_lp64,       \ >>    &LARCH_opts.ase_gpcr >> >> +#define INSN_LA_CALL       \ >> +  "pcaddu18i $ra,%%call36(%1);"    \ >> +  "jirl $ra,$ra,0;",    \ >> +  &LARCH_opts.ase_lp64, 0 >> + >> +#define INSN_LA_TAIL       \ >> +  "pcaddu18i $t0,%%call36(%1);"   \ >> +  "jirl $zero,$t0,0;",   \ >> +  &LARCH_opts.ase_lp64, 0 >> >>  static struct loongarch_opcode loongarch_macro_opcodes[] = >>  { >> @@ -340,6 +349,8 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = >>    { 0, 0, "la.tls.gd", "r,l",   INSN_LA_TLS_GD64, 0 }, >>    { 0, 0, "la.tls.gd", "r,l",   INSN_LA_TLS_GD64_LARGE_ABS, 0 }, >>    { 0, 0, "la.tls.gd", "r,r,l",  INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, >> +  { 0, 0, "call", "la",   INSN_LA_CALL, 0 }, >> +  { 0, 0, "tail", "la",   INSN_LA_TAIL, 0 }, >>    { 0, 0, "pcaddi", "r,la",   "pcaddi %1, %%pcrel_20(%2)", &LARCH_opts.ase_ilp32, 0, 0 }, >>    { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list.  */ >>  };