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[87.115.72.52]) by smtp.gmail.com with ESMTPSA id j6-20020a05620a410600b006b5cc25535fsm6778811qko.99.2022.09.16.06.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Sep 2022 06:21:14 -0700 (PDT) From: Andrew Burgess To: binutils@sourceware.org Cc: Andrew Burgess Subject: [PATCH 1/2] opcodes/arm: add missing ';' characters Date: Fri, 16 Sep 2022 14:21:04 +0100 Message-Id: <8cc1b606a6e5c5164b03389d04f127f7909a2a36.1663334366.git.aburgess@redhat.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I spotted a couple of places where the ARM disassembler produces what seems to be some comment style text '@ Impl Def' without including a comment character ';'. In other places where we have similar messages a comment character is emitted, so I suspect this was just an oversight. Fixed in this commit by adding two new comment characters, and updating the expected test results. --- gas/testsuite/gas/arm/armv8.1-m.main-fp.d | 8 ++++---- gas/testsuite/gas/arm/vfp1xD.d | 16 ++++++++-------- gas/testsuite/gas/arm/vfp1xD_t2.d | 8 ++++---- opcodes/arm-dis.c | 8 ++++---- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d index dd69e0d5252..e8d57ab5fd1 100644 --- a/gas/testsuite/gas/arm/armv8.1-m.main-fp.d +++ b/gas/testsuite/gas/arm/armv8.1-m.main-fp.d @@ -252,13 +252,13 @@ Disassembly of section .text: 0+3b2 <[^>]*> bf04 itt eq 0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9 0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8 -0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def -0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def +0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst ;@ Impl def +0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def 0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0 0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1 0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (|vpr) -0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def -0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def +0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def +0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def 0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0 0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0 0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (|vpr), r0 diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d index 079f7a17e59..2c33e14edc7 100644 --- a/gas/testsuite/gas/arm/vfp1xD.d +++ b/gas/testsuite/gas/arm/vfp1xD.d @@ -239,13 +239,13 @@ Disassembly of section .text: 0+394 <[^>]*> 0ef09a10 (vmrseq|fmrxeq) r9, fpsid 0+398 <[^>]*> 0e019a90 (vmoveq|fmsreq) s3, r9 0+39c <[^>]*> 0ee08a10 (vmsreq|fmxreq) fpsid, r8 -0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst @ Impl def -0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def +0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst ;@ Impl def +0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def 0+3a8 <[^>]*> eef70a10 (vmrs|fmrx) r0, mvfr0 0+3ac <[^>]*> eef60a10 (vmrs|fmrx) r0, mvfr1 0+3b0 <[^>]*> eefc0a10 (vmrs|fmrx) r0, (vpr|) -0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 @ Impl def -0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def +0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def +0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def 0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0 0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0 0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) (vpr|), r0 @@ -280,15 +280,15 @@ Disassembly of section .text: 0+438 <[^>]*> eee1ea10 vmsr fpscr, lr 0+43c <[^>]*> eee01a10 vmsr fpsid, r1 0+440 <[^>]*> eee82a10 vmsr fpexc, r2 -0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def -0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def +0+444 <[^>]*> eee93a10 vmsr fpinst, r3 ;@ Impl def +0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 ;@ Impl def 0+44c <[^>]*> eeef5a10 vmsr (c15||fpcxt_s), r5 0+450 <[^>]*> eef03a10 vmrs r3, fpsid 0+454 <[^>]*> eef64a10 vmrs r4, mvfr1 0+458 <[^>]*> eef75a10 vmrs r5, mvfr0 0+45c <[^>]*> eef86a10 vmrs r6, fpexc -0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def -0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def +0+460 <[^>]*> eef97a10 vmrs r7, fpinst ;@ Impl def +0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 ;@ Impl def 0+468 <[^>]*> eeff9a10 vmrs r9, (c15||fpcxt_s) 0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\) 0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d index 248185d4486..634fbb00518 100644 --- a/gas/testsuite/gas/arm/vfp1xD_t2.d +++ b/gas/testsuite/gas/arm/vfp1xD_t2.d @@ -253,13 +253,13 @@ Disassembly of section .text: 0+3b2 <[^>]*> bf04 itt eq 0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9 0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8 -0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def -0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def +0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst ;@ Impl def +0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 ;@ Impl def 0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0 0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1 0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, (|vpr) -0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def -0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def +0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 ;@ Impl def +0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 ;@ Impl def 0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0 0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0 0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) (|vpr), r0 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 684c74f7f20..5de78cec33d 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -897,9 +897,9 @@ static const struct sopcode32 coprocessor_opcodes[] = {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, + 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t;@ Impl def"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, + 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t;@ Impl def"}, {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"}, {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), @@ -925,9 +925,9 @@ static const struct sopcode32 coprocessor_opcodes[] = {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, + 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t;@ Impl def"}, {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), - 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, + 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t;@ Impl def"}, {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"}, {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE), -- 2.25.4