From: Jan Beulich <jbeulich@suse.com>
To: "Cui, Lili" <lili.cui@intel.com>
Cc: hjl.tools@gmail.com, binutils@sourceware.org
Subject: Re: [PATCH v2 1/3] x86: Use vexvvvv as the switch state to encode the vvvv register
Date: Tue, 30 Apr 2024 17:27:59 +0200 [thread overview]
Message-ID: <8d1aed71-0657-45f1-ab35-de67a303818e@suse.com> (raw)
In-Reply-To: <20240430104004.3048944-2-lili.cui@intel.com>
On 30.04.2024 12:40, Cui, Lili wrote:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -141,7 +141,9 @@
>
> #define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL
>
> -#define DstVVVV VexVVVV=VexVVVV_DST
> +#define Src1VVVV VexVVVV=VexVVVV_SRC1
> +#define DstVVVV VexVVVV=VexVVVV_DST
> +
>
> // The template supports VEX format for cpuid and EVEX format for cpuid & APX_F.
> // While therefore we really mean cpuid|(cpuid&APX_F) here, this can't be
Nit: No double blank lines, please. Okay with that line left out.
Jan
next prev parent reply other threads:[~2024-04-30 15:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 10:40 [PATCH V2 0/3] x86: Optimize the encoder of " Cui, Lili
2024-04-30 10:40 ` [PATCH v2 1/3] x86: Use vexvvvv as the switch state to encode " Cui, Lili
2024-04-30 15:27 ` Jan Beulich [this message]
2024-04-30 10:40 ` [PATCH V2 2/3] x86: Drop SwapSources Cui, Lili
2024-04-30 15:28 ` Jan Beulich
2024-04-30 10:40 ` [PATCH V2 3/3] x86: Drop using extension_opcode to encode vvvv register Cui, Lili
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