From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id D88B0385C332 for ; Sat, 1 Oct 2022 05:39:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D88B0385C332 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 3B7BD300089; Sat, 1 Oct 2022 05:39:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1664602782; bh=En2Zvp0c3pVs1uJCf1B2IGRmO7v+fzqkmk+QeWqr9Hw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=aKJE5gvV7X30sXr8EEcBNI1/zAbAFabpRjYb0mi997ifcTEuPMFrj+W9wBu3yc4RJ kB8Xy/Pi7rbVKwCtk4J2vJTzVOewCaxPSMA012aFq7oV2kXoMuTcHSYKPDiGpQdmpL N2q0GDMDhpkS6NGu3xKNDtoNyz8DwKNp77C9tq1g= From: Tsukasa OI To: Tsukasa OI Cc: binutils@sourceware.org Subject: [PATCH 1/1] RISC-V: Move supervisor instructions after all unprivileged ones Date: Sat, 1 Oct 2022 05:39:26 +0000 Message-Id: <8db04962aba9c780f133840a8934353a58f223fe.1664602716.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This location of supervisor instructions is out of place (because many other privileged instructions are located at the tail but after the supervisor instructions, we have many unprivileged instructions including bit manipulation / crypto / vector instructions). Not only that, this is harmful to implement pseudoinstructions in the latest 'P'-extension proposal (CLROV and RDOV). This commit moves supervisor instructions after all unprivileged instructions. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Adjust indents. Move supervisor instructions after all unprivileged instructions. --- opcodes/riscv-opc.c | 64 ++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 7e95f645c5c..3eb69cdc34c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -912,38 +912,6 @@ const struct riscv_opcode riscv_opcodes[] = {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE }, {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE }, -/* Supervisor instructions. */ -{"csrr", 0, INSN_CLASS_ZICSR,"d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, -{"csrw", 0, INSN_CLASS_ZICSR,"E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrw", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrwi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrs", 0, INSN_CLASS_ZICSR,"E,s", MATCH_CSRRS, MASK_CSRRS|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrs", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrsi", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrc", 0, INSN_CLASS_ZICSR,"E,s", MATCH_CSRRC, MASK_CSRRC|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrc", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrci", 0, INSN_CLASS_ZICSR,"E,Z", MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS }, -{"csrrw", 0, INSN_CLASS_ZICSR,"d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, -{"csrrw", 0, INSN_CLASS_ZICSR,"d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS }, -{"csrrwi", 0, INSN_CLASS_ZICSR,"d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, -{"csrrs", 0, INSN_CLASS_ZICSR,"d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, -{"csrrs", 0, INSN_CLASS_ZICSR,"d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS }, -{"csrrsi", 0, INSN_CLASS_ZICSR,"d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, -{"csrrc", 0, INSN_CLASS_ZICSR,"d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, -{"csrrc", 0, INSN_CLASS_ZICSR,"d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS }, -{"csrrci", 0, INSN_CLASS_ZICSR,"d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, -{"uret", 0, INSN_CLASS_I, "", MATCH_URET, MASK_URET, match_opcode, 0 }, -{"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, -{"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, -{"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, -{"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, -{"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, -{"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, -{"sfence.vma", 0, INSN_CLASS_I, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, -{"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS }, -{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, -{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, - /* Zicbom and Zicboz instructions. */ {"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 }, {"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 }, @@ -1830,6 +1798,38 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, +/* Supervisor instructions. */ +{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, +{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrw", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrs", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRS, MASK_CSRRS|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrs", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrsi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRSI, MASK_CSRRSI|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrc", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRC, MASK_CSRRC|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrc", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrci", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRCI, MASK_CSRRCI|MASK_RD, match_opcode, INSN_ALIAS }, +{"csrrw", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, +{"csrrw", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, INSN_ALIAS }, +{"csrrwi", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, +{"csrrs", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, +{"csrrs", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, INSN_ALIAS }, +{"csrrsi", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, +{"csrrc", 0, INSN_CLASS_ZICSR, "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, +{"csrrc", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, INSN_ALIAS }, +{"csrrci", 0, INSN_CLASS_ZICSR, "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, +{"uret", 0, INSN_CLASS_I, "", MATCH_URET, MASK_URET, match_opcode, 0 }, +{"sret", 0, INSN_CLASS_I, "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, +{"hret", 0, INSN_CLASS_I, "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, +{"mret", 0, INSN_CLASS_I, "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, +{"dret", 0, INSN_CLASS_I, "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, +{"sfence.vm", 0, INSN_CLASS_I, "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, +{"sfence.vm", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, +{"sfence.vma", 0, INSN_CLASS_I, "", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS }, +{"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS }, +{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 }, +{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, + /* Svinval instructions. */ {"sinval.vma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 }, {"sfence.w.inval", 0, INSN_CLASS_SVINVAL, "", MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 }, -- 2.34.1