From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 76480 invoked by alias); 1 May 2019 17:16:30 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 76471 invoked by uid 89); 1 May 2019 17:16:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LOTSOFHASH autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 May 2019 17:16:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 171A180D for ; Wed, 1 May 2019 10:16:27 -0700 (PDT) Received: from [10.2.207.62] (e107157-lin.cambridge.arm.com [10.2.207.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B4EE23F719 for ; Wed, 1 May 2019 10:16:26 -0700 (PDT) Subject: [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh To: binutils@sourceware.org References: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> From: "Andre Vieira (lists)" Message-ID: <8db2c559-5949-f9bc-f50e-9b02ebdfe1ce@arm.com> Date: Wed, 01 May 2019 17:16:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <19569550-4d2e-0bb3-592a-d91050d490f6@arm.com> Content-Type: multipart/mixed; boundary="------------7741FC5A5264DB7CAF688AD1" X-IsSubscribed: yes X-SW-Source: 2019-05/txt/msg00053.txt.bz2 This is a multi-part message in MIME format. --------------7741FC5A5264DB7CAF688AD1 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 576 Hi, This patch adds support for MVE instructions VMLAS, VMULH, and VRMULH. gas/ChangeLog: 2019-05-01 Andre Vieira * config/tc-arm.c (do_mve_vmlas): New encoding function. (do_mve_vmulh): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlas-bad.d: New test. * testsuite/gas/arm/mve-vmlas-bad.l: New test. * testsuite/gas/arm/mve-vmlas-bad.s: New test. * testsuite/gas/arm/mve-vmulh-bad.d: New test. * testsuite/gas/arm/mve-vmulh-bad.l: New test. * testsuite/gas/arm/mve-vmulh-bad.s: New test. --------------7741FC5A5264DB7CAF688AD1 Content-Type: text/x-patch; name="24.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="24.patch" Content-length: 8067 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index dd02a8e5a790f170d1f87ae1c36dd5e7e5a4827a..1819b7bf078721aecd44a7a4c429b357b478657b 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15707,6 +15707,33 @@ do_mve_viddup (void) inst.is_neon = 1; } +static void +do_mve_vmlas (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); + + if (inst.operands[2].reg == REG_PC) + as_tsktsk (MVE_BAD_PC); + else if (inst.operands[2].reg == REG_SP) + as_tsktsk (MVE_BAD_SP); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + inst.instruction |= (et.type == NT_unsigned) << 28; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= neon_logbits (et.size) << 20; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= inst.operands[2].reg; + inst.is_neon = 1; +} + static void do_mve_vmaxnma_vminnma (void) { @@ -17238,6 +17265,21 @@ do_mve_vsbc (void) mve_encode_qqq (1, 64); } +static void +do_mve_vmulh (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + mve_encode_qqq (et.type == NT_unsigned, et.size); +} + static void do_mve_vmull (void) { @@ -24652,6 +24694,10 @@ static const struct asm_opcode insns[] = mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), + mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas), + mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), + mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), + #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), diff --git a/gas/testsuite/gas/arm/mve-vmlas-bad.d b/gas/testsuite/gas/arm/mve-vmlas-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..d33b1853628db5af044eea556e8005c56a409075 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlas-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VMLAS instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmlas-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmlas-bad.l b/gas/testsuite/gas/arm/mve-vmlas-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..3a06f32f636331a73ae150a5a62bd51b4360122d --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlas-bad.l @@ -0,0 +1,16 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmlas.s64 q0,q1,r2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmlas.f32 q0,q1,r2' +[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Error: syntax error -- `vmlaseq.s16 q0,q1,r2' +[^:]*:17: Error: syntax error -- `vmlaseq.s16 q0,q1,r2' +[^:]*:19: Error: syntax error -- `vmlaseq.s16 q0,q1,r2' +[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vmlast.s16 q0,q1,r2' +[^:]*:22: Error: instruction missing MVE vector predication code -- `vmlas.s16 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vmlas-bad.s b/gas/testsuite/gas/arm/mve-vmlas-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..5eff30e4f38aed6a3d970b9f0fa7d7f96eae468f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlas-bad.s @@ -0,0 +1,22 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vmlas.s16 q0, q1, r2 +.endr +.endm + +.syntax unified +.thumb +vmlas.s64 q0, q1, r2 +vmlas.f32 q0, q1, r2 +vmlas.u32 q0, q1, sp +vmlas.u32 q0, q1, pc +cond +it eq +vmlaseq.s16 q0, q1, r2 +vmlaseq.s16 q0, q1, r2 +vpst +vmlaseq.s16 q0, q1, r2 +vmlast.s16 q0, q1, r2 +vpst +vmlas.s16 q0, q1, r2 diff --git a/gas/testsuite/gas/arm/mve-vmulh-bad.d b/gas/testsuite/gas/arm/mve-vmulh-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..febf2812545e7901a0021f1220c0a78d8749a7d0 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmulh-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMULH and VRMULH instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmulh-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmulh-bad.l b/gas/testsuite/gas/arm/mve-vmulh-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..7e3c01b38f94f36c69d208110c0a8b51f79c4893 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmulh-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmulh.f16 q0,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmulh.i32 q0,q1,q2' +[^:]*:12: Error: bad type in SIMD instruction -- `vmulh.s64 q0,q1,q2' +[^:]*:13: Error: bad type in SIMD instruction -- `vrmulh.f16 q0,q1,q2' +[^:]*:14: Error: bad type in SIMD instruction -- `vrmulh.i32 q0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vrmulh.s64 q0,q1,q2' +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Error: syntax error -- `vmulheq.s16 q0,q1,q2' +[^:]*:20: Error: syntax error -- `vmulheq.s16 q0,q1,q2' +[^:]*:22: Error: syntax error -- `vmulheq.s16 q0,q1,q2' +[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmulht.s16 q0,q1,q2' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vmulh.s16 q0,q1,q2' +[^:]*:27: Error: syntax error -- `vrmulheq.s16 q0,q1,q2' +[^:]*:28: Error: syntax error -- `vrmulheq.s16 q0,q1,q2' +[^:]*:30: Error: syntax error -- `vrmulheq.s16 q0,q1,q2' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vrmulht.s16 q0,q1,q2' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vrmulh.s16 q0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmulh-bad.s b/gas/testsuite/gas/arm/mve-vmulh-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..84d3cceb87a21ff926e546daf05670fe6f22a39a --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmulh-bad.s @@ -0,0 +1,33 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().u16 q0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +vmulh.f16 q0, q1, q2 +vmulh.i32 q0, q1, q2 +vmulh.s64 q0, q1, q2 +vrmulh.f16 q0, q1, q2 +vrmulh.i32 q0, q1, q2 +vrmulh.s64 q0, q1, q2 +cond vmulh +cond vrmulh +it eq +vmulheq.s16 q0, q1, q2 +vmulheq.s16 q0, q1, q2 +vpst +vmulheq.s16 q0, q1, q2 +vmulht.s16 q0, q1, q2 +vpst +vmulh.s16 q0, q1, q2 +it eq +vrmulheq.s16 q0, q1, q2 +vrmulheq.s16 q0, q1, q2 +vpst +vrmulheq.s16 q0, q1, q2 +vrmulht.s16 q0, q1, q2 +vpst +vrmulh.s16 q0, q1, q2 --------------7741FC5A5264DB7CAF688AD1--