From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id C408C3858C00 for ; Sat, 30 Jul 2022 03:47:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C408C3858C00 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 1FC92300089; Sat, 30 Jul 2022 03:47:37 +0000 (UTC) Message-ID: <8ec9b6f2-6dab-ec90-f235-a27c5c5d07b9@irq.a4lg.com> Date: Sat, 30 Jul 2022 12:47:35 +0900 Mime-Version: 1.0 Subject: Re: [RFC PATCH 0/3] RISC-V: Check shift amount against XLEN (disassembler) Content-Language: en-US To: Palmer Dabbelt , Nelson Chu , Kito Cheng Cc: binutils@sourceware.org References: From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 30 Jul 2022 03:47:40 -0000 This patchset is officially withdrawn as I will submit new simpler patchset for the exact same issue. Thanks, Tsukasa On 2022/05/23 19:06, Tsukasa OI wrote: > ** Note ** > This patch is not compatible with my previous Zfinx fixes. Actual PATCH > v1 is going to be submitted after this patchset is reviewed and Zfinx > fixes (relatively high priority) are applied. > > Certain shift instructions have a constraint: shift amount must be less > than current XLEN. This constraint is checked on assembler and > simulator, but not on disassembler. It causes GDB to print wrong (and > invalid) instructions and can be a problem while ... for instance, > checking for invalid build configuration. > > We have several methods to deal with it: > > - Add `xlen' argument to match_func to test XLEN > - Split shift instructions to per-XLEN variants > > Because shift instructions are so basic and XLEN-checking is so simple, > I chose the former. The latter is used on my Zfinx fixes but this is > because register pair checking involves relatively complex per-operand > constraints. Complex solution for simple problem can be a new problem. > > But... > > - Is it okay to add an argument anyway? > - Which is better extra argument? > 1. unsigned xlen > 2. const riscv_parse_subset_t * subset > which contains ISA version, XLEN and extensions > ... but a part of BFD, not opcodes. > > I also (slightly) changed the assembler to suppress extra error message > just like I did on Zicbop instructions: > > > > > > > Tsukasa OI (3): > RISC-V: Add xlen to match_func > RISC-V: Check shift amount against XLEN > RISC-V: Add disassembler tests for shift amount > > gas/config/tc-riscv.c | 8 +- > gas/testsuite/gas/riscv/shamt-dis-32.d | 34 +++++++ > gas/testsuite/gas/riscv/shamt-dis-64.d | 34 +++++++ > gas/testsuite/gas/riscv/shamt-dis.s | 45 +++++++++ > include/opcode/riscv.h | 3 +- > opcodes/riscv-dis.c | 2 +- > opcodes/riscv-opc.c | 122 +++++++++++++++---------- > sim/riscv/sim-main.c | 2 +- > 8 files changed, 195 insertions(+), 55 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/shamt-dis-32.d > create mode 100644 gas/testsuite/gas/riscv/shamt-dis-64.d > create mode 100644 gas/testsuite/gas/riscv/shamt-dis.s > > > base-commit: cb0d58bf4d274cfb1ae11b75bd2b3ba81c8d371d