From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id CF148385AE4D for ; Sat, 9 Jul 2022 09:09:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CF148385AE4D Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 20B85300089; Sat, 9 Jul 2022 09:09:40 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 2/5] RISC-V: Complete tidying up with SCALL and SBREAK Date: Sat, 9 Jul 2022 18:09:11 +0900 Message-Id: <8ff41c96aca22fca64e0180d10b69c632b235bac.1657357697.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Jul 2022 09:09:43 -0000 This commit removes SCALL and SBREAK-related references except alias opcode entries because they are renamed to ECALL and EBREAK (respectively). include/ChangeLog: * opcode/riscv-opc.h (MATCH_SCALL, MASK_SCALL, MATCH_SBREAK, MASK_SBREAK): Remove. Also remove corresponding DECLARE_INSN declarations. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Use `ebreak' instead of `sbreak'. ChangeLog: * sim/riscv/sim-main.c (execute_i): Use `ebreak' instead of `sbreak'. --- include/opcode/riscv-opc.h | 6 ------ opcodes/riscv-opc.c | 4 ++-- sim/riscv/sim-main.c | 6 +++--- 3 files changed, 5 insertions(+), 11 deletions(-) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a808f52232b..d1f332708b5 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -49,10 +49,6 @@ #define MASK_RDTIMEH 0xfffff07f #define MATCH_RDINSTRETH 0xc8202073 #define MASK_RDINSTRETH 0xfffff07f -#define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff -#define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff #define MATCH_BEQ 0x63 #define MASK_BEQ 0x707f #define MATCH_BNE 0x1063 @@ -2508,8 +2504,6 @@ DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) -DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) -DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 2f9945aa930..bba152ecb41 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -428,8 +428,8 @@ const struct riscv_opcode riscv_opcodes[] = {"rdcycleh", 32, INSN_CLASS_I, "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, INSN_ALIAS }, {"rdinstreth", 32, INSN_CLASS_I, "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, INSN_ALIAS }, {"rdtimeh", 32, INSN_CLASS_I, "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, INSN_ALIAS }, -{"ecall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, -{"scall", 0, INSN_CLASS_I, "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{"ecall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, 0 }, +{"scall", 0, INSN_CLASS_I, "", MATCH_ECALL, MASK_ECALL, match_opcode, 0 }, {"xori", 0, INSN_CLASS_I, "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, {"xor", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, {"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 62f475671c9..30d2f1e1c9a 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -583,9 +583,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FENCE_I: TRACE_INSN (cpu, "fence.i;"); break; - case MATCH_SBREAK: - TRACE_INSN (cpu, "sbreak;"); - /* GDB expects us to step over SBREAK. */ + case MATCH_EBREAK: + TRACE_INSN (cpu, "ebreak;"); + /* GDB expects us to step over EBREAK. */ sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP); break; case MATCH_ECALL: -- 2.34.1