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Date: Wed, 30 Aug 2023 12:59:55 +0900
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Subject: Re: [PATCH 0/1] RISC-V: Make XVentanaCondOps RV64 only
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To: Greg Favor <gfavor@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, Andrew Waterman <andrew@sifive.com>,
 Jim Wilson <jim.wilson.gcc@gmail.com>, Nelson Chu <nelson@rivosinc.com>,
 Kito Cheng <kito.cheng@sifive.com>, Jeff Law <jlaw@ventanamicro.com>,
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From: Tsukasa OI <research_trasio@irq.a4lg.com>
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On 2023/08/30 12:21, Greg Favor wrote:
> On Tue, Aug 29, 2023 at 6:38 PM Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>> wrote:
> 
>     Unless Ventana is working on some RV32 processors (and soon to be
>     released
>     ), I think disabling XVentanaCondOps instructions on RV32 would be safer
>     (to prevent possible misuses).  I would like to hear thoughts especially
>     from Ventana employees since I am just a volunteer.
> 
> 
> Representing Ventana, what you say is correct, i.e. we have no plans to
> do RV32 processors.
> 
> Greg

Thanks for the official information.  Committing.

(we could make XVentanaCondOps invalid on RV32 considering your answer
but that's for another time.)

Tsukasa

>  
> 
>     I also chose not to reject XVentanaCondOps + RV32 because it is not
>     stated
>     that is illegal (unlike Zcf + RV64).  This patch set makes
>     XVentanaCondOps
>     + RV32 empty (yet legal).
>