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From: Jan Beulich <jbeulich@suse.com>
To: jacob navia <jacob@jacob.remcomp.fr>
Cc: Peter Bergner <bergner@linux.ibm.com>,
	binutils@sourceware.org, Andrew Waterman <andrew@sifive.com>
Subject: Re: Defined illegal instruction
Date: Mon, 12 Feb 2024 08:29:14 +0100	[thread overview]
Message-ID: <924c9ff6-4583-40b7-8099-4c48baf4dbaf@suse.com> (raw)
In-Reply-To: <80629157-361A-457F-81E1-21D2D23DD99F@jacob.remcomp.fr>

On 10.02.2024 13:56, jacob navia wrote:
> OK. So now we have:
> 
> unimp and
> c.unimp
> 
> Both generate 16 bit zeroes if the C extension is present.
> 
> If the C extension is not present,
> unimp generates 
> 
> csrw cycle, x0
> 
> If we want to generate the defined unimplemented instruction in 32 bis we write
> 
> .long 0
> 
> As in the power PC.

Except that on RISC-V (and other architectures separating code from data
by special labels, like Arm) you want to use .insn. Iirc this also ensures
debug line info would be properly emitted, if enabled.

Jan

  parent reply	other threads:[~2024-02-12  7:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-09 17:03 jacob navia
2024-02-09 17:21 ` Peter Bergner
2024-02-10  0:03   ` Andrew Waterman
2024-02-10 12:56     ` jacob navia
2024-02-11  0:50       ` Andrew Waterman
2024-02-12  7:29       ` Jan Beulich [this message]
     [not found]         ` <C47C292B-6017-4D1C-BEEC-E4D9D88BBD8E@jacob.remcomp.fr>
2024-02-13  7:20           ` Jan Beulich
2024-02-13  9:05             ` jacob navia

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