From: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
To: <binutils@sourceware.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>, <nickc@redhat.com>
Subject: [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements.
Date: Thu, 16 Nov 2023 11:39:41 +0000 [thread overview]
Message-ID: <94805bd5-a22c-4285-a068-8ce701880af6@arm.com> (raw)
In-Reply-To: <82c92cc2-bdb2-487c-b50f-05ec88f861d7@arm.com>
[-- Attachment #1: Type: text/plain, Size: 564 bytes --]
Hi,
This patch adds the permission model enhancement and memory
attribute index enhancement features and their corresponding
system registers in AArch64 assembler.
Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
Memory Attribute Index Enhancement (FEAT_AIE)
Extension to Translation Control Registers (FEAT_TCR2)
These features are available by default from Armv9.4-A architecture.
Regression tested for aarch64-none-elf target and found
no regressions.
Ok for binutils-master?
Regards,
Srinath.
[-- Attachment #2: rb18002.patch --]
[-- Type: text/plain, Size: 14614 bytes --]
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 1b67843a4dd1744ef1ab2a7f9af3013922b7dbec..71ec06e3cb47ae629e9fd023268c9e5b0c55cda6 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -27,3 +27,53 @@
.*: Error: selected processor does not support system register name 's1e1a'
.*: Error: selected processor does not support system register name 's1e2a'
.*: Error: selected processor does not support system register name 's1e3a'
+.*: Error: selected processor does not support system register name 'amair2_el1'
+.*: Error: selected processor does not support system register name 'amair2_el12'
+.*: Error: selected processor does not support system register name 'amair2_el2'
+.*: Error: selected processor does not support system register name 'amair2_el3'
+.*: Error: selected processor does not support system register name 'mair2_el1'
+.*: Error: selected processor does not support system register name 'mair2_el12'
+.*: Error: selected processor does not support system register name 'mair2_el2'
+.*: Error: selected processor does not support system register name 'mair2_el3'
+.*: Error: selected processor does not support system register name 'amair2_el1'
+.*: Error: selected processor does not support system register name 'amair2_el12'
+.*: Error: selected processor does not support system register name 'amair2_el2'
+.*: Error: selected processor does not support system register name 'amair2_el3'
+.*: Error: selected processor does not support system register name 'mair2_el1'
+.*: Error: selected processor does not support system register name 'mair2_el12'
+.*: Error: selected processor does not support system register name 'mair2_el2'
+.*: Error: selected processor does not support system register name 'mair2_el3'
+.*: Error: selected processor does not support system register name 'pir_el1'
+.*: Error: selected processor does not support system register name 'pir_el12'
+.*: Error: selected processor does not support system register name 'pir_el2'
+.*: Error: selected processor does not support system register name 'pir_el3'
+.*: Error: selected processor does not support system register name 'pire0_el1'
+.*: Error: selected processor does not support system register name 'pire0_el12'
+.*: Error: selected processor does not support system register name 'pire0_el2'
+.*: Error: selected processor does not support system register name 'pir_el1'
+.*: Error: selected processor does not support system register name 'pir_el12'
+.*: Error: selected processor does not support system register name 'pir_el2'
+.*: Error: selected processor does not support system register name 'pir_el3'
+.*: Error: selected processor does not support system register name 'pire0_el1'
+.*: Error: selected processor does not support system register name 'pire0_el12'
+.*: Error: selected processor does not support system register name 'pire0_el2'
+.*: Error: selected processor does not support system register name 's2pir_el2'
+.*: Error: selected processor does not support system register name 's2pir_el2'
+.*: Error: selected processor does not support system register name 'por_el0'
+.*: Error: selected processor does not support system register name 'por_el1'
+.*: Error: selected processor does not support system register name 'por_el12'
+.*: Error: selected processor does not support system register name 'por_el2'
+.*: Error: selected processor does not support system register name 'por_el3'
+.*: Error: selected processor does not support system register name 'por_el0'
+.*: Error: selected processor does not support system register name 'por_el1'
+.*: Error: selected processor does not support system register name 'por_el12'
+.*: Error: selected processor does not support system register name 'por_el2'
+.*: Error: selected processor does not support system register name 'por_el3'
+.*: Error: selected processor does not support system register name 's2por_el1'
+.*: Error: selected processor does not support system register name 's2por_el1'
+.*: Error: selected processor does not support system register name 'tcr2_el1'
+.*: Error: selected processor does not support system register name 'tcr2_el12'
+.*: Error: selected processor does not support system register name 'tcr2_el2'
+.*: Error: selected processor does not support system register name 'tcr2_el1'
+.*: Error: selected processor does not support system register name 'tcr2_el12'
+.*: Error: selected processor does not support system register name 'tcr2_el2'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index 18376bb5ac19d821c8fcef2dcb272cdc2b9c5e52..ea4cc867ec3ea9595f7076e49d5d48c7794921dd 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -34,3 +34,53 @@ Disassembly of section \.text:
.*: d5087941 at s1e1a, x1
.*: d50c7943 at s1e2a, x3
.*: d50e7945 at s1e3a, x5
+.*: d538a320 mrs x0, amair2_el1
+.*: d53da320 mrs x0, amair2_el12
+.*: d53ca320 mrs x0, amair2_el2
+.*: d53ea320 mrs x0, amair2_el3
+.*: d538a220 mrs x0, mair2_el1
+.*: d53da220 mrs x0, mair2_el12
+.*: d53ca120 mrs x0, mair2_el2
+.*: d53ea120 mrs x0, mair2_el3
+.*: d518a320 msr amair2_el1, x0
+.*: d51da320 msr amair2_el12, x0
+.*: d51ca320 msr amair2_el2, x0
+.*: d51ea320 msr amair2_el3, x0
+.*: d518a220 msr mair2_el1, x0
+.*: d51da220 msr mair2_el12, x0
+.*: d51ca120 msr mair2_el2, x0
+.*: d51ea120 msr mair2_el3, x0
+.*: d538a260 mrs x0, pir_el1
+.*: d53da260 mrs x0, pir_el12
+.*: d53ca260 mrs x0, pir_el2
+.*: d53ea260 mrs x0, pir_el3
+.*: d538a240 mrs x0, pire0_el1
+.*: d53da240 mrs x0, pire0_el12
+.*: d53ca240 mrs x0, pire0_el2
+.*: d518a260 msr pir_el1, x0
+.*: d51da260 msr pir_el12, x0
+.*: d51ca260 msr pir_el2, x0
+.*: d51ea260 msr pir_el3, x0
+.*: d518a240 msr pire0_el1, x0
+.*: d51da240 msr pire0_el12, x0
+.*: d51ca240 msr pire0_el2, x0
+.*: d53ca2a0 mrs x0, s2pir_el2
+.*: d51ca2a0 msr s2pir_el2, x0
+.*: d53ba280 mrs x0, por_el0
+.*: d538a280 mrs x0, por_el1
+.*: d53da280 mrs x0, por_el12
+.*: d53ca280 mrs x0, por_el2
+.*: d53ea280 mrs x0, por_el3
+.*: d51ba280 msr por_el0, x0
+.*: d518a280 msr por_el1, x0
+.*: d51da280 msr por_el12, x0
+.*: d51ca280 msr por_el2, x0
+.*: d51ea280 msr por_el3, x0
+.*: d538a2a0 mrs x0, s2por_el1
+.*: d518a2a0 msr s2por_el1, x0
+.*: d5382060 mrs x0, tcr2_el1
+.*: d53d2060 mrs x0, tcr2_el12
+.*: d53c2060 mrs x0, tcr2_el2
+.*: d5182060 msr tcr2_el1, x0
+.*: d51d2060 msr tcr2_el12, x0
+.*: d51c2060 msr tcr2_el2, x0
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 4e494a965f6a9196395b2da1f8fb7da3e42faa7c..2768c2686903629d88ca36ef1404b4ea0a0c477a 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -32,3 +32,69 @@
at s1e1a, x1
at s1e2a, x3
at s1e3a, x5
+
+ /* FEAT_AIE. */
+ mrs x0, amair2_el1
+ mrs x0, amair2_el12
+ mrs x0, amair2_el2
+ mrs x0, amair2_el3
+ mrs x0, mair2_el1
+ mrs x0, mair2_el12
+ mrs x0, mair2_el2
+ mrs x0, mair2_el3
+
+ msr amair2_el1, x0
+ msr amair2_el12, x0
+ msr amair2_el2, x0
+ msr amair2_el3, x0
+ msr mair2_el1, x0
+ msr mair2_el12, x0
+ msr mair2_el2, x0
+ msr mair2_el3, x0
+
+ /* FEAT_S1PIE. */
+ mrs x0, pir_el1
+ mrs x0, pir_el12
+ mrs x0, pir_el2
+ mrs x0, pir_el3
+ mrs x0, pire0_el1
+ mrs x0, pire0_el12
+ mrs x0, pire0_el2
+
+ msr pir_el1, x0
+ msr pir_el12, x0
+ msr pir_el2, x0
+ msr pir_el3, x0
+ msr pire0_el1, x0
+ msr pire0_el12, x0
+ msr pire0_el2, x0
+
+ /* FEAT_S2PIE. */
+ mrs x0, s2pir_el2
+ msr s2pir_el2, x0
+
+ /* FEAT_S1POE. */
+ mrs x0, por_el0
+ mrs x0, por_el1
+ mrs x0, por_el12
+ mrs x0, por_el2
+ mrs x0, por_el3
+
+ msr por_el0, x0
+ msr por_el1, x0
+ msr por_el12, x0
+ msr por_el2, x0
+ msr por_el3, x0
+
+ /* FEAT_S21POE. */
+ mrs x0, s2por_el1
+ msr s2por_el1, x0
+
+ /* FEAT_TCR2. */
+ mrs x0, tcr2_el1
+ mrs x0, tcr2_el12
+ mrs x0, tcr2_el2
+
+ msr tcr2_el1, x0
+ msr tcr2_el12, x0
+ msr tcr2_el2, x0
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 792d6a4f4a7603487899f175c2b49763cbb47697..df0864009fe145028aef9c8d5e5e76badd616f1b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -185,6 +185,18 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PFAR,
/* Address Translate Stage 1. */
AARCH64_FEATURE_ATS1A,
+ /* Memory Attribute Index Enhancement. */
+ AARCH64_FEATURE_AIE,
+ /* Stage 1 Permission Indirection Extension. */
+ AARCH64_FEATURE_S1PIE,
+ /* Stage 2 Permission Indirection Extension. */
+ AARCH64_FEATURE_S2PIE,
+ /* Stage 1 Permission Overlay Extension. */
+ AARCH64_FEATURE_S1POE,
+ /* Stage 2 Permission Overlay Extension. */
+ AARCH64_FEATURE_S2POE,
+ /* Extension to Translation Control Registers. */
+ AARCH64_FEATURE_TCR2,
AARCH64_NUM_FEATURES
};
@@ -248,7 +260,13 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
| AARCH64_FEATBIT (X, PFAR) \
- | AARCH64_FEATBIT (X, ATS1A))
+ | AARCH64_FEATBIT (X, ATS1A) \
+ | AARCH64_FEATBIT (X, AIE) \
+ | AARCH64_FEATBIT (X, S1PIE) \
+ | AARCH64_FEATBIT (X, S2PIE) \
+ | AARCH64_FEATBIT (X, S1POE) \
+ | AARCH64_FEATBIT (X, S2POE) \
+ | AARCH64_FEATBIT (X, TCR2))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index b51c5aa14598abe8628d6a1363b43d6604dc8fda..0f647efca7e46a8554ac5c850fb315860bbede33 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -54,6 +54,10 @@
SYSREG ("amair_el12", CPENC (3,5,10,3,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("amair_el2", CPENC (3,4,10,3,0), 0, AARCH64_NO_FEATURES)
SYSREG ("amair_el3", CPENC (3,6,10,3,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("amair2_el1", CPENC (3,0,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el12", CPENC (3,5,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el2", CPENC (3,4,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("amair2_el3", CPENC (3,6,10,3,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
SYSREG ("amcfgr_el0", CPENC (3,3,13,2,1), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
SYSREG ("amcg1idr_el0", CPENC (3,3,13,2,6), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_6A))
SYSREG ("amcgcr_el0", CPENC (3,3,13,2,2), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_4A))
@@ -556,6 +560,10 @@
SYSREG ("mair_el12", CPENC (3,5,10,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("mair_el2", CPENC (3,4,10,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("mair_el3", CPENC (3,6,10,2,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("mair2_el1", CPENC (3,0,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el12", CPENC (3,5,10,2,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el2", CPENC (3,4,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
+ SYSREG ("mair2_el3", CPENC (3,6,10,1,1), F_ARCHEXT, AARCH64_FEATURE (AIE))
SYSREG ("mdccint_el1", CPENC (2,0,0,2,0), 0, AARCH64_NO_FEATURES)
SYSREG ("mdccsr_el0", CPENC (2,3,0,1,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("mdcr_el2", CPENC (3,4,1,1,1), 0, AARCH64_NO_FEATURES)
@@ -600,6 +608,13 @@
SYSREG ("oseccr_el1", CPENC (2,0,0,6,2), 0, AARCH64_NO_FEATURES)
SYSREG ("oslar_el1", CPENC (2,0,1,0,4), F_REG_WRITE, AARCH64_NO_FEATURES)
SYSREG ("oslsr_el1", CPENC (2,0,1,1,4), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("pir_el1", CPENC (3,0,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el12", CPENC (3,5,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el2", CPENC (3,4,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pir_el3", CPENC (3,6,10,2,3), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el1", CPENC (3,0,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el12", CPENC (3,5,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
+ SYSREG ("pire0_el2", CPENC (3,4,10,2,2), F_ARCHEXT, AARCH64_FEATURE (S1PIE))
SYSREG ("pan", CPENC (3,0,4,2,3), F_ARCHEXT, AARCH64_FEATURE (PAN))
SYSREG ("par_el1", CPENC (3,0,7,4,0), F_REG_128, AARCH64_NO_FEATURES)
SYSREG ("pfar_el1", CPENC (3,0,6,0,5), F_ARCHEXT, AARCH64_FEATURE (PFAR))
@@ -699,6 +714,11 @@
SYSREG ("pmuserenr_el0", CPENC (3,3,9,14,0), 0, AARCH64_NO_FEATURES)
SYSREG ("pmxevcntr_el0", CPENC (3,3,9,13,2), 0, AARCH64_NO_FEATURES)
SYSREG ("pmxevtyper_el0", CPENC (3,3,9,13,1), 0, AARCH64_NO_FEATURES)
+ SYSREG ("por_el0", CPENC (3,3,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el1", CPENC (3,0,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el12", CPENC (3,5,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el2", CPENC (3,4,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
+ SYSREG ("por_el3", CPENC (3,6,10,2,4), F_ARCHEXT, AARCH64_FEATURE (S1POE))
SYSREG ("prbar10_el1", CPENC (3,0,6,13,0), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("prbar10_el2", CPENC (3,4,6,13,0), F_ARCHEXT, AARCH64_FEATURE (V8R))
SYSREG ("prbar11_el1", CPENC (3,0,6,13,4), F_ARCHEXT, AARCH64_FEATURE (V8R))
@@ -818,11 +838,16 @@
SYSREG ("spsr_und", CPENC (3,4,4,3,2), 0, AARCH64_NO_FEATURES)
SYSREG ("ssbs", CPENC (3,3,4,2,6), F_ARCHEXT, AARCH64_FEATURE (SSBS))
SYSREG ("svcr", CPENC (3,3,4,2,2), F_ARCHEXT, AARCH64_FEATURE (SME))
+ SYSREG ("s2pir_el2", CPENC (3,4,10,2,5), F_ARCHEXT, AARCH64_FEATURE (S2PIE))
+ SYSREG ("s2por_el1", CPENC (3,0,10,2,5), F_ARCHEXT, AARCH64_FEATURE (S2POE))
SYSREG ("tco", CPENC (3,3,4,2,7), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
SYSREG ("tcr_el1", CPENC (3,0,2,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("tcr_el12", CPENC (3,5,2,0,2), F_ARCHEXT, AARCH64_FEATURE (V8_1A))
SYSREG ("tcr_el2", CPENC (3,4,2,0,2), 0, AARCH64_NO_FEATURES)
SYSREG ("tcr_el3", CPENC (3,6,2,0,2), 0, AARCH64_NO_FEATURES)
+ SYSREG ("tcr2_el1", CPENC (3,0,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2))
+ SYSREG ("tcr2_el12", CPENC (3,5,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2))
+ SYSREG ("tcr2_el2", CPENC (3,4,2,0,3), F_ARCHEXT, AARCH64_FEATURE (TCR2))
SYSREG ("teecr32_el1", CPENC (2,2,0,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("teehbr32_el1", CPENC (2,2,1,0,0), 0, AARCH64_NO_FEATURES)
SYSREG ("tfsr_el1", CPENC (3,0,5,6,0), F_ARCHEXT, AARCH64_FEATURE (MEMTAG))
next prev parent reply other threads:[~2023-11-16 11:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-16 11:26 [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Srinath Parvathaneni
2023-11-16 11:28 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Srinath Parvathaneni
2023-11-16 11:31 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Srinath Parvathaneni
2023-11-16 11:38 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Srinath Parvathaneni
2023-11-16 11:39 ` Srinath Parvathaneni [this message]
2023-11-16 14:16 ` [PATCH 5/5][BINUTILS] aarch64: Add support for VMSA feature enhancements Richard Earnshaw
2023-11-28 14:01 ` Jan Beulich
2023-11-16 14:13 ` [PATCH 4/5][BINUTILS] aarch64: Add new AT system instructions Richard Earnshaw
2023-11-16 12:04 ` [PATCH 3/5][BINUTILS] aarch64: Add support to new features in RAS extension Richard Earnshaw
2023-11-16 11:58 ` [PATCH 2/5][BINUTILS] aarch64: Add features to the Statistical Profiling Extension Richard Earnshaw
2023-11-16 11:55 ` [PATCH 1/5][BINUTILS] aarch64: Add SLC target for PRFM instruction Richard Earnshaw
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