From: Jan Beulich <jbeulich@suse.com>
To: Binutils <binutils@sourceware.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>
Subject: [PATCH 05/10] x86: SIMD shift-by-immediate don't need to go through mod_table[]
Date: Tue, 4 Jul 2023 17:21:38 +0200 [thread overview]
Message-ID: <96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com> (raw)
In-Reply-To: <de113d3f-86db-2196-8ac9-fa6dc7efa195@suse.com>
OP_MS() and OP_XS() reject memory forms of insns quite fine. This then
also eliminates mis-named enumerators (we use M_1 for register forms).
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -828,17 +828,17 @@ enum
REG_0F1E_P_1_MOD_3,
REG_0F38D8_PREFIX_1,
REG_0F3A0F_PREFIX_1_MOD_3,
- REG_0F71_MOD_0,
- REG_0F72_MOD_0,
- REG_0F73_MOD_0,
+ REG_0F71,
+ REG_0F72,
+ REG_0F73,
REG_0FA6,
REG_0FA7,
REG_0FAE,
REG_0FBA,
REG_0FC7,
- REG_VEX_0F71_M_0,
- REG_VEX_0F72_M_0,
- REG_VEX_0F73_M_0,
+ REG_VEX_0F71,
+ REG_VEX_0F72,
+ REG_VEX_0F73,
REG_VEX_0FAE,
REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
REG_VEX_0F38F3_L_0,
@@ -884,9 +884,6 @@ enum
MOD_0F1C_PREFIX_0,
MOD_0F1E_PREFIX_1,
MOD_0F50,
- MOD_0F71,
- MOD_0F72,
- MOD_0F73,
MOD_0FAE_REG_0,
MOD_0FAE_REG_1,
MOD_0FAE_REG_2,
@@ -911,9 +908,6 @@ enum
MOD_VEX_0F47_L_1,
MOD_VEX_0F4A_L_1,
MOD_VEX_0F4B_L_1,
- MOD_VEX_0F71,
- MOD_VEX_0F72,
- MOD_VEX_0F73,
MOD_VEX_0F91_L_0,
MOD_VEX_0F92_L_0,
MOD_VEX_0F93_L_0,
@@ -2188,9 +2182,9 @@ static const struct dis386 dis386_twobyt
{ PREFIX_TABLE (PREFIX_0F6F) },
/* 70 */
{ PREFIX_TABLE (PREFIX_0F70) },
- { MOD_TABLE (MOD_0F71) },
- { MOD_TABLE (MOD_0F72) },
- { MOD_TABLE (MOD_0F73) },
+ { REG_TABLE (REG_0F71) },
+ { REG_TABLE (REG_0F72) },
+ { REG_TABLE (REG_0F73) },
{ "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
{ "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
{ "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
@@ -2745,7 +2739,7 @@ static const struct dis386 reg_table[][8
{
{ RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
},
- /* REG_0F71_MOD_0 */
+ /* REG_0F71 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -2755,7 +2749,7 @@ static const struct dis386 reg_table[][8
{ Bad_Opcode },
{ "psllw", { MS, Ib }, PREFIX_OPCODE },
},
- /* REG_0F72_MOD_0 */
+ /* REG_0F72 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -2765,7 +2759,7 @@ static const struct dis386 reg_table[][8
{ Bad_Opcode },
{ "pslld", { MS, Ib }, PREFIX_OPCODE },
},
- /* REG_0F73_MOD_0 */
+ /* REG_0F73 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -2824,7 +2818,7 @@ static const struct dis386 reg_table[][8
{ MOD_TABLE (MOD_0FC7_REG_6) },
{ MOD_TABLE (MOD_0FC7_REG_7) },
},
- /* REG_VEX_0F71_M_0 */
+ /* REG_VEX_0F71 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -2834,7 +2828,7 @@ static const struct dis386 reg_table[][8
{ Bad_Opcode },
{ "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
},
- /* REG_VEX_0F72_M_0 */
+ /* REG_VEX_0F72 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -2844,7 +2838,7 @@ static const struct dis386 reg_table[][8
{ Bad_Opcode },
{ "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
},
- /* REG_VEX_0F73_M_0 */
+ /* REG_VEX_0F73 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -6015,9 +6009,9 @@ static const struct dis386 vex_table[][2
{ PREFIX_TABLE (PREFIX_VEX_0F6F) },
/* 70 */
{ PREFIX_TABLE (PREFIX_VEX_0F70) },
- { MOD_TABLE (MOD_VEX_0F71) },
- { MOD_TABLE (MOD_VEX_0F72) },
- { MOD_TABLE (MOD_VEX_0F73) },
+ { REG_TABLE (REG_VEX_0F71) },
+ { REG_TABLE (REG_VEX_0F72) },
+ { REG_TABLE (REG_VEX_0F73) },
{ "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
@@ -8040,21 +8034,6 @@ static const struct dis386 mod_table[][2
{ "VmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
- /* MOD_0F71 */
- { Bad_Opcode },
- { REG_TABLE (REG_0F71_MOD_0) },
- },
- {
- /* MOD_0F72 */
- { Bad_Opcode },
- { REG_TABLE (REG_0F72_MOD_0) },
- },
- {
- /* MOD_0F73 */
- { Bad_Opcode },
- { REG_TABLE (REG_0F73_MOD_0) },
- },
- {
/* MOD_0FAE_REG_0 */
{ "fxsave", { FXSAVE }, 0 },
{ PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
@@ -8170,21 +8149,6 @@ static const struct dis386 mod_table[][2
{ VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
},
{
- /* MOD_VEX_0F71 */
- { Bad_Opcode },
- { REG_TABLE (REG_VEX_0F71_M_0) },
- },
- {
- /* MOD_VEX_0F72 */
- { Bad_Opcode },
- { REG_TABLE (REG_VEX_0F72_M_0) },
- },
- {
- /* MOD_VEX_0F73 */
- { Bad_Opcode },
- { REG_TABLE (REG_VEX_0F73_M_0) },
- },
- {
/* MOD_VEX_0F91_L_0 */
{ VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
},
next prev parent reply other threads:[~2023-07-04 15:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 15:17 [PATCH 00/10] x86: disassembler table entry folding plus some cleanup Jan Beulich
2023-07-04 15:18 ` [PATCH 01/10] x86: fold certain legacy/VEX table entries Jan Beulich
2023-07-04 15:19 ` [PATCH 02/10] x86: fold legacy/VEX {,V}MOV{H,L}* entries Jan Beulich
2023-07-04 15:20 ` [PATCH 03/10] x86: {,V}MOVNT* don't need to go through mod_table[] Jan Beulich
2023-07-04 15:21 ` [PATCH 04/10] x86: misc further memory-only insns " Jan Beulich
2023-07-04 15:21 ` Jan Beulich [this message]
2023-07-04 15:22 ` [PATCH 06/10] x86: slightly rework handling of some register-only insns Jan Beulich
2023-07-04 15:22 ` [PATCH 07/10] x86: various operations on mask registers can avoid going through mod_table[] Jan Beulich
2023-07-04 15:22 ` [PATCH 08/10] x86: misc further register-only insns don't need to go " Jan Beulich
2023-07-07 12:28 ` Jan Beulich
2023-07-04 15:23 ` [PATCH 09/10] x86: convert 0FXOP to just XOP in enumerator names Jan Beulich
2023-07-04 15:24 ` [PATCH 10/10] x86: simplify table-referencing macros Jan Beulich
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=96a500b4-1b68-520b-bccc-01d78f8e6f6c@suse.com \
--to=jbeulich@suse.com \
--cc=binutils@sourceware.org \
--cc=hjl.tools@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).