From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8252 invoked by alias); 17 Jan 2002 12:40:51 -0000 Mailing-List: contact binutils-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sources.redhat.com Received: (qmail 8104 invoked from network); 17 Jan 2002 12:40:48 -0000 Received: from unknown (HELO sohm.kpit.com) (203.129.230.82) by sources.redhat.com with SMTP; 17 Jan 2002 12:40:48 -0000 content-class: urn:content-classes:message Subject: [ PATCH] : SH Assembler generates incorrect opcode for PCMP instructions X-MIMEOLE: Produced By Microsoft Exchange V6.0.5762.3 Date: Thu, 17 Jan 2002 06:09:00 -0000 Message-ID: <97AA06615400F34AB695F23CE3D42E914B70A6@sohm.kpit.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: sh-coff-objdump cannot disassemble DSP instructions Thread-Index: AcGd1k30i7y+MFCvRHSua5EkFGEsYQBfNmxQ From: "Arati Dikey" To: X-SW-Source: 2002-01/txt/msg00344.txt.bz2 Hi ! The SH assembler generates incorrect opcodes for the parallel PCMP instruction. Basically, its last nibble is a copy of the previous instruction's second nibble when working in Big Endian format. For example, test.s movs.w @-R5, A0 PCMP X0,Y0 generates opcodes f5 70 f8 00 84 05 instead of f8 00 84 00 The following patch corrects this. I have also verified that it does not cause any side effect on other DSP instructions. Regards, Arati Dikey --- tc-sh.c.orig Thu Dec 6 11:34:18 2001 +++ tc-sh.c Thu Jan 17 16:41:28 2002 @@ -1769,7 +1769,10 @@ if (field_b) as_bad (_("multiple parallel processing specifications")); field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] << 8) - + (reg_x << 6) + (reg_y << 4) + reg_n); + + (reg_x << 6) + (reg_y << 4) ); + + if (strcmp (opcode->name, "pcmp") != 0) + field_b += reg_n; break; case PDC: if (cond)