[PATCH] Add MIPS R10000 performance counter opcodes

[PATCH] Add MIPS R10000 performance counter opcodes

[Thiemo Seufer]

Hi All,

this patch adds the MIPS R1[02]000 performance counter opcodes,
as well as a little testcase for these. I don't know if the
testcase is useful enough for inclusion.


Thiemo


2001-08-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>

	/include/opcode/ChangeLog
	* mips.h (INSN_10000): Define.
	(OPCODE_IS_MEMBER): Check for INSN_10000.

	/opcodes/ChangeLog
	* mips-opc.c (M1): Define. Reformatted Code.
	(mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
	mtps, mtps. Typo.

	/gas/testsuite/ChangeLog
	* gas/mips/mips.exp: Added performance counter test.
	* gas/mips/perfcount.s: New File. Test of performance counter opcodes.
	* gas/mips/perfcount.d: Likewise.


diff -BurpNX /bigdisk/src/binutils-exclude src-orig/include/opcode/mips.h src/include/opcode/mips.h
--- src-orig/include/opcode/mips.h	Sun Aug 12 13:35:15 2001
+++ src/include/opcode/mips.h	Sun Aug 12 16:25:38 2001
@@ -326,6 +326,8 @@ struct mips_opcode
 #define INSN_4100                 0x00040000
 /* Toshiba R3900 instruction.  */
 #define INSN_3900                 0x00080000
+/* MIPS R10000 instruction.  */
+#define INSN_10000                0x00100000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -375,7 +377,9 @@ struct mips_opcode
      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\
      || ((cpu == CPU_VR4100 || cpu == CPU_R4111)			\
 	 && ((insn)->membership & INSN_4100) != 0)			\
-     || (cpu == CPU_R3900  && ((insn)->membership & INSN_3900) != 0))
+     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
+     || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\
+	 && ((insn)->membership & INSN_10000) != 0))
 
 /* This is a list of macro expanded instructions.
 
diff -BurpNX /bigdisk/src/binutils-exclude src-orig/opcodes/mips-opc.c src/opcodes/mips-opc.c
--- src-orig/opcodes/mips-opc.c	Sun Aug 12 13:35:27 2001
+++ src/opcodes/mips-opc.c	Sun Aug 12 16:03:42 2001
@@ -86,15 +86,16 @@ Software Foundation, 59 Temple Place - S
 #define L1	INSN_4010
 #define V1      INSN_4100
 #define T3      INSN_3900
+#define M1	INSN_10000
 
 #define G1      (T3             \
                  )
 
-#define G2      (T3                   \
+#define G2      (T3             \
                  )
 
-#define G3 (I4             \
-            )
+#define G3      (I4             \
+                 )
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -557,6 +558,8 @@ const struct mips_opcode mips_builtin_op
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      G1	},
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1	},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          V1 },
+{"mfpc",    "t,P",	0x4000c801, 0xffe0ffc1,	LCD|WR_t|RD_C0,		M1	},
+{"mfps",    "t,P",	0x4000c800, 0xffe0ffc1,	LCD|WR_t|RD_C0,		M1	},
 {"mfc0",    "t,G",	0x40000000, 0xffe007ff,	LCD|WR_t|RD_C0,		I1	},
 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 	I32     },
 {"mfc1",    "t,S",	0x44000000, 0xffe007ff,	LCD|WR_t|RD_S|FP_S,	I1	},
@@ -594,6 +597,8 @@ const struct mips_opcode mips_builtin_op
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	L1	},
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     I32     },
+{"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		M1	},
+{"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		M1	},
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	I1	},
 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   I32     },
 {"mtc1",    "t,S",	0x44800000, 0xffe007ff,	COD|RD_t|WR_S|FP_S,	I1	},
@@ -836,7 +841,7 @@ const struct mips_opcode mips_builtin_op
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
-   disasembler recognizes more specific versions first.  */
+   disassembler recognizes more specific versions first.  */
 {"c0",      "C",	0x42000000, 0xfe000000,	0,			I1	},
 {"c1",      "C",	0x46000000, 0xfe000000,	0,			I1	},
 {"c2",      "C",	0x4a000000, 0xfe000000,	0,			I1	},
diff -BurpNX /bigdisk/src/binutils-exclude src-orig/gas/testsuite/gas/mips/mips.exp src/gas/testsuite/gas/mips/mips.exp
--- src-orig/gas/testsuite/gas/mips/mips.exp	Sun Aug 12 13:34:58 2001
+++ src/gas/testsuite/gas/mips/mips.exp	Sun Aug 12 16:03:42 2001
@@ -111,6 +111,7 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "mips4010"
     run_dump_test "mips4650"
     run_dump_test "mips4100"
+    run_dump_test "perfcount"
     # Linux uses ELF stabs, which doesn't support line number.
     setup_xfail "mips*-*-*linux*"
     run_dump_test "lineno"
diff -BurpNX /bigdisk/src/binutils-exclude src-orig/gas/testsuite/gas/mips/perfcount.d src/gas/testsuite/gas/mips/perfcount.d
--- src-orig/gas/testsuite/gas/mips/perfcount.d	Thu Jan  1 01:00:00 1970
+++ src/gas/testsuite/gas/mips/perfcount.d	Sun Aug 12 16:03:42 2001
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses -mmips:10000
+#name: MIPS R1[20]000 performance counters
+#as: -mips4 -march=r10000
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> mtps	a0,0
+0+0004 <[^>]*> mfps	a0,1
+0+0008 <[^>]*> mtpc	a0,1
+0+000c <[^>]*> mfpc	a0,0
diff -BurpNX /bigdisk/src/binutils-exclude src-orig/gas/testsuite/gas/mips/perfcount.s src/gas/testsuite/gas/mips/perfcount.s
--- src-orig/gas/testsuite/gas/mips/perfcount.s	Thu Jan  1 01:00:00 1970
+++ src/gas/testsuite/gas/mips/perfcount.s	Sun Aug 12 16:03:42 2001
@@ -0,0 +1,7 @@
+# source file to test assembly of R1[20]000 performance counter instructions.
+
+foo:
+	mtps	$4, 0
+	mfps	$4, 1
+	mtpc	$4, 1
+	mfpc	$4, 0

Re: [PATCH] Add MIPS R10000 performance counter opcodes

[Eric Christopher]

On 15 Aug 2001 23:25:43 +0200, Thiemo Seufer wrote:
> Hi All,
> 
> this patch adds the MIPS R1[02]000 performance counter opcodes,
> as well as a little testcase for these. I don't know if the
> testcase is useful enough for inclusion.
> 

Good to check that all of the instructions assemble.

> 2001-08-15  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
> 
> 	/include/opcode/ChangeLog
> 	* mips.h (INSN_10000): Define.
> 	(OPCODE_IS_MEMBER): Check for INSN_10000.
> 
> 	/opcodes/ChangeLog
> 	* mips-opc.c (M1): Define. Reformatted Code.
> 	(mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps,
> 	mtps, mtps. Typo.
> 
> 	/gas/testsuite/ChangeLog
> 	* gas/mips/mips.exp: Added performance counter test.
> 	* gas/mips/perfcount.s: New File. Test of performance counter opcodes.
> 	* gas/mips/perfcount.d: Likewise.
> 

Ok.

-eric

-- 
Look out behind you!