From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29087 invoked by alias); 22 May 2006 22:37:11 -0000 Received: (qmail 29079 invoked by uid 22791); 22 May 2006 22:37:10 -0000 X-Spam-Check-By: sourceware.org Received: from mail-out4.apple.com (HELO mail-out4.apple.com) (17.254.13.23) by sourceware.org (qpsmtpd/0.31) with ESMTP; Mon, 22 May 2006 22:37:06 +0000 Received: from relay5.apple.com (a17-128-113-35.apple.com [17.128.113.35]) by mail-out4.apple.com (8.12.11/8.12.11) with ESMTP id k4MMb1qj021578; Mon, 22 May 2006 15:37:01 -0700 (PDT) Received: from [17.201.27.222] (unknown [17.201.27.222]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (No client certificate requested) by relay5.apple.com (Apple SCV relay) with ESMTP id AF3BA324014; Mon, 22 May 2006 15:37:01 -0700 (PDT) In-Reply-To: <20060522202627.GE30254@networkno.de> References: <20060522202627.GE30254@networkno.de> Mime-Version: 1.0 (Apple Message framework v750) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: <9C4668ED-B9FB-4A18-BCF4-CA7F5DFFE0E1@apple.com> Cc: binutils@sourceware.org Content-Transfer-Encoding: 7bit From: Eric Christopher Subject: Re: [PATCH] Better checking of ISA/ASE/ABI options for MIPS gas Date: Tue, 23 May 2006 04:06:00 -0000 To: Thiemo Seufer X-Mailer: Apple Mail (2.750) X-IsSubscribed: yes Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2006-05/txt/msg00390.txt.bz2 > > I'm somewhat uncertain about the ABI incompatibility warning for > wrong FP register widths, does it make sense to force a different > FP register width in the assembler in some cases? > No. No more reading the minds of programmers. :) btw, the indention on the code in the diff is wacky. I assume it's correct in your files? > @@ -1031,7 +1052,13 @@ static int validate_mips_insn (const str > struct mips_cpu_info > { > const char *name; /* CPU or ISA name. */ > - int is_isa; /* Is this an ISA? (If 0, a CPU.) */ > + int flags; > +#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ > +#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS > ASE */ > +#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */ > +#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */ > +#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */ > +#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */ > int isa; /* ISA level. */ > int cpu; /* CPU number (default CPU if ISA). */ > }; Ugh. Can you haul these defines out somewhere else? And why change the table to include default extensions for the cpu? > > /* End of GCC-shared inference code. */ You need to make sure that this shared code is the same logic in both places - preferably before committing this. > + > +#if 0 /* XXX FIXME */ > + /* 32 bit code with 64 bit FP registers. */ > + if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) > + elf_elfheader (stdoutput)->e_flags |= ???; > +#endif > } > ??? -eric