From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson.chu@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Liao Shihua <shihua@iscas.ac.cn>
Cc: binutils@sourceware.org, gdb-patches@sourceware.org
Subject: [PATCH v5 1/3] RISC-V: Add 'M' extension testcases
Date: Mon, 29 Aug 2022 01:58:16 +0000 [thread overview]
Message-ID: <9a9dc0740607b2a2da025c0a31c540309e92898e.1661738291.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1661738291.git.research_trasio@irq.a4lg.com>
This commit adds basic 'M' (multiply/divide) extension testcases. m-ext.s
also contains preparation for 'Zmmul' extension testing (`zmmul' symbol).
gas/ChangeLog:
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
---
gas/testsuite/gas/riscv/m-ext-32.d | 18 +++++++++++++++
gas/testsuite/gas/riscv/m-ext-64.d | 23 ++++++++++++++++++++
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d | 4 ++++
gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l | 6 +++++
gas/testsuite/gas/riscv/m-ext.s | 21 ++++++++++++++++++
5 files changed, 72 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
create mode 100644 gas/testsuite/gas/riscv/m-ext.s
diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
new file mode 100644
index 00000000000..fe2ef9af54b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-32.d
@@ -0,0 +1,18 @@
+#as: -march=rv32im
+#source: m-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5c533[ ]+div[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5d533[ ]+divu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5e533[ ]+rem[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5f533[ ]+remu[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
new file mode 100644
index 00000000000..05099b14e9e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-64.d
@@ -0,0 +1,23 @@
+#as: -march=rv64im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+02c58533[ ]+mul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c59533[ ]+mulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5a533[ ]+mulhsu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5b533[ ]+mulhu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5c533[ ]+div[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5d533[ ]+divu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5e533[ ]+rem[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5f533[ ]+remu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5853b[ ]+mulw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5c53b[ ]+divw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5d53b[ ]+divuw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5e53b[ ]+remw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+02c5f53b[ ]+remuw[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
new file mode 100644
index 00000000000..54f8b8225dc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
@@ -0,0 +1,4 @@
+#as: -march=rv32im -defsym rv64=1
+#source: m-ext.s
+#objdump: -d
+#error_output: m-ext-fail-xlen-32.l
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
new file mode 100644
index 00000000000..d65ca4980e6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
@@ -0,0 +1,6 @@
+.*Assembler messages:
+.*: Error: unrecognized opcode `mulw a0,a1,a2'
+.*: Error: unrecognized opcode `divw a0,a1,a2'
+.*: Error: unrecognized opcode `divuw a0,a1,a2'
+.*: Error: unrecognized opcode `remw a0,a1,a2'
+.*: Error: unrecognized opcode `remuw a0,a1,a2'
diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
new file mode 100644
index 00000000000..68baf2ab9c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext.s
@@ -0,0 +1,21 @@
+target:
+ mul a0, a1, a2
+ mulh a0, a1, a2
+ mulhsu a0, a1, a2
+ mulhu a0, a1, a2
+.ifndef zmmul
+ div a0, a1, a2
+ divu a0, a1, a2
+ rem a0, a1, a2
+ remu a0, a1, a2
+.endif
+
+.ifdef rv64
+ mulw a0, a1, a2
+.ifndef zmmul
+ divw a0, a1, a2
+ divuw a0, a1, a2
+ remw a0, a1, a2
+ remuw a0, a1, a2
+.endif
+.endif
--
2.34.1
next prev parent reply other threads:[~2022-08-29 1:58 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-09 7:19 [PATCH 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-07-09 7:19 ` [PATCH 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI
2022-07-12 8:38 ` 廖仕华
2022-07-13 3:08 ` Tsukasa OI
2022-07-09 7:19 ` [PATCH 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-07-09 7:19 ` [PATCH 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-07-13 13:59 ` [PATCH v2 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-07-13 13:59 ` [PATCH v2 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI
2022-07-13 13:59 ` [PATCH v2 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-07-13 13:59 ` [PATCH v2 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-07-14 10:12 ` [PATCH v3 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-07-14 10:12 ` [PATCH v3 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI
2022-07-14 10:12 ` [PATCH v3 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-07-14 10:12 ` [PATCH v3 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-08-09 3:37 ` [PATCH v4 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-09 3:37 ` [PATCH v4 1/3] RISC-V: Add 'M' extension testcases Tsukasa OI
2022-08-09 3:37 ` [PATCH v4 2/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-09 3:37 ` [PATCH v4 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-08-29 1:58 ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Tsukasa OI
2022-08-29 1:58 ` Tsukasa OI [this message]
2022-08-29 1:58 ` [PATCH v5 2/3] " Tsukasa OI
2022-08-29 1:58 ` [PATCH v5 3/3] RISC-V: Add 'Zmmul' failure testcases Tsukasa OI
2022-08-30 9:55 ` [PATCH v5 0/3] RISC-V: Add 'Zmmul' extension Nelson Chu
2022-09-01 7:47 ` Tsukasa OI
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