From: Peter Bergner <bergner@linux.ibm.com>
To: Binutils <binutils@sourceware.org>
Subject: [COMMITTED] PowerPC: Add support for RFC02656 - Enhanced Load Store, with Length Instructions
Date: Wed, 7 Dec 2022 11:59:19 -0600 [thread overview]
Message-ID: <9e57c8dc-481b-82d3-7bba-8e7bd9426a1f@linux.ibm.com> (raw)
The following patch adds support for Power RFC02656 - Enhanced Load Store
with Length Instructions. When or even if this will ever show up in
hardware is not determined or guaranteed, therefore this is enabled using
the -mfuture gas option.
Peter
opcodes/
* ppc-opc.c (PPCVSXF): New define.
(powerpc_opcodes): Add lxvrl, lxvrll, lxvprl, lxvprll, stxvrl,
stxvrll, stxvprl, stxvprl.
gas/
* testsuite/gas/ppc/rfc02656.s: New test.
* testsuite/gas/ppc/rfc02656.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
---
gas/testsuite/gas/ppc/ppc.exp | 1 +
gas/testsuite/gas/ppc/rfc02656.d | 19 +++++++++++++++++++
gas/testsuite/gas/ppc/rfc02656.s | 10 ++++++++++
opcodes/ppc-opc.c | 13 +++++++++++++
4 files changed, 43 insertions(+)
create mode 100644 gas/testsuite/gas/ppc/rfc02656.d
create mode 100644 gas/testsuite/gas/ppc/rfc02656.s
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 500738a06ab..3c593eca805 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -146,6 +146,7 @@ run_dump_test "scalarquad"
run_dump_test "rop"
run_dump_test "rop-checks"
run_dump_test "rfc02653"
+run_dump_test "rfc02656"
run_dump_test "rfc02658"
run_dump_test "dcbt"
diff --git a/gas/testsuite/gas/ppc/rfc02656.d b/gas/testsuite/gas/ppc/rfc02656.d
new file mode 100644
index 00000000000..a24e13517f2
--- /dev/null
+++ b/gas/testsuite/gas/ppc/rfc02656.d
@@ -0,0 +1,19 @@
+#as: -mfuture
+#objdump: -dr -Mfuture
+#name: RFC02656 tests
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*: (1b 5c 4a 7c|7c 4a 5c 1b) lxvrl vs34,r10,r11
+.*: (5b 64 6a 7c|7c 6a 64 5b) lxvrll vs35,r10,r12
+.*: (9a 6c aa 7c|7c aa 6c 9a) lxvprl vs36,r10,r13
+.*: (da 74 ea 7c|7c ea 74 da) lxvprll vs38,r10,r14
+.*: (1b 7d 0a 7d|7d 0a 7d 1b) stxvrl vs40,r10,r15
+.*: (5b 85 2a 7d|7d 2a 85 5b) stxvrll vs41,r10,r16
+.*: (9a 8d 2a 7d|7d 2a 8d 9a) stxvprl vs40,r10,r17
+.*: (da 95 6a 7d|7d 6a 95 da) stxvprll vs42,r10,r18
+#pass
diff --git a/gas/testsuite/gas/ppc/rfc02656.s b/gas/testsuite/gas/ppc/rfc02656.s
new file mode 100644
index 00000000000..55ed2a672ae
--- /dev/null
+++ b/gas/testsuite/gas/ppc/rfc02656.s
@@ -0,0 +1,10 @@
+ .text
+_start:
+ lxvrl 34,10,11
+ lxvrll 35,10,12
+ lxvprl 36,10,13
+ lxvprll 38,10,14
+ stxvrl 40,10,15
+ stxvrll 41,10,16
+ stxvprl 40,10,17
+ stxvprll 42,10,18
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 4d67d2581b1..579b5b71ffe 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4972,6 +4972,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
#define PPCVSX2 PPC_OPCODE_POWER8
#define PPCVSX3 PPC_OPCODE_POWER9
#define PPCVSX4 PPC_OPCODE_POWER10
+#define PPCVSXF PPC_OPCODE_FUTURE
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
@@ -8405,6 +8406,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
+{"lxvrl", X(31,525), XX1_MASK, PPCVSXF, 0, {XT6, RA0, RB}},
{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
@@ -8450,6 +8452,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"subo.", XO(31,40,1,1), XO_MASK, PPC, EXT, {RT, RB, RA}},
+{"lxvrll", X(31,557), XX1_MASK, PPCVSXF, 0, {XT6, RA0, RB}},
+
{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
@@ -8471,6 +8475,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
+{"lxvprl", X(31,589), XX1_MASK, PPCVSXF, 0, {XTP, RA0, RB}},
{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
@@ -8512,6 +8517,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+{"lxvprll", X(31,621), XX1_MASK, PPCVSXF, 0, {XTP, RA0, RB}},
+
{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
@@ -8525,6 +8532,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
+{"stxvrl", X(31,653), XX1_MASK, PPCVSXF, 0, {XS6, RA0, RB}},
{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
@@ -8566,6 +8574,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+{"stxvrll", X(31,685), XX1_MASK, PPCVSXF, 0, {XS6, RA0, RB}},
+
{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
@@ -8588,6 +8598,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
+{"stxvprl", X(31,717), XX1_MASK, PPCVSXF, 0, {XSP, RA0, RB}},
{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
@@ -8645,6 +8656,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
+{"stxvprll", X(31,749), XX1_MASK, PPCVSXF, 0, {XSP, RA0, RB}},
+
{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, EXT, {0}},
{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, EXT, {0}},
{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
--
2.27.0
reply other threads:[~2022-12-07 17:59 UTC|newest]
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