From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id B62A13858D38 for ; Mon, 3 Oct 2022 04:31:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B62A13858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=irq.a4lg.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=irq.a4lg.com Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 709FF300089; Mon, 3 Oct 2022 04:31:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1664771476; bh=LdpB6ILQPLb77kuJ6ZGqxRmpYqtOWavLBrR97eBXfYA=; h=Message-ID:Date:Mime-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type:Content-Transfer-Encoding; b=BbgkaM1quBdi+3Dd/ziTTUmbThVQ0ZAC5wzlXCZ9xELG0Uz+6ka36fQcrl4SdTxOG 5TrIFOXhmnU/kLruicknXiBhqpGMLV8BA0Irunx8OWDwB8Iq5R4wFd5Fx4EbmNUdet MwzQ7um0jy+9rtOMgeeaCXPDA/F8y+uMReszL9a0= Message-ID: <9f63bceb-5536-5b17-3248-1dc17fa2e834@irq.a4lg.com> Date: Mon, 3 Oct 2022 13:31:14 +0900 Mime-Version: 1.0 Subject: Re: [PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers To: Nelson Chu , Jeff Law , Andrew Burgess Cc: binutils@sourceware.org References: <874jwni91f.fsf@redhat.com> <7cea93e7-f75b-2d5a-d63b-73288d4b3e5e@gmail.com> Content-Language: en-US From: Tsukasa OI In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Many thanks to all of you! Though I have to report that the exact changes you approved are merged but two commits are splitted differently (due to technical mistake I made; I mistakenly chose a "working" branch to push). Approved PATCH v3: - PATCH 1: Assign DWARF register numbers to vector ones - PATCH 2: Add DWARF register number testcases (GPRs/FPRs/vector) Merged commits: - COMMIT 1: Add DWARF register number testcases (GPRs/FPRs) - COMMIT 2: Assign DWARF register numbers to vector ones and add them to "existing" tests I repeat that changes (COMMIT 1+2) are the _exactly_ the same as PATCH 1+2 but splitted differently. Despite that this is functionally the same, this is clearly not obvious and I should have checked. I'll submit the remaining part (to add "fp" to DWARF register number testcases) as a separate patch but feel free to revert those two commits. In the event, I'll submit PATCH v4 of it. Regards, Tsukasa On 2022/10/03 10:36, Nelson Chu wrote: > On Sun, Oct 2, 2022 at 11:59 PM Jeff Law via Binutils > wrote: >> >> On 10/1/22 14:27, Andrew Burgess via Binutils wrote: >>> I can't approve binutils patches, but as this mentioned RISC-V and >>> DWARF, both of which I'm interested in, I took a look :) >>> >>> Both these patches look good to me. The register numbers align with the >>> spec, and the test makes sense. >> >> Well, that's the key property -- they align with the spec. >> >> >> I'm also not sure if I can approve for binutils, but if I can, OK for >> the trunk ;-) > > Thanks for your help, Andrew and Jeff! > > Hi Jeff, > > Of course! You are a global maintainer of both gcc and binutils. > Welcome and please feel free to approve any RISC-V binutils patch if > you are free and the patch looks good to you :-) > > Thanks! > Nelson >