* [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions.
@ 2024-07-04 12:40 Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 01/12] aarch64: Add support for sve2p1 orqv instruction Srinath Parvathaneni
` (12 more replies)
0 siblings, 13 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
Hi,
This patch series adds the support for remaining aarch64 sve2p1 instructions
and the spec can be found here [1].
Srinath Parvathaneni (12):
aarch64: Add support for sve2p1 orqv instruction.
aarch64: Add support for sve2p1 orqv instruction (regenerated files).
aarch64: Add support for sve2p1 tblq instruction.
aarch64: Add support for sve2p1 tblq instruction (regenerated files).
aarch64: Add support for sve2p1 uzpq[1-2] instructions.
aarch64: Add support for sve2p1 uzpq[1-2] instructions (regenerated files).
aarch64: Add support for sve2p1 zipq[1-2] instructions.
aarch64: Add support for sve2p1 zipq[1-2] instructions (regenerated files).
aarch64: Add support for sve2p1 tbxq instruction.
aarch64: Add support for sve2p1 tbxq instruction (regenerated files).
aarch64: Add support for sve2p1 pmov instruction.
aarch64: Add support for sve2p1 pmov instruction (regenerated files).
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
Ok for binutils-master?
Regards,
Srinath.
gas/config/tc-aarch64.c | 28 +-
gas/testsuite/gas/aarch64/sve2p1-5-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-5-invalid.l | 27 +
gas/testsuite/gas/aarch64/sve2p1-5-invalid.s | 8 +
gas/testsuite/gas/aarch64/sve2p1-5.d | 18 +
gas/testsuite/gas/aarch64/sve2p1-5.s | 8 +
gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 78 +++
gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 36 +
gas/testsuite/gas/aarch64/sve2p1-6.d | 58 ++
gas/testsuite/gas/aarch64/sve2p1-6.s | 53 ++
gas/testsuite/gas/aarch64/sve2p1-7-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-7-invalid.l | 118 ++++
gas/testsuite/gas/aarch64/sve2p1-7-invalid.s | 76 +++
gas/testsuite/gas/aarch64/sve2p1-7.d | 64 ++
gas/testsuite/gas/aarch64/sve2p1-7.s | 63 ++
include/opcode/aarch64.h | 8 +
opcodes/aarch64-asm-2.c | 40 +-
opcodes/aarch64-dis-2.c | 651 ++++++++++++-------
opcodes/aarch64-opc-2.c | 8 +
opcodes/aarch64-opc.c | 34 +-
opcodes/aarch64-opc.h | 2 +
opcodes/aarch64-tbl.h | 61 +-
23 files changed, 1183 insertions(+), 265 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.s
--
2.25.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 01/12] aarch64: Add support for sve2p1 orqv instruction.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 02/12] aarch64: Add support for sve2p1 orqv instruction (regenerated files) Srinath Parvathaneni
` (11 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 877 bytes --]
This patch adds support for SVE2p1 "orqv" instruction, spec available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sve2p1-5-invalid.d | 3 +++
gas/testsuite/gas/aarch64/sve2p1-5-invalid.l | 27 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-5-invalid.s | 8 ++++++
gas/testsuite/gas/aarch64/sve2p1-5.d | 18 +++++++++++++
gas/testsuite/gas/aarch64/sve2p1-5.s | 8 ++++++
opcodes/aarch64-tbl.h | 1 +
6 files changed, 65 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0001-aarch64-Add-support-for-sve2p1-orqv-instruction.patch --]
[-- Type: text/x-patch; name="v1-0001-aarch64-Add-support-for-sve2p1-orqv-instruction.patch", Size: 4166 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
new file mode 100644
index 00000000000..d28b059b244
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 orqv instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-5-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
new file mode 100644
index 00000000000..4cd75025da9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
@@ -0,0 +1,27 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `orqv v0.8h,p0,z0.b'
+.*: Info: did you mean this\?
+.*: Info: orqv v0.16b, p0, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: orqv v0.8h, p0, z0.h
+.*: Info: orqv v0.4s, p0, z0.s
+.*: Info: orqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `orqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `orqv v0.2d,p7,z0.b'
+.*: Info: did you mean this\?
+.*: Info: orqv v0.16b, p7, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: orqv v0.8h, p7, z0.h
+.*: Info: orqv v0.4s, p7, z0.s
+.*: Info: orqv v0.2d, p7, z0.d
+.*: Error: bad vector arrangement type at operand 1 -- `orqv v0.2b,p7,z0.b'
+.*: Error: indexed vector register expected at operand 1 -- `orqv v0.b,p0,z0.16b'
+.*: Error: unexpected character `8' in element size at operand 3 -- `orqv v0.4h,p0,z0.8h'
+.*: Error: unexpected character `4' in element size at operand 3 -- `orqv v0.4s,p8/m,z0.4s'
+.*: Error: operand mismatch -- `orqv v0.2d,p0/z,z0.d'
+.*: Info: did you mean this\?
+.*: Info: orqv v0.2d, p0, z0.d
+.*: Info: other valid variant\(s\):
+.*: Info: orqv v0.16b, p0, z0.b
+.*: Info: orqv v0.8h, p0, z0.h
+.*: Info: orqv v0.4s, p0, z0.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
new file mode 100644
index 00000000000..36edb878433
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
@@ -0,0 +1,8 @@
+orqv v0.8h, p0, z0.b
+orqv v31.16b, p8, z0.b
+orqv v0.2d, p7, z0.b
+orqv v0.2b, p7, z0.b
+orqv v0.b, p0, z0.16b
+orqv v0.4h, p0, z0.8h
+orqv v0.4s, p8/m, z0.4s
+orqv v0.2d, p0/z, z0.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.d b/gas/testsuite/gas/aarch64/sve2p1-5.d
new file mode 100644
index 00000000000..f581e345f58
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.d
@@ -0,0 +1,18 @@
+#name: Test of SVE2.1 orqv instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 041c2000 orqv v0.16b, p0, z0.b
+.*: 041c201f orqv v31.16b, p0, z0.b
+.*: 04dc2000 orqv v0.2d, p0, z0.d
+.*: 041c3c00 orqv v0.16b, p7, z0.b
+.*: 041c23e0 orqv v0.16b, p0, z31.b
+.*: 04dc3fff orqv v31.2d, p7, z31.d
+.*: 045c35ef orqv v15.8h, p5, z15.h
+.*: 049c2e8a orqv v10.4s, p3, z20.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.s b/gas/testsuite/gas/aarch64/sve2p1-5.s
new file mode 100644
index 00000000000..12f0b859751
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.s
@@ -0,0 +1,8 @@
+orqv v0.16b, p0, z0.b
+orqv v31.16b, p0, z0.b
+orqv v0.2d, p0, z0.d
+orqv v0.16b, p7, z0.b
+orqv v0.16b, p0, z31.b
+orqv v31.2d, p7, z31.d
+orqv v15.8h, p5, z15.h
+orqv v10.4s, p3, z20.s
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7ef9cea9119..81b23b3f369 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6640,6 +6640,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
+ SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 02/12] aarch64: Add support for sve2p1 orqv instruction (regenerated files).
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 01/12] aarch64: Add support for sve2p1 orqv instruction Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 03/12] aarch64: Add support for sve2p1 tblq instruction Srinath Parvathaneni
` (10 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 227 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sve2p1 orqv instruction.
---
opcodes/aarch64-dis-2.c | 447 ++++++++++++++++++++--------------------
1 file changed, 229 insertions(+), 218 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0002-aarch64-Add-support-for-sve2p1-orqv-instruction-r.patch --]
[-- Type: text/x-patch; name="v1-0002-aarch64-Add-support-for-sve2p1-orqv-instruction-r.patch", Size: 108079 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 49ca8239773..0175dd0127a 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3394;
+ return 3395;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3395;
+ return 3396;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3396;
+ return 3397;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3462;
+ return 3463;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3461;
+ return 3462;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3455;
+ return 3456;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3440;
+ return 3441;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3454;
+ return 3455;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3447;
+ return 3448;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3446;
+ return 3447;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3453;
+ return 3454;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3433;
+ return 3434;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3434;
+ return 3435;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3445;
+ return 3446;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3464;
+ return 3465;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3439;
+ return 3440;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3463;
+ return 3464;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3465;
+ return 3466;
}
else
{
@@ -3155,16 +3155,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3459;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx000xxxx10000x
- fmlall. */
return 3460;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxx10000x
+ fmlall. */
+ return 3461;
+ }
}
}
}
@@ -3218,16 +3218,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3457;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx000xxxxx00x1x
- fmlall. */
return 3458;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx000xxxxx00x1x
+ fmlall. */
+ return 3459;
+ }
}
}
else
@@ -3280,16 +3280,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3443;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxx100xxx
- fdot. */
return 3444;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx100xxx
+ fdot. */
+ return 3445;
+ }
}
}
}
@@ -3350,16 +3350,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3451;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001101xxxx10xx010xxxx1000xx
- fmlal. */
return 3452;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx010xxxx1000xx
+ fmlal. */
+ return 3453;
+ }
}
}
}
@@ -3413,16 +3413,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3449;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx010xxxxx001xx
- fmlal. */
return 3450;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx010xxxxx001xx
+ fmlal. */
+ return 3451;
+ }
}
}
else
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3456;
+ return 3457;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3448;
+ return 3449;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3397;
+ return 3398;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3398;
+ return 3399;
}
}
}
@@ -3739,16 +3739,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3437;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxx110xxx
- fdot. */
return 3438;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx110xxx
+ fdot. */
+ return 3439;
+ }
}
}
}
@@ -4038,16 +4038,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3441;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx01xxx
- fdot. */
return 3442;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3443;
+ }
}
}
else
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3399;
+ return 3400;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3400;
+ return 3401;
}
}
}
@@ -4398,16 +4398,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3435;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx11xxx
- fdot. */
return 3436;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3437;
+ }
}
}
else
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3371;
+ return 3372;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3368;
+ return 3369;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3363;
+ return 3364;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3369;
+ return 3370;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3370;
+ return 3371;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3364;
+ return 3365;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3365;
+ return 3366;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3359;
+ return 3360;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3360;
+ return 3361;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3366;
+ return 3367;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3367;
+ return 3368;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3361;
+ return 3362;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3362;
+ return 3363;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3373;
+ return 3374;
}
}
else
@@ -5774,7 +5774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3372;
+ return 3373;
}
else
{
@@ -5782,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3374;
+ return 3375;
}
}
}
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3375;
+ return 3376;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3376;
+ return 3377;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3377;
+ return 3378;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3378;
+ return 3379;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3379;
+ return 3380;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3381;
+ return 3382;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3380;
+ return 3381;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3382;
+ return 3383;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3384;
+ return 3385;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3383;
+ return 3384;
}
}
}
@@ -14312,11 +14312,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 16) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx0xx100001xxxxxxxxxxxxx
- smaxqv. */
- return 3308;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x0xx00x100001xxxxxxxxxxxxx
+ smaxqv. */
+ return 3308;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x0xx01x100001xxxxxxxxxxxxx
+ orqv. */
+ return 3319;
+ }
}
else
{
@@ -15153,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3320;
+ return 3321;
}
else
{
@@ -16630,7 +16641,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3329;
+ return 3330;
}
else
{
@@ -16640,7 +16651,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3328;
+ return 3329;
}
else
{
@@ -16648,7 +16659,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3330;
+ return 3331;
}
}
}
@@ -17314,7 +17325,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3321;
+ return 3322;
}
}
}
@@ -17450,7 +17461,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3324;
+ return 3325;
}
}
else
@@ -17595,7 +17606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3331;
+ return 3332;
}
}
else
@@ -17638,7 +17649,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3332;
+ return 3333;
}
}
else
@@ -17679,7 +17690,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3333;
+ return 3334;
}
}
}
@@ -17708,7 +17719,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3420;
+ return 3421;
}
}
else
@@ -17717,7 +17728,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3422;
+ return 3423;
}
}
else
@@ -17758,7 +17769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3432;
+ return 3433;
}
}
else
@@ -17791,7 +17802,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3418;
+ return 3419;
}
}
else
@@ -17862,7 +17873,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3423;
+ return 3424;
}
}
else
@@ -17871,7 +17882,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3419;
+ return 3420;
}
}
else
@@ -17880,7 +17891,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3424;
+ return 3425;
}
}
else
@@ -17889,7 +17900,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3425;
+ return 3426;
}
}
else
@@ -17916,7 +17927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3421;
+ return 3422;
}
}
else
@@ -17934,7 +17945,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3428;
+ return 3429;
}
}
else
@@ -17943,7 +17954,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3431;
+ return 3432;
}
}
else
@@ -17976,7 +17987,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3417;
+ return 3418;
}
}
else
@@ -17985,7 +17996,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3426;
+ return 3427;
}
}
else
@@ -18017,7 +18028,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3430;
+ return 3431;
}
}
else
@@ -18316,7 +18327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3327;
+ return 3328;
}
}
else
@@ -18331,7 +18342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3427;
+ return 3428;
}
else
{
@@ -18339,7 +18350,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3429;
+ return 3430;
}
}
else
@@ -19092,7 +19103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001x01xxxxxxxxxx
extq. */
- return 3319;
+ return 3320;
}
}
else
@@ -20695,7 +20706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3389;
+ return 3390;
}
}
else
@@ -20704,7 +20715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3390;
+ return 3391;
}
}
else
@@ -20717,16 +20728,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3391;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x1xx1xxxxx101101xxxxxxxxxx
- luti4. */
return 3392;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101101xxxxxxxxxx
+ luti4. */
+ return 3393;
+ }
}
else
{
@@ -20734,7 +20745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3393;
+ return 3394;
}
}
}
@@ -21685,7 +21696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3351;
+ return 3352;
}
else
{
@@ -21693,7 +21704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3347;
+ return 3348;
}
}
else
@@ -21704,7 +21715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3352;
+ return 3353;
}
else
{
@@ -21712,7 +21723,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3348;
+ return 3349;
}
}
}
@@ -21757,7 +21768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3356;
+ return 3357;
}
else
{
@@ -21765,7 +21776,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3355;
+ return 3356;
}
}
else
@@ -21776,7 +21787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3357;
+ return 3358;
}
else
{
@@ -21784,7 +21795,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3358;
+ return 3359;
}
}
}
@@ -21845,7 +21856,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3353;
+ return 3354;
}
else
{
@@ -21853,7 +21864,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3349;
+ return 3350;
}
}
else
@@ -21864,7 +21875,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3354;
+ return 3355;
}
else
{
@@ -21872,7 +21883,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3350;
+ return 3351;
}
}
}
@@ -23198,7 +23209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3322;
+ return 3323;
}
else
{
@@ -23206,7 +23217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3323;
+ return 3324;
}
}
}
@@ -24379,7 +24390,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3325;
+ return 3326;
}
else
{
@@ -24387,7 +24398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3326;
+ return 3327;
}
}
else
@@ -26452,7 +26463,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3385;
+ return 3386;
}
}
}
@@ -26466,16 +26477,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3387;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx100xxxxxxxxxx
- luti4. */
return 3388;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx100xxxxxxxxxx
+ luti4. */
+ return 3389;
+ }
}
else
{
@@ -26483,7 +26494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3386;
+ return 3387;
}
}
}
@@ -26599,7 +26610,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3409;
+ return 3410;
}
else
{
@@ -26607,7 +26618,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3411;
+ return 3412;
}
}
else
@@ -26618,7 +26629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3410;
+ return 3411;
}
else
{
@@ -26626,7 +26637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3412;
+ return 3413;
}
}
}
@@ -26714,7 +26725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3342;
+ return 3343;
}
else
{
@@ -26722,7 +26733,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3343;
+ return 3344;
}
}
else
@@ -26731,7 +26742,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3344;
+ return 3345;
}
}
}
@@ -26874,7 +26885,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3401;
+ return 3402;
}
else
{
@@ -26884,7 +26895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3403;
+ return 3404;
}
else
{
@@ -26894,7 +26905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3405;
+ return 3406;
}
else
{
@@ -26902,7 +26913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3406;
+ return 3407;
}
}
}
@@ -27176,7 +27187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3345;
+ return 3346;
}
}
}
@@ -28568,7 +28579,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3338;
+ return 3339;
}
else
{
@@ -28576,7 +28587,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3339;
+ return 3340;
}
}
else
@@ -28587,7 +28598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3334;
+ return 3335;
}
else
{
@@ -28595,7 +28606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3335;
+ return 3336;
}
}
}
@@ -28609,7 +28620,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3340;
+ return 3341;
}
else
{
@@ -28617,7 +28628,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3341;
+ return 3342;
}
}
else
@@ -28628,7 +28639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3336;
+ return 3337;
}
else
{
@@ -28636,7 +28647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3337;
+ return 3338;
}
}
}
@@ -30635,7 +30646,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3346;
+ return 3347;
}
}
}
@@ -32351,7 +32362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3402;
+ return 3403;
}
else
{
@@ -32381,7 +32392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3404;
+ return 3405;
}
else
{
@@ -32391,16 +32402,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3407;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x100111111xxxxxx0000x0xxxxxxxxxx
- fmlalt. */
return 3408;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111111xxxxxx0000x0xxxxxxxxxx
+ fmlalt. */
+ return 3409;
+ }
}
}
}
@@ -32941,7 +32952,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3413;
+ return 3414;
}
else
{
@@ -32949,7 +32960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3415;
+ return 3416;
}
}
else
@@ -32980,7 +32991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3414;
+ return 3415;
}
else
{
@@ -32988,7 +32999,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3416;
+ return 3417;
}
}
}
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 03/12] aarch64: Add support for sve2p1 tblq instruction.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 01/12] aarch64: Add support for sve2p1 orqv instruction Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 02/12] aarch64: Add support for sve2p1 orqv instruction (regenerated files) Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 04/12] aarch64: Add support for sve2p1 tblq instruction (regenerated files) Srinath Parvathaneni
` (9 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 885 bytes --]
This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 3 +++
gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 18 ++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 6 ++++++
gas/testsuite/gas/aarch64/sve2p1-6.d | 18 ++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-6.s | 8 ++++++++
opcodes/aarch64-tbl.h | 1 +
6 files changed, 54 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0003-aarch64-Add-support-for-sve2p1-tblq-instruction.patch --]
[-- Type: text/x-patch; name="v1-0003-aarch64-Add-support-for-sve2p1-tblq-instruction.patch", Size: 3804 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
new file mode 100644
index 00000000000..1aa2b39f857
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
new file mode 100644
index 00000000000..0fea3255db4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -0,0 +1,18 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `tblq z0.s,{z0.b},z0.b'
+.*: Info: did you mean this\?
+.*: Info: tblq z0.b, {z0.b}, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: tblq z0.h, {z0.h}, z0.h
+.*: Info: tblq z0.s, {z0.s}, z0.s
+.*: Info: tblq z0.d, {z0.d}, z0.d
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected a single-register list at operand 2 -- `tblq z0.s,{z0.s-z1.s},z0.s'
+.*: Error: operand mismatch -- `tblq z0.s,{z31.s},z0.b'
+.*: Info: did you mean this\?
+.*: Info: tblq z0.s, {z31.s}, z0.s
+.*: Info: other valid variant\(s\):
+.*: Info: tblq z0.b, {z31.b}, z0.b
+.*: Info: tblq z0.h, {z31.h}, z0.h
+.*: Info: tblq z0.d, {z31.d}, z0.d
+.*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
new file mode 100644
index 00000000000..0f8300e385c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -0,0 +1,6 @@
+tblq z0.s, {z0.b}, z0.b
+tblq z31.b, z0.b, z0.b
+tblq z0.s, {z0.s, z1.s}, z0.s
+tblq z0.s, {z0.s - z1.s}, z0.s
+tblq z0.s, {z31.s}, z0.b
+tblq z0.b, {z0.b}, {z31.b}
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
new file mode 100644
index 00000000000..d146903c4a7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -0,0 +1,18 @@
+#name: Test of SVE2.1 TBLQ instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 4400f800 tblq z0.b, {z0.b}, z0.b
+.*: 4400f81f tblq z31.b, {z0.b}, z0.b
+.*: 44c0f800 tblq z0.d, {z0.d}, z0.d
+.*: 4400fbe0 tblq z0.b, {z31.b}, z0.b
+.*: 441ff800 tblq z0.b, {z0.b}, z31.b
+.*: 44dffbff tblq z31.d, {z31.d}, z31.d
+.*: 444ff945 tblq z5.h, {z10.h}, z15.h
+.*: 4487f861 tblq z1.s, {z3.s}, z7.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
new file mode 100644
index 00000000000..d2a0ef5fedf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -0,0 +1,8 @@
+tblq z0.b, {z0.b}, z0.b
+tblq z31.b, {z0.b}, z0.b
+tblq z0.d, {z0.d}, z0.d
+tblq z0.b, {z31.b}, z0.b
+tblq z0.b, {z0.b}, z31.b
+tblq z31.d, {z31.d}, z31.d
+tblq z5.h, {z10.h}, z15.h
+tblq z1.s, {z3.s}, z7.s
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 81b23b3f369..56a6c9d6e82 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6641,6 +6641,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 04/12] aarch64: Add support for sve2p1 tblq instruction (regenerated files).
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (2 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 03/12] aarch64: Add support for sve2p1 tblq instruction Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 05/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions Srinath Parvathaneni
` (8 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 227 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sve2p1 tblq instruction.
---
opcodes/aarch64-dis-2.c | 493 ++++++++++++++++++++--------------------
1 file changed, 252 insertions(+), 241 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0004-aarch64-Add-support-for-sve2p1-tblq-instruction-r.patch --]
[-- Type: text/x-patch; name="v1-0004-aarch64-Add-support-for-sve2p1-tblq-instruction-r.patch", Size: 111574 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 0175dd0127a..5fadd4b2b00 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3395;
+ return 3396;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3396;
+ return 3397;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3397;
+ return 3398;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3463;
+ return 3464;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3462;
+ return 3463;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3456;
+ return 3457;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3441;
+ return 3442;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3455;
+ return 3456;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3448;
+ return 3449;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3447;
+ return 3448;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3454;
+ return 3455;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3434;
+ return 3435;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3435;
+ return 3436;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3446;
+ return 3447;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3465;
+ return 3466;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3440;
+ return 3441;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3464;
+ return 3465;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3466;
+ return 3467;
}
else
{
@@ -3155,16 +3155,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3460;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx000xxxx10000x
- fmlall. */
return 3461;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxx10000x
+ fmlall. */
+ return 3462;
+ }
}
}
}
@@ -3218,16 +3218,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3458;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx000xxxxx00x1x
- fmlall. */
return 3459;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx000xxxxx00x1x
+ fmlall. */
+ return 3460;
+ }
}
}
else
@@ -3280,16 +3280,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3444;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxx100xxx
- fdot. */
return 3445;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx100xxx
+ fdot. */
+ return 3446;
+ }
}
}
}
@@ -3350,16 +3350,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3452;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001101xxxx10xx010xxxx1000xx
- fmlal. */
return 3453;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx010xxxx1000xx
+ fmlal. */
+ return 3454;
+ }
}
}
}
@@ -3413,16 +3413,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3450;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx010xxxxx001xx
- fmlal. */
return 3451;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx010xxxxx001xx
+ fmlal. */
+ return 3452;
+ }
}
}
else
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3457;
+ return 3458;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3449;
+ return 3450;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3398;
+ return 3399;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3399;
+ return 3400;
}
}
}
@@ -3739,16 +3739,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3438;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxx110xxx
- fdot. */
return 3439;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx110xxx
+ fdot. */
+ return 3440;
+ }
}
}
}
@@ -4038,16 +4038,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3442;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx01xxx
- fdot. */
return 3443;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3444;
+ }
}
}
else
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3400;
+ return 3401;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3401;
+ return 3402;
}
}
}
@@ -4398,16 +4398,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3436;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx11xxx
- fdot. */
return 3437;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3438;
+ }
}
}
else
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3372;
+ return 3373;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3369;
+ return 3370;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3364;
+ return 3365;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3370;
+ return 3371;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3371;
+ return 3372;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3365;
+ return 3366;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3366;
+ return 3367;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3360;
+ return 3361;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3361;
+ return 3362;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3367;
+ return 3368;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3368;
+ return 3369;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3362;
+ return 3363;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3363;
+ return 3364;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3374;
+ return 3375;
}
}
else
@@ -5774,7 +5774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3373;
+ return 3374;
}
else
{
@@ -5782,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3375;
+ return 3376;
}
}
}
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3376;
+ return 3377;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3377;
+ return 3378;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3378;
+ return 3379;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3379;
+ return 3380;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3380;
+ return 3381;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3382;
+ return 3383;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3381;
+ return 3382;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3383;
+ return 3384;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3385;
+ return 3386;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3384;
+ return 3385;
}
}
}
@@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3321;
+ return 3322;
}
else
{
@@ -16168,42 +16168,53 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x0000xxxxx111xxxxxxxxxxxxx
- prfb. */
- return 1836;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x0100xxxxx111xxxxxxxxxxxxx
- prfh. */
- return 1850;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx111xxxxxxxxxxxxx
+ tblq. */
+ return 3320;
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x0010xxxxx111xxxxxxxxxxxxx
- ldff1b. */
- return 1699;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0000xxxxx111xxxxxxxxxxxxx
+ prfb. */
+ return 1836;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0100xxxxx111xxxxxxxxxxxxx
+ prfh. */
+ return 1850;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x0110xxxxx111xxxxxxxxxxxxx
- ldff1h. */
- return 1719;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0010xxxxx111xxxxxxxxxxxxx
+ ldff1b. */
+ return 1699;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0110xxxxx111xxxxxxxxxxxxx
+ ldff1h. */
+ return 1719;
+ }
}
}
}
@@ -16641,7 +16652,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3330;
+ return 3331;
}
else
{
@@ -16651,7 +16662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3329;
+ return 3330;
}
else
{
@@ -16659,7 +16670,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3331;
+ return 3332;
}
}
}
@@ -17325,7 +17336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3322;
+ return 3323;
}
}
}
@@ -17461,7 +17472,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3325;
+ return 3326;
}
}
else
@@ -17606,7 +17617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3332;
+ return 3333;
}
}
else
@@ -17649,7 +17660,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3333;
+ return 3334;
}
}
else
@@ -17690,7 +17701,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3334;
+ return 3335;
}
}
}
@@ -17719,7 +17730,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3421;
+ return 3422;
}
}
else
@@ -17728,7 +17739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3423;
+ return 3424;
}
}
else
@@ -17769,7 +17780,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3433;
+ return 3434;
}
}
else
@@ -17802,7 +17813,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3419;
+ return 3420;
}
}
else
@@ -17873,7 +17884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3424;
+ return 3425;
}
}
else
@@ -17882,7 +17893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3420;
+ return 3421;
}
}
else
@@ -17891,7 +17902,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3425;
+ return 3426;
}
}
else
@@ -17900,7 +17911,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3426;
+ return 3427;
}
}
else
@@ -17927,7 +17938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3422;
+ return 3423;
}
}
else
@@ -17945,7 +17956,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3429;
+ return 3430;
}
}
else
@@ -17954,7 +17965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3432;
+ return 3433;
}
}
else
@@ -17987,7 +17998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3418;
+ return 3419;
}
}
else
@@ -17996,7 +18007,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3427;
+ return 3428;
}
}
else
@@ -18028,7 +18039,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3431;
+ return 3432;
}
}
else
@@ -18327,7 +18338,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3328;
+ return 3329;
}
}
else
@@ -18342,7 +18353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3428;
+ return 3429;
}
else
{
@@ -18350,7 +18361,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3430;
+ return 3431;
}
}
else
@@ -19103,7 +19114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1x11xxxxx001x01xxxxxxxxxx
extq. */
- return 3320;
+ return 3321;
}
}
else
@@ -20706,7 +20717,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3390;
+ return 3391;
}
}
else
@@ -20715,7 +20726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3391;
+ return 3392;
}
}
else
@@ -20728,16 +20739,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3392;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x1xx1xxxxx101101xxxxxxxxxx
- luti4. */
return 3393;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101101xxxxxxxxxx
+ luti4. */
+ return 3394;
+ }
}
else
{
@@ -20745,7 +20756,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3394;
+ return 3395;
}
}
}
@@ -21696,7 +21707,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3352;
+ return 3353;
}
else
{
@@ -21704,7 +21715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3348;
+ return 3349;
}
}
else
@@ -21715,7 +21726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3353;
+ return 3354;
}
else
{
@@ -21723,7 +21734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3349;
+ return 3350;
}
}
}
@@ -21768,7 +21779,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3357;
+ return 3358;
}
else
{
@@ -21776,7 +21787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3356;
+ return 3357;
}
}
else
@@ -21787,7 +21798,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3358;
+ return 3359;
}
else
{
@@ -21795,7 +21806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3359;
+ return 3360;
}
}
}
@@ -21856,7 +21867,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3354;
+ return 3355;
}
else
{
@@ -21864,7 +21875,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3350;
+ return 3351;
}
}
else
@@ -21875,7 +21886,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3355;
+ return 3356;
}
else
{
@@ -21883,7 +21894,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3351;
+ return 3352;
}
}
}
@@ -23209,7 +23220,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3323;
+ return 3324;
}
else
{
@@ -23217,7 +23228,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3324;
+ return 3325;
}
}
}
@@ -24390,7 +24401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3326;
+ return 3327;
}
else
{
@@ -24398,7 +24409,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3327;
+ return 3328;
}
}
else
@@ -26463,7 +26474,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3386;
+ return 3387;
}
}
}
@@ -26477,16 +26488,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3388;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx100xxxxxxxxxx
- luti4. */
return 3389;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx100xxxxxxxxxx
+ luti4. */
+ return 3390;
+ }
}
else
{
@@ -26494,7 +26505,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3387;
+ return 3388;
}
}
}
@@ -26610,7 +26621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3410;
+ return 3411;
}
else
{
@@ -26618,7 +26629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3412;
+ return 3413;
}
}
else
@@ -26629,7 +26640,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3411;
+ return 3412;
}
else
{
@@ -26637,7 +26648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3413;
+ return 3414;
}
}
}
@@ -26725,7 +26736,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3343;
+ return 3344;
}
else
{
@@ -26733,7 +26744,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3344;
+ return 3345;
}
}
else
@@ -26742,7 +26753,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3345;
+ return 3346;
}
}
}
@@ -26885,7 +26896,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3402;
+ return 3403;
}
else
{
@@ -26895,7 +26906,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3404;
+ return 3405;
}
else
{
@@ -26905,7 +26916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3406;
+ return 3407;
}
else
{
@@ -26913,7 +26924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3407;
+ return 3408;
}
}
}
@@ -27187,7 +27198,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3346;
+ return 3347;
}
}
}
@@ -28579,7 +28590,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3339;
+ return 3340;
}
else
{
@@ -28587,7 +28598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3340;
+ return 3341;
}
}
else
@@ -28598,7 +28609,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3335;
+ return 3336;
}
else
{
@@ -28606,7 +28617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3336;
+ return 3337;
}
}
}
@@ -28620,7 +28631,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3341;
+ return 3342;
}
else
{
@@ -28628,7 +28639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3342;
+ return 3343;
}
}
else
@@ -28639,7 +28650,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3337;
+ return 3338;
}
else
{
@@ -28647,7 +28658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3338;
+ return 3339;
}
}
}
@@ -30646,7 +30657,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3347;
+ return 3348;
}
}
}
@@ -32362,7 +32373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3403;
+ return 3404;
}
else
{
@@ -32392,7 +32403,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3405;
+ return 3406;
}
else
{
@@ -32402,16 +32413,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3408;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x100111111xxxxxx0000x0xxxxxxxxxx
- fmlalt. */
return 3409;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111111xxxxxx0000x0xxxxxxxxxx
+ fmlalt. */
+ return 3410;
+ }
}
}
}
@@ -32952,7 +32963,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3414;
+ return 3415;
}
else
{
@@ -32960,7 +32971,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3416;
+ return 3417;
}
}
else
@@ -32991,7 +33002,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3415;
+ return 3416;
}
else
{
@@ -32999,7 +33010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3417;
+ return 3418;
}
}
}
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 05/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (3 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 04/12] aarch64: Add support for sve2p1 tblq instruction (regenerated files) Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 06/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions (regenerated files) Srinath Parvathaneni
` (7 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 615 bytes --]
This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is
available here [1]
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 2 +-
gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 24 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 12 ++++++++++
gas/testsuite/gas/aarch64/sve2p1-6.d | 18 ++++++++++++++-
gas/testsuite/gas/aarch64/sve2p1-6.s | 18 +++++++++++++++
opcodes/aarch64-tbl.h | 2 ++
6 files changed, 74 insertions(+), 2 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0005-aarch64-Add-support-for-sve2p1-uzpq-1-2-instructi.patch --]
[-- Type: text/x-patch; name="v1-0005-aarch64-Add-support-for-sve2p1-uzpq-1-2-instructi.patch", Size: 6043 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
index 1aa2b39f857..0971a587815 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -1,3 +1,3 @@
-#name: Test of illegal SVE2.1 TBLQ instruction.
+#name: Test of illegal SVE2.1 tblq, uzpq1 and uzpq2 instruction.
#as: -march=armv9.4-a
#error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
index 0fea3255db4..c784ca6c891 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -16,3 +16,27 @@
.*: Info: tblq z0.h, {z31.h}, z0.h
.*: Info: tblq z0.d, {z31.d}, z0.d
.*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `uzpq1 z31.s,z0.b,z0.h'
+.*: Info: did you mean this\?
+.*: Info: uzpq1 z31.b, z0.b, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: uzpq1 z31.h, z0.h, z0.h
+.*: Info: uzpq1 z31.s, z0.s, z0.s
+.*: Info: uzpq1 z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.h,{z0.h-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `uzpq1 {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `uzpq2 z31.s,z0.b,z0.h'
+.*: Info: did you mean this\?
+.*: Info: uzpq2 z31.b, z0.b, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: uzpq2 z31.h, z0.h, z0.h
+.*: Info: uzpq2 z31.s, z0.s, z0.s
+.*: Info: uzpq2 z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.h,{z0.h-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `uzpq2 {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.b,{z0.b},{z31.b}'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
index 0f8300e385c..8a6df867726 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -4,3 +4,15 @@ tblq z0.s, {z0.s, z1.s}, z0.s
tblq z0.s, {z0.s - z1.s}, z0.s
tblq z0.s, {z31.s}, z0.b
tblq z0.b, {z0.b}, {z31.b}
+uzpq1 z0.s, {z0.b}, z0.b
+uzpq1 z31.s, z0.b, z0.h
+uzpq1 z0.s, {z0.s, z1.s}, z0.s
+uzpq1 z0.h, {z0.h - z1.h}, z0.h
+uzpq1 {z0.s}, z31.s, z0.b
+uzpq1 z0.b, {z0.b}, {z31.b}
+uzpq2 z0.s, {z0.b}, z0.b
+uzpq2 z31.s, z0.b, z0.h
+uzpq2 z0.s, {z0.s, z1.s}, z0.s
+uzpq2 z0.h, {z0.h - z1.h}, z0.h
+uzpq2 {z0.s}, z31.s, z0.b
+uzpq2 z0.b, {z0.b}, {z31.b}
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
index d146903c4a7..b36515f234c 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -1,4 +1,4 @@
-#name: Test of SVE2.1 TBLQ instruction.
+#name: Test of SVE2.1 tblq, uzpq1 and uzpq2 instruction.
#as: -march=armv9.4-a
#objdump: -dr
@@ -16,3 +16,19 @@
.*: 44dffbff tblq z31.d, {z31.d}, z31.d
.*: 444ff945 tblq z5.h, {z10.h}, z15.h
.*: 4487f861 tblq z1.s, {z3.s}, z7.s
+.*: 4400e800 uzpq1 z0.b, z0.b, z0.b
+.*: 4400e81f uzpq1 z31.b, z0.b, z0.b
+.*: 44c0e800 uzpq1 z0.d, z0.d, z0.d
+.*: 4400ebe0 uzpq1 z0.b, z31.b, z0.b
+.*: 441fe800 uzpq1 z0.b, z0.b, z31.b
+.*: 44dfebff uzpq1 z31.d, z31.d, z31.d
+.*: 448fe945 uzpq1 z5.s, z10.s, z15.s
+.*: 4454e9ea uzpq1 z10.h, z15.h, z20.h
+.*: 4400ec00 uzpq2 z0.b, z0.b, z0.b
+.*: 4400ec1f uzpq2 z31.b, z0.b, z0.b
+.*: 44c0ec00 uzpq2 z0.d, z0.d, z0.d
+.*: 4400efe0 uzpq2 z0.b, z31.b, z0.b
+.*: 441fec00 uzpq2 z0.b, z0.b, z31.b
+.*: 44dfefff uzpq2 z31.d, z31.d, z31.d
+.*: 448fed45 uzpq2 z5.s, z10.s, z15.s
+.*: 4454edea uzpq2 z10.h, z15.h, z20.h
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
index d2a0ef5fedf..b8c6ed72a89 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -6,3 +6,21 @@ tblq z0.b, {z0.b}, z31.b
tblq z31.d, {z31.d}, z31.d
tblq z5.h, {z10.h}, z15.h
tblq z1.s, {z3.s}, z7.s
+
+uzpq1 z0.b, z0.b, z0.b
+uzpq1 z31.b, z0.b, z0.b
+uzpq1 z0.d, z0.d, z0.d
+uzpq1 z0.b, z31.b, z0.b
+uzpq1 z0.b, z0.b, z31.b
+uzpq1 z31.d, z31.d, z31.d
+uzpq1 z5.s, z10.s, z15.s
+uzpq1 z10.h, z15.h, z20.h
+
+uzpq2 z0.b, z0.b, z0.b
+uzpq2 z31.b, z0.b, z0.b
+uzpq2 z0.d, z0.d, z0.d
+uzpq2 z0.b, z31.b, z0.b
+uzpq2 z0.b, z0.b, z31.b
+uzpq2 z31.d, z31.d, z31.d
+uzpq2 z5.s, z10.s, z15.s
+uzpq2 z10.h, z15.h, z20.h
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 56a6c9d6e82..7089f167552 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6643,6 +6643,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
+ SVE2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 06/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions (regenerated files).
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (4 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 05/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 07/12] aarch64: Add support for sve2p1 zipq[1-2] instructions Srinath Parvathaneni
` (6 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 233 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sve2p1 uzpq[1-2] instructions.
---
opcodes/aarch64-dis-2.c | 408 +++++++++++++++++++++-------------------
1 file changed, 215 insertions(+), 193 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0006-aarch64-Add-support-for-sve2p1-uzpq-1-2-instructi.patch --]
[-- Type: text/x-patch; name="v1-0006-aarch64-Add-support-for-sve2p1-uzpq-1-2-instructi.patch", Size: 105155 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 5fadd4b2b00..b31ab44e03f 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3396;
+ return 3398;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3397;
+ return 3399;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3398;
+ return 3400;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3464;
+ return 3466;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3463;
+ return 3465;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3457;
+ return 3459;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3442;
+ return 3444;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3456;
+ return 3458;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3449;
+ return 3451;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3448;
+ return 3450;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3455;
+ return 3457;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3435;
+ return 3437;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3436;
+ return 3438;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3447;
+ return 3449;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3466;
+ return 3468;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3441;
+ return 3443;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3465;
+ return 3467;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3467;
+ return 3469;
}
else
{
@@ -3155,7 +3155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3461;
+ return 3463;
}
else
{
@@ -3163,7 +3163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3462;
+ return 3464;
}
}
}
@@ -3218,7 +3218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3459;
+ return 3461;
}
else
{
@@ -3226,7 +3226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3460;
+ return 3462;
}
}
}
@@ -3280,7 +3280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3445;
+ return 3447;
}
else
{
@@ -3288,7 +3288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3446;
+ return 3448;
}
}
}
@@ -3350,7 +3350,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3453;
+ return 3455;
}
else
{
@@ -3358,7 +3358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3454;
+ return 3456;
}
}
}
@@ -3413,7 +3413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3451;
+ return 3453;
}
else
{
@@ -3421,7 +3421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3452;
+ return 3454;
}
}
}
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3458;
+ return 3460;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3450;
+ return 3452;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3399;
+ return 3401;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3400;
+ return 3402;
}
}
}
@@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3439;
+ return 3441;
}
else
{
@@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3440;
+ return 3442;
}
}
}
@@ -4038,7 +4038,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3443;
+ return 3445;
}
else
{
@@ -4046,7 +4046,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3444;
+ return 3446;
}
}
}
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3401;
+ return 3403;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3402;
+ return 3404;
}
}
}
@@ -4398,7 +4398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3437;
+ return 3439;
}
else
{
@@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3438;
+ return 3440;
}
}
}
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3373;
+ return 3375;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3370;
+ return 3372;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3365;
+ return 3367;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3371;
+ return 3373;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3372;
+ return 3374;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3366;
+ return 3368;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3367;
+ return 3369;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3361;
+ return 3363;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3362;
+ return 3364;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3368;
+ return 3370;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3369;
+ return 3371;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3363;
+ return 3365;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3364;
+ return 3366;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3375;
+ return 3377;
}
}
else
@@ -5774,16 +5774,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3374;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1110xx100xxxx0
- fscale. */
return 3376;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1110xx100xxxx0
+ fscale. */
+ return 3378;
+ }
}
}
else
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3377;
+ return 3379;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3378;
+ return 3380;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3379;
+ return 3381;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3380;
+ return 3382;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3381;
+ return 3383;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3383;
+ return 3385;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3382;
+ return 3384;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3384;
+ return 3386;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3386;
+ return 3388;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3385;
+ return 3387;
}
}
}
@@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3322;
+ return 3324;
}
else
{
@@ -16170,11 +16170,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx111xxxxxxxxxxxxx
- tblq. */
- return 3320;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx1110x0xxxxxxxxxx
+ uzpq1. */
+ return 3322;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx1111x0xxxxxxxxxx
+ tblq. */
+ return 3320;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx111xx1xxxxxxxxxx
+ uzpq2. */
+ return 3323;
+ }
}
else
{
@@ -16652,7 +16674,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3331;
+ return 3333;
}
else
{
@@ -16662,16 +16684,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3330;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x0110xxxxx000xxxxxxxxxxxxx
- st4q. */
return 3332;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x0110xxxxx000xxxxxxxxxxxxx
+ st4q. */
+ return 3334;
+ }
}
}
else
@@ -17336,7 +17358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3323;
+ return 3325;
}
}
}
@@ -17472,7 +17494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3326;
+ return 3328;
}
}
else
@@ -17617,7 +17639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3333;
+ return 3335;
}
}
else
@@ -17660,7 +17682,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3334;
+ return 3336;
}
}
else
@@ -17701,7 +17723,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3335;
+ return 3337;
}
}
}
@@ -17730,7 +17752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3422;
+ return 3424;
}
}
else
@@ -17739,7 +17761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3424;
+ return 3426;
}
}
else
@@ -17780,7 +17802,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3434;
+ return 3436;
}
}
else
@@ -17813,7 +17835,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3420;
+ return 3422;
}
}
else
@@ -17884,7 +17906,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3425;
+ return 3427;
}
}
else
@@ -17893,7 +17915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3421;
+ return 3423;
}
}
else
@@ -17902,7 +17924,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3426;
+ return 3428;
}
}
else
@@ -17911,7 +17933,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3427;
+ return 3429;
}
}
else
@@ -17938,7 +17960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3423;
+ return 3425;
}
}
else
@@ -17956,7 +17978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3430;
+ return 3432;
}
}
else
@@ -17965,7 +17987,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3433;
+ return 3435;
}
}
else
@@ -17998,7 +18020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3419;
+ return 3421;
}
}
else
@@ -18007,7 +18029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3428;
+ return 3430;
}
}
else
@@ -18039,7 +18061,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3432;
+ return 3434;
}
}
else
@@ -18338,7 +18360,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3329;
+ return 3331;
}
}
else
@@ -18353,16 +18375,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3429;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0001xxxxx1011xxxxxxxxxxxx
- fmlalltt. */
return 3431;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1011xxxxxxxxxxxx
+ fmlalltt. */
+ return 3433;
+ }
}
else
{
@@ -20717,7 +20739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3391;
+ return 3393;
}
}
else
@@ -20726,7 +20748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3392;
+ return 3394;
}
}
else
@@ -20739,7 +20761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3393;
+ return 3395;
}
else
{
@@ -20747,7 +20769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3394;
+ return 3396;
}
}
else
@@ -20756,7 +20778,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3395;
+ return 3397;
}
}
}
@@ -21707,7 +21729,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3353;
+ return 3355;
}
else
{
@@ -21715,7 +21737,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3349;
+ return 3351;
}
}
else
@@ -21726,7 +21748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3354;
+ return 3356;
}
else
{
@@ -21734,7 +21756,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3350;
+ return 3352;
}
}
}
@@ -21779,7 +21801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3358;
+ return 3360;
}
else
{
@@ -21787,7 +21809,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3357;
+ return 3359;
}
}
else
@@ -21798,7 +21820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3359;
+ return 3361;
}
else
{
@@ -21806,7 +21828,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3360;
+ return 3362;
}
}
}
@@ -21867,7 +21889,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3355;
+ return 3357;
}
else
{
@@ -21875,7 +21897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3351;
+ return 3353;
}
}
else
@@ -21886,7 +21908,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3356;
+ return 3358;
}
else
{
@@ -21894,7 +21916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3352;
+ return 3354;
}
}
}
@@ -23220,7 +23242,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3324;
+ return 3326;
}
else
{
@@ -23228,7 +23250,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3325;
+ return 3327;
}
}
}
@@ -24401,7 +24423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3327;
+ return 3329;
}
else
{
@@ -24409,7 +24431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3328;
+ return 3330;
}
}
else
@@ -26474,29 +26496,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3387;
- }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx000xxxxxxxxxx
- luti4. */
return 3389;
}
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx000xxxxxxxxxx
+ luti4. */
+ return 3391;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3390;
+ return 3392;
}
}
else
@@ -26505,7 +26527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3388;
+ return 3390;
}
}
}
@@ -26621,7 +26643,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3411;
+ return 3413;
}
else
{
@@ -26629,7 +26651,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3413;
+ return 3415;
}
}
else
@@ -26640,7 +26662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3412;
+ return 3414;
}
else
{
@@ -26648,7 +26670,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3414;
+ return 3416;
}
}
}
@@ -26736,7 +26758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3344;
+ return 3346;
}
else
{
@@ -26744,7 +26766,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3345;
+ return 3347;
}
}
else
@@ -26753,7 +26775,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3346;
+ return 3348;
}
}
}
@@ -26896,7 +26918,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3403;
+ return 3405;
}
else
{
@@ -26906,7 +26928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3405;
+ return 3407;
}
else
{
@@ -26916,7 +26938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3407;
+ return 3409;
}
else
{
@@ -26924,7 +26946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3408;
+ return 3410;
}
}
}
@@ -27198,7 +27220,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3347;
+ return 3349;
}
}
}
@@ -28590,7 +28612,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3340;
+ return 3342;
}
else
{
@@ -28598,7 +28620,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3341;
+ return 3343;
}
}
else
@@ -28609,7 +28631,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3336;
+ return 3338;
}
else
{
@@ -28617,7 +28639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3337;
+ return 3339;
}
}
}
@@ -28631,7 +28653,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3342;
+ return 3344;
}
else
{
@@ -28639,7 +28661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3343;
+ return 3345;
}
}
else
@@ -28650,7 +28672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3338;
+ return 3340;
}
else
{
@@ -28658,7 +28680,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3339;
+ return 3341;
}
}
}
@@ -30657,7 +30679,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3348;
+ return 3350;
}
}
}
@@ -32373,7 +32395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3404;
+ return 3406;
}
else
{
@@ -32403,7 +32425,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3406;
+ return 3408;
}
else
{
@@ -32413,7 +32435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3409;
+ return 3411;
}
else
{
@@ -32421,7 +32443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3410;
+ return 3412;
}
}
}
@@ -32963,16 +32985,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3415;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x110111100xxxxxx1000x0xxxxxxxxxx
- fmlalltb. */
return 3417;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110111100xxxxxx1000x0xxxxxxxxxx
+ fmlalltb. */
+ return 3419;
+ }
}
else
{
@@ -33002,16 +33024,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3416;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1101111x1xxxxxx1000x0xxxxxxxxxx
- fmlalltt. */
return 3418;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101111x1xxxxxx1000x0xxxxxxxxxx
+ fmlalltt. */
+ return 3420;
+ }
}
}
}
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 07/12] aarch64: Add support for sve2p1 zipq[1-2] instructions.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (5 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 06/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 08/12] aarch64: Add support for sve2p1 zipq[1-2] instructions (regenerated files) Srinath Parvathaneni
` (5 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 616 bytes --]
This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is
available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 2 +-
gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 24 ++++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 12 ++++++++++
gas/testsuite/gas/aarch64/sve2p1-6.d | 18 ++++++++++++++-
gas/testsuite/gas/aarch64/sve2p1-6.s | 18 +++++++++++++++
opcodes/aarch64-tbl.h | 2 ++
6 files changed, 74 insertions(+), 2 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0007-aarch64-Add-support-for-sve2p1-zipq-1-2-instructi.patch --]
[-- Type: text/x-patch; name="v1-0007-aarch64-Add-support-for-sve2p1-zipq-1-2-instructi.patch", Size: 6186 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
index 0971a587815..db35ae7acb3 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -1,3 +1,3 @@
-#name: Test of illegal SVE2.1 tblq, uzpq1 and uzpq2 instruction.
+#name: Test of illegal SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
#as: -march=armv9.4-a
#error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
index c784ca6c891..55987acc8b0 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -40,3 +40,27 @@
.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.h,{z0.h-z1.h},z0.h'
.*: Error: expected an SVE vector register at operand 1 -- `uzpq2 {z0.s},z31.s,z0.b'
.*: Error: expected an SVE vector register at operand 2 -- `uzpq2 z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `zipq1 z31.s,z0.b,z0.h'
+.*: Info: did you mean this\?
+.*: Info: zipq1 z31.b, z0.b, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: zipq1 z31.h, z0.h, z0.h
+.*: Info: zipq1 z31.s, z0.s, z0.s
+.*: Info: zipq1 z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.h,{z0.b-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `zipq1 {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq1 z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `zipq2 z31.s,z0.b,z0.h'
+.*: Info: did you mean this\?
+.*: Info: zipq2 z31.b, z0.b, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: zipq2 z31.h, z0.h, z0.h
+.*: Info: zipq2 z31.s, z0.s, z0.s
+.*: Info: zipq2 z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.h,{z0.b-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `zipq2 {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `zipq2 z0.b,{z0.b},{z31.b}'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
index 8a6df867726..f79dfac78d4 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -16,3 +16,15 @@ uzpq2 z0.s, {z0.s, z1.s}, z0.s
uzpq2 z0.h, {z0.h - z1.h}, z0.h
uzpq2 {z0.s}, z31.s, z0.b
uzpq2 z0.b, {z0.b}, {z31.b}
+zipq1 z0.s, {z0.b}, z0.b
+zipq1 z31.s, z0.b, z0.h
+zipq1 z0.s, {z0.s, z1.s}, z0.s
+zipq1 z0.h, {z0.b - z1.h}, z0.h
+zipq1 {z0.s}, z31.s, z0.b
+zipq1 z0.b, {z0.b}, {z31.b}
+zipq2 z0.s, {z0.b}, z0.b
+zipq2 z31.s, z0.b, z0.h
+zipq2 z0.s, {z0.s, z1.s}, z0.s
+zipq2 z0.h, {z0.b - z1.h}, z0.h
+zipq2 {z0.s}, z31.s, z0.b
+zipq2 z0.b, {z0.b}, {z31.b}
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
index b36515f234c..83ba1426135 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -1,4 +1,4 @@
-#name: Test of SVE2.1 tblq, uzpq1 and uzpq2 instruction.
+#name: Test of SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
#as: -march=armv9.4-a
#objdump: -dr
@@ -32,3 +32,19 @@
.*: 44dfefff uzpq2 z31.d, z31.d, z31.d
.*: 448fed45 uzpq2 z5.s, z10.s, z15.s
.*: 4454edea uzpq2 z10.h, z15.h, z20.h
+.*: 4400e000 zipq1 z0.b, z0.b, z0.b
+.*: 4400e01f zipq1 z31.b, z0.b, z0.b
+.*: 44c0e000 zipq1 z0.d, z0.d, z0.d
+.*: 4400e3e0 zipq1 z0.b, z31.b, z0.b
+.*: 441fe000 zipq1 z0.b, z0.b, z31.b
+.*: 44dfe3ff zipq1 z31.d, z31.d, z31.d
+.*: 448fe145 zipq1 z5.s, z10.s, z15.s
+.*: 4454e1ea zipq1 z10.h, z15.h, z20.h
+.*: 4400e400 zipq2 z0.b, z0.b, z0.b
+.*: 4400e41f zipq2 z31.b, z0.b, z0.b
+.*: 44c0e400 zipq2 z0.d, z0.d, z0.d
+.*: 4400e7e0 zipq2 z0.b, z31.b, z0.b
+.*: 441fe400 zipq2 z0.b, z0.b, z31.b
+.*: 44dfe7ff zipq2 z31.d, z31.d, z31.d
+.*: 448fe545 zipq2 z5.s, z10.s, z15.s
+.*: 4454e5ea zipq2 z10.h, z15.h, z20.h
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
index b8c6ed72a89..11126c35221 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -24,3 +24,21 @@ uzpq2 z0.b, z0.b, z31.b
uzpq2 z31.d, z31.d, z31.d
uzpq2 z5.s, z10.s, z15.s
uzpq2 z10.h, z15.h, z20.h
+
+zipq1 z0.b, z0.b, z0.b
+zipq1 z31.b, z0.b, z0.b
+zipq1 z0.d, z0.d, z0.d
+zipq1 z0.b, z31.b, z0.b
+zipq1 z0.b, z0.b, z31.b
+zipq1 z31.d, z31.d, z31.d
+zipq1 z5.s, z10.s, z15.s
+zipq1 z10.h, z15.h, z20.h
+
+zipq2 z0.b, z0.b, z0.b
+zipq2 z31.b, z0.b, z0.b
+zipq2 z0.d, z0.d, z0.d
+zipq2 z0.b, z31.b, z0.b
+zipq2 z0.b, z0.b, z31.b
+zipq2 z31.d, z31.d, z31.d
+zipq2 z5.s, z10.s, z15.s
+zipq2 z10.h, z15.h, z20.h
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7089f167552..9832fc29485 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6645,6 +6645,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
SVE2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 08/12] aarch64: Add support for sve2p1 zipq[1-2] instructions (regenerated files).
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (6 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 07/12] aarch64: Add support for sve2p1 zipq[1-2] instructions Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 09/12] aarch64: Add support for sve2p1 tbxq instruction Srinath Parvathaneni
` (4 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 233 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sve2p1 zipq[1-2] instructions.
---
opcodes/aarch64-dis-2.c | 426 +++++++++++++++++++++-------------------
1 file changed, 224 insertions(+), 202 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0008-aarch64-Add-support-for-sve2p1-zipq-1-2-instructi.patch --]
[-- Type: text/x-patch; name="v1-0008-aarch64-Add-support-for-sve2p1-zipq-1-2-instructi.patch", Size: 107351 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index b31ab44e03f..d837fb8d62c 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3398;
+ return 3400;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3399;
+ return 3401;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3400;
+ return 3402;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3466;
+ return 3468;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3465;
+ return 3467;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3459;
+ return 3461;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3444;
+ return 3446;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3458;
+ return 3460;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3451;
+ return 3453;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3450;
+ return 3452;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3457;
+ return 3459;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3437;
+ return 3439;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3438;
+ return 3440;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3449;
+ return 3451;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3468;
+ return 3470;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3443;
+ return 3445;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3467;
+ return 3469;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3469;
+ return 3471;
}
else
{
@@ -3155,7 +3155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3463;
+ return 3465;
}
else
{
@@ -3163,7 +3163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3464;
+ return 3466;
}
}
}
@@ -3218,7 +3218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3461;
+ return 3463;
}
else
{
@@ -3226,7 +3226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3462;
+ return 3464;
}
}
}
@@ -3280,7 +3280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3447;
+ return 3449;
}
else
{
@@ -3288,7 +3288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3448;
+ return 3450;
}
}
}
@@ -3350,7 +3350,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3455;
+ return 3457;
}
else
{
@@ -3358,7 +3358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3456;
+ return 3458;
}
}
}
@@ -3413,7 +3413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3453;
+ return 3455;
}
else
{
@@ -3421,7 +3421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3454;
+ return 3456;
}
}
}
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3460;
+ return 3462;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3452;
+ return 3454;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3401;
+ return 3403;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3402;
+ return 3404;
}
}
}
@@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3441;
+ return 3443;
}
else
{
@@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3442;
+ return 3444;
}
}
}
@@ -4038,7 +4038,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3445;
+ return 3447;
}
else
{
@@ -4046,7 +4046,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3446;
+ return 3448;
}
}
}
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3403;
+ return 3405;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3404;
+ return 3406;
}
}
}
@@ -4398,7 +4398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3439;
+ return 3441;
}
else
{
@@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3440;
+ return 3442;
}
}
}
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3375;
+ return 3377;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3372;
+ return 3374;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3367;
+ return 3369;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3373;
+ return 3375;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3374;
+ return 3376;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3368;
+ return 3370;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3369;
+ return 3371;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3363;
+ return 3365;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3364;
+ return 3366;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3370;
+ return 3372;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3371;
+ return 3373;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3365;
+ return 3367;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3366;
+ return 3368;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3377;
+ return 3379;
}
}
else
@@ -5774,16 +5774,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3376;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1110xx100xxxx0
- fscale. */
return 3378;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx1x1110xx100xxxx0
+ fscale. */
+ return 3380;
+ }
}
}
else
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3379;
+ return 3381;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3380;
+ return 3382;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3381;
+ return 3383;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3382;
+ return 3384;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3383;
+ return 3385;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3385;
+ return 3387;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3384;
+ return 3386;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3386;
+ return 3388;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3388;
+ return 3390;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3387;
+ return 3389;
}
}
}
@@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3324;
+ return 3326;
}
else
{
@@ -16172,30 +16172,52 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 010001x0xx0xxxxx1110x0xxxxxxxxxx
- uzpq1. */
- return 3322;
+ 010001x0xx0xxxxx111x00xxxxxxxxxx
+ zipq1. */
+ return 3324;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx1111x0xxxxxxxxxx
- tblq. */
- return 3320;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx111010xxxxxxxxxx
+ uzpq1. */
+ return 3322;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx111110xxxxxxxxxx
+ tblq. */
+ return 3320;
+ }
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx111xx1xxxxxxxxxx
- uzpq2. */
- return 3323;
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx111x01xxxxxxxxxx
+ zipq2. */
+ return 3325;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx111x11xxxxxxxxxx
+ uzpq2. */
+ return 3323;
+ }
}
}
else
@@ -16674,7 +16696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3333;
+ return 3335;
}
else
{
@@ -16684,16 +16706,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3332;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x0110xxxxx000xxxxxxxxxxxxx
- st4q. */
return 3334;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x0110xxxxx000xxxxxxxxxxxxx
+ st4q. */
+ return 3336;
+ }
}
}
else
@@ -17358,7 +17380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3325;
+ return 3327;
}
}
}
@@ -17494,7 +17516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3328;
+ return 3330;
}
}
else
@@ -17639,7 +17661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3335;
+ return 3337;
}
}
else
@@ -17682,7 +17704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3336;
+ return 3338;
}
}
else
@@ -17723,7 +17745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3337;
+ return 3339;
}
}
}
@@ -17752,7 +17774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3424;
+ return 3426;
}
}
else
@@ -17761,7 +17783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3426;
+ return 3428;
}
}
else
@@ -17802,7 +17824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3436;
+ return 3438;
}
}
else
@@ -17835,7 +17857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3422;
+ return 3424;
}
}
else
@@ -17906,7 +17928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3427;
+ return 3429;
}
}
else
@@ -17915,7 +17937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3423;
+ return 3425;
}
}
else
@@ -17924,7 +17946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3428;
+ return 3430;
}
}
else
@@ -17933,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3429;
+ return 3431;
}
}
else
@@ -17960,7 +17982,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3425;
+ return 3427;
}
}
else
@@ -17978,7 +18000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3432;
+ return 3434;
}
}
else
@@ -17987,7 +18009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3435;
+ return 3437;
}
}
else
@@ -18020,7 +18042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3421;
+ return 3423;
}
}
else
@@ -18029,7 +18051,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3430;
+ return 3432;
}
}
else
@@ -18061,7 +18083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3434;
+ return 3436;
}
}
else
@@ -18360,7 +18382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3331;
+ return 3333;
}
}
else
@@ -18375,16 +18397,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3431;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0001xxxxx1011xxxxxxxxxxxx
- fmlalltt. */
return 3433;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1011xxxxxxxxxxxx
+ fmlalltt. */
+ return 3435;
+ }
}
else
{
@@ -20739,7 +20761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3393;
+ return 3395;
}
}
else
@@ -20748,7 +20770,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3394;
+ return 3396;
}
}
else
@@ -20761,7 +20783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3395;
+ return 3397;
}
else
{
@@ -20769,7 +20791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3396;
+ return 3398;
}
}
else
@@ -20778,7 +20800,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3397;
+ return 3399;
}
}
}
@@ -21729,7 +21751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3355;
+ return 3357;
}
else
{
@@ -21737,7 +21759,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3351;
+ return 3353;
}
}
else
@@ -21748,7 +21770,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3356;
+ return 3358;
}
else
{
@@ -21756,7 +21778,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3352;
+ return 3354;
}
}
}
@@ -21801,7 +21823,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3360;
+ return 3362;
}
else
{
@@ -21809,7 +21831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3359;
+ return 3361;
}
}
else
@@ -21820,7 +21842,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3361;
+ return 3363;
}
else
{
@@ -21828,7 +21850,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3362;
+ return 3364;
}
}
}
@@ -21889,7 +21911,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3357;
+ return 3359;
}
else
{
@@ -21897,7 +21919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3353;
+ return 3355;
}
}
else
@@ -21908,7 +21930,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3358;
+ return 3360;
}
else
{
@@ -21916,7 +21938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3354;
+ return 3356;
}
}
}
@@ -23242,7 +23264,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3326;
+ return 3328;
}
else
{
@@ -23250,7 +23272,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3327;
+ return 3329;
}
}
}
@@ -24423,7 +24445,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3329;
+ return 3331;
}
else
{
@@ -24431,7 +24453,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3330;
+ return 3332;
}
}
else
@@ -26496,29 +26518,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3389;
- }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx000xxxxxxxxxx
- luti4. */
return 3391;
}
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx000xxxxxxxxxx
+ luti4. */
+ return 3393;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3392;
+ return 3394;
}
}
else
@@ -26527,7 +26549,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3390;
+ return 3392;
}
}
}
@@ -26643,7 +26665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3413;
+ return 3415;
}
else
{
@@ -26651,7 +26673,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3415;
+ return 3417;
}
}
else
@@ -26662,7 +26684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3414;
+ return 3416;
}
else
{
@@ -26670,7 +26692,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3416;
+ return 3418;
}
}
}
@@ -26758,7 +26780,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3346;
+ return 3348;
}
else
{
@@ -26766,7 +26788,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3347;
+ return 3349;
}
}
else
@@ -26775,7 +26797,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3348;
+ return 3350;
}
}
}
@@ -26918,7 +26940,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3405;
+ return 3407;
}
else
{
@@ -26928,7 +26950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3407;
+ return 3409;
}
else
{
@@ -26938,7 +26960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3409;
+ return 3411;
}
else
{
@@ -26946,7 +26968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3410;
+ return 3412;
}
}
}
@@ -27220,7 +27242,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3349;
+ return 3351;
}
}
}
@@ -28612,7 +28634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3342;
+ return 3344;
}
else
{
@@ -28620,7 +28642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3343;
+ return 3345;
}
}
else
@@ -28631,7 +28653,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3338;
+ return 3340;
}
else
{
@@ -28639,7 +28661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3339;
+ return 3341;
}
}
}
@@ -28653,7 +28675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3344;
+ return 3346;
}
else
{
@@ -28661,7 +28683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3345;
+ return 3347;
}
}
else
@@ -28672,7 +28694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3340;
+ return 3342;
}
else
{
@@ -28680,7 +28702,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3341;
+ return 3343;
}
}
}
@@ -30679,7 +30701,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3350;
+ return 3352;
}
}
}
@@ -32395,7 +32417,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3406;
+ return 3408;
}
else
{
@@ -32425,7 +32447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3408;
+ return 3410;
}
else
{
@@ -32435,7 +32457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3411;
+ return 3413;
}
else
{
@@ -32443,7 +32465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3412;
+ return 3414;
}
}
}
@@ -32985,16 +33007,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3417;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x110111100xxxxxx1000x0xxxxxxxxxx
- fmlalltb. */
return 3419;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110111100xxxxxx1000x0xxxxxxxxxx
+ fmlalltb. */
+ return 3421;
+ }
}
else
{
@@ -33024,16 +33046,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3418;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1101111x1xxxxxx1000x0xxxxxxxxxx
- fmlalltt. */
return 3420;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101111x1xxxxxx1000x0xxxxxxxxxx
+ fmlalltt. */
+ return 3422;
+ }
}
}
}
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 09/12] aarch64: Add support for sve2p1 tbxq instruction.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (7 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 08/12] aarch64: Add support for sve2p1 zipq[1-2] instructions (regenerated files) Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 10/12] aarch64: Add support for sve2p1 tbxq instruction (regenerated files) Srinath Parvathaneni
` (3 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 578 bytes --]
This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 2 +-
gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 12 ++++++++++++
gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 6 ++++++
gas/testsuite/gas/aarch64/sve2p1-6.d | 10 +++++++++-
gas/testsuite/gas/aarch64/sve2p1-6.s | 9 +++++++++
opcodes/aarch64-tbl.h | 1 +
6 files changed, 38 insertions(+), 2 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0009-aarch64-Add-support-for-sve2p1-tbxq-instruction.patch --]
[-- Type: text/x-patch; name="v1-0009-aarch64-Add-support-for-sve2p1-tbxq-instruction.patch", Size: 5072 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
index db35ae7acb3..437f810868d 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
@@ -1,3 +1,3 @@
-#name: Test of illegal SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
+#name: Test of illegal SVE2.1 tblq, tbxq, uzpq[1-2] and zipq[1-2] instruction.
#as: -march=armv9.4-a
#error_output: sve2p1-6-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
index 55987acc8b0..f37a3a0df9f 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
@@ -16,6 +16,18 @@
.*: Info: tblq z0.h, {z31.h}, z0.h
.*: Info: tblq z0.d, {z31.d}, z0.d
.*: Error: expected an SVE vector register at operand 3 -- `tblq z0.b,{z0.b},{z31.b}'
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.s,{z0.b},z0.b'
+.*: Error: operand mismatch -- `tbxq z31.s,z0.b,z0.h'
+.*: Info: did you mean this\?
+.*: Info: tbxq z31.b, z0.b, z0.b
+.*: Info: other valid variant\(s\):
+.*: Info: tbxq z31.h, z0.h, z0.h
+.*: Info: tbxq z31.s, z0.s, z0.s
+.*: Info: tbxq z31.d, z0.d, z0.d
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.s,{z0.s,z1.s},z0.s'
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.h,{z0.h-z1.h},z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `tbxq {z0.s},z31.s,z0.b'
+.*: Error: expected an SVE vector register at operand 2 -- `tbxq z0.b,{z0.b},{z31.b}'
.*: Error: expected an SVE vector register at operand 2 -- `uzpq1 z0.s,{z0.b},z0.b'
.*: Error: operand mismatch -- `uzpq1 z31.s,z0.b,z0.h'
.*: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
index f79dfac78d4..7d3209e5293 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
@@ -4,6 +4,12 @@ tblq z0.s, {z0.s, z1.s}, z0.s
tblq z0.s, {z0.s - z1.s}, z0.s
tblq z0.s, {z31.s}, z0.b
tblq z0.b, {z0.b}, {z31.b}
+tbxq z0.s, {z0.b}, z0.b
+tbxq z31.s, z0.b, z0.h
+tbxq z0.s, {z0.s, z1.s}, z0.s
+tbxq z0.h, {z0.h - z1.h}, z0.h
+tbxq {z0.s}, z31.s, z0.b
+tbxq z0.b, {z0.b}, {z31.b}
uzpq1 z0.s, {z0.b}, z0.b
uzpq1 z31.s, z0.b, z0.h
uzpq1 z0.s, {z0.s, z1.s}, z0.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.d b/gas/testsuite/gas/aarch64/sve2p1-6.d
index 83ba1426135..42d1ee41e99 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.d
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.d
@@ -1,4 +1,4 @@
-#name: Test of SVE2.1 tblq, uzpq[1-2] and zipq[1-2] instruction.
+#name: Test of SVE2.1 tblq, tbxq, uzpq[1-2] and zipq[1-2] instruction.
#as: -march=armv9.4-a
#objdump: -dr
@@ -16,6 +16,14 @@
.*: 44dffbff tblq z31.d, {z31.d}, z31.d
.*: 444ff945 tblq z5.h, {z10.h}, z15.h
.*: 4487f861 tblq z1.s, {z3.s}, z7.s
+.*: 05203400 tbxq z0.b, z0.b, z0.b
+.*: 0520341f tbxq z31.b, z0.b, z0.b
+.*: 05e03400 tbxq z0.d, z0.d, z0.d
+.*: 052037e0 tbxq z0.b, z31.b, z0.b
+.*: 053f3400 tbxq z0.b, z0.b, z31.b
+.*: 05ff37ff tbxq z31.d, z31.d, z31.d
+.*: 05af3545 tbxq z5.s, z10.s, z15.s
+.*: 057435ea tbxq z10.h, z15.h, z20.h
.*: 4400e800 uzpq1 z0.b, z0.b, z0.b
.*: 4400e81f uzpq1 z31.b, z0.b, z0.b
.*: 44c0e800 uzpq1 z0.d, z0.d, z0.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-6.s b/gas/testsuite/gas/aarch64/sve2p1-6.s
index 11126c35221..f61cd82e1b3 100644
--- a/gas/testsuite/gas/aarch64/sve2p1-6.s
+++ b/gas/testsuite/gas/aarch64/sve2p1-6.s
@@ -7,6 +7,15 @@ tblq z31.d, {z31.d}, z31.d
tblq z5.h, {z10.h}, z15.h
tblq z1.s, {z3.s}, z7.s
+tbxq z0.b, z0.b, z0.b
+tbxq z31.b, z0.b, z0.b
+tbxq z0.d, z0.d, z0.d
+tbxq z0.b, z31.b, z0.b
+tbxq z0.b, z0.b, z31.b
+tbxq z31.d, z31.d, z31.d
+tbxq z5.s, z10.s, z15.s
+tbxq z10.h, z15.h, z20.h
+
uzpq1 z0.b, z0.b, z0.b
uzpq1 z31.b, z0.b, z0.b
uzpq1 z0.d, z0.d, z0.d
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 9832fc29485..0bd2cc0c34b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6642,6 +6642,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSN("orqv",0x041c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
SVE2p1_INSN("tblq",0x4400f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
+ SVE2p1_INSN("tbxq",0x05203400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
SVE2p1_INSN("uzpq1",0x4400e800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSN("uzpq2",0x4400ec00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 10/12] aarch64: Add support for sve2p1 tbxq instruction (regenerated files).
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (8 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 09/12] aarch64: Add support for sve2p1 tbxq instruction Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-04 12:40 ` [PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction Srinath Parvathaneni
` (2 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 227 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sve2p1 tbxq instruction.
---
opcodes/aarch64-dis-2.c | 459 ++++++++++++++++++++--------------------
1 file changed, 235 insertions(+), 224 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0010-aarch64-Add-support-for-sve2p1-tbxq-instruction-r.patch --]
[-- Type: text/x-patch; name="v1-0010-aarch64-Add-support-for-sve2p1-tbxq-instruction-r.patch", Size: 110851 bytes --]
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index d837fb8d62c..6458bbca0e8 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3400;
+ return 3401;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3401;
+ return 3402;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3402;
+ return 3403;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3468;
+ return 3469;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3467;
+ return 3468;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3461;
+ return 3462;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3446;
+ return 3447;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3460;
+ return 3461;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3453;
+ return 3454;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3452;
+ return 3453;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3459;
+ return 3460;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3439;
+ return 3440;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3440;
+ return 3441;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3451;
+ return 3452;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3470;
+ return 3471;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3445;
+ return 3446;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3469;
+ return 3470;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3471;
+ return 3472;
}
else
{
@@ -3155,16 +3155,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3465;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx000xxxx10000x
- fmlall. */
return 3466;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxx10000x
+ fmlall. */
+ return 3467;
+ }
}
}
}
@@ -3218,16 +3218,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3463;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx000xxxxx00x1x
- fmlall. */
return 3464;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx000xxxxx00x1x
+ fmlall. */
+ return 3465;
+ }
}
}
else
@@ -3280,16 +3280,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3449;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxx100xxx
- fdot. */
return 3450;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx100xxx
+ fdot. */
+ return 3451;
+ }
}
}
}
@@ -3350,16 +3350,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3457;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001101xxxx10xx010xxxx1000xx
- fmlal. */
return 3458;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx010xxxx1000xx
+ fmlal. */
+ return 3459;
+ }
}
}
}
@@ -3413,16 +3413,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3455;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx010xxxxx001xx
- fmlal. */
return 3456;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx010xxxxx001xx
+ fmlal. */
+ return 3457;
+ }
}
}
else
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3462;
+ return 3463;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3454;
+ return 3455;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3403;
+ return 3404;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3404;
+ return 3405;
}
}
}
@@ -3739,16 +3739,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3443;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxx110xxx
- fdot. */
return 3444;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx110xxx
+ fdot. */
+ return 3445;
+ }
}
}
}
@@ -4038,16 +4038,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3447;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx01xxx
- fdot. */
return 3448;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3449;
+ }
}
}
else
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3405;
+ return 3406;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3406;
+ return 3407;
}
}
}
@@ -4398,16 +4398,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3441;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx11xxx
- fdot. */
return 3442;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3443;
+ }
}
}
else
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3377;
+ return 3378;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3374;
+ return 3375;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3369;
+ return 3370;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3375;
+ return 3376;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3376;
+ return 3377;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3370;
+ return 3371;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3371;
+ return 3372;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3365;
+ return 3366;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3366;
+ return 3367;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3372;
+ return 3373;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3373;
+ return 3374;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3367;
+ return 3368;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3368;
+ return 3369;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3379;
+ return 3380;
}
}
else
@@ -5774,7 +5774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3378;
+ return 3379;
}
else
{
@@ -5782,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3380;
+ return 3381;
}
}
}
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3381;
+ return 3382;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3382;
+ return 3383;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3383;
+ return 3384;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3384;
+ return 3385;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3385;
+ return 3386;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3387;
+ return 3388;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3386;
+ return 3387;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3388;
+ return 3389;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3390;
+ return 3391;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3389;
+ return 3390;
}
}
}
@@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3326;
+ return 3327;
}
else
{
@@ -16178,7 +16178,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3324;
+ return 3325;
}
else
{
@@ -16188,7 +16188,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3322;
+ return 3323;
}
else
{
@@ -16208,7 +16208,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3325;
+ return 3326;
}
else
{
@@ -16216,7 +16216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3323;
+ return 3324;
}
}
}
@@ -16696,7 +16696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3335;
+ return 3336;
}
else
{
@@ -16706,7 +16706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3334;
+ return 3335;
}
else
{
@@ -16714,7 +16714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3336;
+ return 3337;
}
}
}
@@ -17380,7 +17380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3327;
+ return 3328;
}
}
}
@@ -17516,7 +17516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3330;
+ return 3331;
}
}
else
@@ -17661,7 +17661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3337;
+ return 3338;
}
}
else
@@ -17704,7 +17704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3338;
+ return 3339;
}
}
else
@@ -17745,7 +17745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3339;
+ return 3340;
}
}
}
@@ -17774,7 +17774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3426;
+ return 3427;
}
}
else
@@ -17783,7 +17783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3428;
+ return 3429;
}
}
else
@@ -17824,7 +17824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3438;
+ return 3439;
}
}
else
@@ -17857,7 +17857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3424;
+ return 3425;
}
}
else
@@ -17928,7 +17928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3429;
+ return 3430;
}
}
else
@@ -17937,7 +17937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3425;
+ return 3426;
}
}
else
@@ -17946,7 +17946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3430;
+ return 3431;
}
}
else
@@ -17955,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3431;
+ return 3432;
}
}
else
@@ -17982,7 +17982,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3427;
+ return 3428;
}
}
else
@@ -18000,7 +18000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3434;
+ return 3435;
}
}
else
@@ -18009,7 +18009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3437;
+ return 3438;
}
}
else
@@ -18042,7 +18042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3423;
+ return 3424;
}
}
else
@@ -18051,7 +18051,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3432;
+ return 3433;
}
}
else
@@ -18083,7 +18083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3436;
+ return 3437;
}
}
else
@@ -18382,7 +18382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3333;
+ return 3334;
}
}
else
@@ -18397,7 +18397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3433;
+ return 3434;
}
else
{
@@ -18405,7 +18405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3435;
+ return 3436;
}
}
else
@@ -19144,20 +19144,31 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1x01xxxxx001x01xxxxxxxxxx
- dupq. */
- return 3318;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1x01xxxxx001001xxxxxxxxxx
+ dupq. */
+ return 3318;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1x11xxxxx001001xxxxxxxxxx
+ extq. */
+ return 3322;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 000001x1x11xxxxx001x01xxxxxxxxxx
- extq. */
+ 000001x1xx1xxxxx001101xxxxxxxxxx
+ tbxq. */
return 3321;
}
}
@@ -20761,7 +20772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3395;
+ return 3396;
}
}
else
@@ -20770,7 +20781,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3396;
+ return 3397;
}
}
else
@@ -20783,16 +20794,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3397;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x1xx1xxxxx101101xxxxxxxxxx
- luti4. */
return 3398;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101101xxxxxxxxxx
+ luti4. */
+ return 3399;
+ }
}
else
{
@@ -20800,7 +20811,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3399;
+ return 3400;
}
}
}
@@ -21751,7 +21762,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3357;
+ return 3358;
}
else
{
@@ -21759,7 +21770,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3353;
+ return 3354;
}
}
else
@@ -21770,7 +21781,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3358;
+ return 3359;
}
else
{
@@ -21778,7 +21789,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3354;
+ return 3355;
}
}
}
@@ -21823,7 +21834,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3362;
+ return 3363;
}
else
{
@@ -21831,7 +21842,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3361;
+ return 3362;
}
}
else
@@ -21842,7 +21853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3363;
+ return 3364;
}
else
{
@@ -21850,7 +21861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3364;
+ return 3365;
}
}
}
@@ -21911,7 +21922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3359;
+ return 3360;
}
else
{
@@ -21919,7 +21930,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3355;
+ return 3356;
}
}
else
@@ -21930,7 +21941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3360;
+ return 3361;
}
else
{
@@ -21938,7 +21949,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3356;
+ return 3357;
}
}
}
@@ -23264,7 +23275,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3328;
+ return 3329;
}
else
{
@@ -23272,7 +23283,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3329;
+ return 3330;
}
}
}
@@ -24445,7 +24456,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3331;
+ return 3332;
}
else
{
@@ -24453,7 +24464,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3332;
+ return 3333;
}
}
else
@@ -26518,7 +26529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3391;
+ return 3392;
}
}
}
@@ -26532,16 +26543,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3393;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxxx100xxxxxxxxxx
- luti4. */
return 3394;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxxxx100xxxxxxxxxx
+ luti4. */
+ return 3395;
+ }
}
else
{
@@ -26549,7 +26560,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3392;
+ return 3393;
}
}
}
@@ -26665,7 +26676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3415;
+ return 3416;
}
else
{
@@ -26673,7 +26684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3417;
+ return 3418;
}
}
else
@@ -26684,7 +26695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3416;
+ return 3417;
}
else
{
@@ -26692,7 +26703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3418;
+ return 3419;
}
}
}
@@ -26780,7 +26791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3348;
+ return 3349;
}
else
{
@@ -26788,7 +26799,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3349;
+ return 3350;
}
}
else
@@ -26797,7 +26808,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3350;
+ return 3351;
}
}
}
@@ -26940,7 +26951,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3407;
+ return 3408;
}
else
{
@@ -26950,7 +26961,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3409;
+ return 3410;
}
else
{
@@ -26960,7 +26971,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3411;
+ return 3412;
}
else
{
@@ -26968,7 +26979,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3412;
+ return 3413;
}
}
}
@@ -27242,7 +27253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3351;
+ return 3352;
}
}
}
@@ -28634,7 +28645,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3344;
+ return 3345;
}
else
{
@@ -28642,7 +28653,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3345;
+ return 3346;
}
}
else
@@ -28653,7 +28664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3340;
+ return 3341;
}
else
{
@@ -28661,7 +28672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3341;
+ return 3342;
}
}
}
@@ -28675,7 +28686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3346;
+ return 3347;
}
else
{
@@ -28683,7 +28694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3347;
+ return 3348;
}
}
else
@@ -28694,7 +28705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3342;
+ return 3343;
}
else
{
@@ -28702,7 +28713,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3343;
+ return 3344;
}
}
}
@@ -30701,7 +30712,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3352;
+ return 3353;
}
}
}
@@ -32417,7 +32428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3408;
+ return 3409;
}
else
{
@@ -32447,7 +32458,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3410;
+ return 3411;
}
else
{
@@ -32457,16 +32468,16 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3413;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x100111111xxxxxx0000x0xxxxxxxxxx
- fmlalt. */
return 3414;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111111xxxxxx0000x0xxxxxxxxxx
+ fmlalt. */
+ return 3415;
+ }
}
}
}
@@ -33007,7 +33018,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3419;
+ return 3420;
}
else
{
@@ -33015,7 +33026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3421;
+ return 3422;
}
}
else
@@ -33046,7 +33057,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3420;
+ return 3421;
}
else
{
@@ -33054,7 +33065,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3422;
+ return 3423;
}
}
}
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (9 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 10/12] aarch64: Add support for sve2p1 tbxq instruction (regenerated files) Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-08 16:15 ` Richard Earnshaw (lists)
2024-07-04 12:40 ` [PATCH v1 12/12] aarch64: Add support for sve2p1 pmov instruction (regenerated files) Srinath Parvathaneni
2024-07-08 16:16 ` [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Richard Earnshaw (lists)
12 siblings, 1 reply; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, srinath
[-- Attachment #1: Type: text/plain, Size: 2479 bytes --]
This patch adds support for followign SVE2p1 instruction, spec is available here [1].
1. PMOV (to vector)
2. PMOV (to predicate)
Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.
AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".
As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
PMOV <Pn>.D, <Zd>{[<imm>]}
Example1:
Assembly: pmov z5[0], p6.d
Disassembly: pmov z5, p6.d
Assembly: pmov z5, p6.d
Disassembly: pmov z5, p6.d
Example2:
Assembly: pmov p4.b, z5[0]
Disassembly: pmov p4.b, z5
Assembly: pmov p4.b, z5
Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
---
gas/config/tc-aarch64.c | 28 ++++-
gas/testsuite/gas/aarch64/sve2p1-7-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-7-invalid.l | 118 +++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-7-invalid.s | 76 ++++++++++++
gas/testsuite/gas/aarch64/sve2p1-7.d | 64 ++++++++++
gas/testsuite/gas/aarch64/sve2p1-7.s | 63 ++++++++++
include/opcode/aarch64.h | 8 ++
opcodes/aarch64-opc.c | 34 +++++-
opcodes/aarch64-opc.h | 2 +
opcodes/aarch64-tbl.h | 54 ++++++++-
10 files changed, 440 insertions(+), 10 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0011-aarch64-Add-support-for-sve2p1-pmov-instruction.patch --]
[-- Type: text/x-patch; name="v1-0011-aarch64-Add-support-for-sve2p1-pmov-instruction.patch", Size: 23344 bytes --]
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 42c03bd199e..50f00515521 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -113,6 +113,7 @@ enum vector_el_type
#define NTA_HASTYPE 1
#define NTA_HASINDEX 2
#define NTA_HASVARWIDTH 4
+#define NTA_NOINDEX 8
struct vector_type_el
{
@@ -1185,11 +1186,15 @@ parse_index_expression (char **str, int64_t *imm)
register index.
FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
- an operand that we can be confident that it is a good match. */
+ an operand that we can be confident that it is a good match.
+
+ FLAGS includes PTR_OPTIONAL_INDEX, which has been introduced to parse
+ instructions with optional index operands. */
#define PTR_IN_REGLIST (1U << 0)
#define PTR_FULL_REG (1U << 1)
#define PTR_GOOD_MATCH (1U << 2)
+#define PTR_OPTIONAL_INDEX (1U << 3)
static const reg_entry *
parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1277,7 +1282,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
atype.width = parsetype.width;
}
- if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
+ if ((flags & PTR_OPTIONAL_INDEX) && (*str == '\0' || *str == ','))
+ atype.defined |= NTA_NOINDEX;
+ else if ((!(flags & PTR_FULL_REG) || (flags & PTR_OPTIONAL_INDEX))
+ && skip_past_char (&str, '['))
{
/* Reject Sn[index] syntax. */
if (reg->type != REG_TYPE_Z
@@ -6886,6 +6894,20 @@ parse_operands (char *str, const aarch64_opcode *opcode)
reg_type = REG_TYPE_Z;
goto vector_reg_index;
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
+ reg_type = REG_TYPE_Z;
+ reg = parse_typed_reg (&str, reg_type, &vectype, PTR_OPTIONAL_INDEX);
+ if (!reg || !(vectype.defined & (NTA_HASINDEX | NTA_NOINDEX)))
+ goto failure;
+ goto vector_reg_optional_index;
+
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
@@ -6899,7 +6921,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
if (!(vectype.defined & NTA_HASINDEX))
goto failure;
-
+ vector_reg_optional_index:
if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype)
/* Unqualified Zn[index] is allowed in LUTI2 instructions. */
info->qualifier = AARCH64_OPND_QLF_NIL;
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
new file mode 100644
index 00000000000..ddf2ccb0deb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal pmov instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-7-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
new file mode 100644
index 00000000000..4559f6f8d36
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
@@ -0,0 +1,118 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `pmov p0,z0'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.b,z0'
+.*: Error: register element index must be 0 at operand 2 -- `pmov p0.b,z31\[1\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.b'
+.*: Error: operand mismatch -- `pmov p15,z31.b\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[4\]
+.*: Error: operand mismatch -- `pmov p7,z15.b'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.h, z15
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p7,w15.b'
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p7.b,x15'
+.*: Error: operand mismatch -- `pmov p0,z0\[3\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[3\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.h,z0'
+.*: Error: register element index out of range 0 to 1 at operand 2 -- `pmov p0.h,z31\[2\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.h'
+.*: Error: operand mismatch -- `pmov p15,z31.h\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[4\]
+.*: Error: operand mismatch -- `pmov p7.h,z15.h'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.h, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.h,x15.h'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.h,w15'
+.*: Error: operand mismatch -- `pmov p0,z0\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[4\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.s,z0'
+.*: Error: register element index out of range 0 to 3 at operand 2 -- `pmov p0.s,z31\[5\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.s'
+.*: Error: operand mismatch -- `pmov p15,z31.s\[6\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[6\]
+.*: Error: operand mismatch -- `pmov p7.s,z15.s'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.s, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.s,w15.s'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.s,x15'
+.*: Error: operand mismatch -- `pmov p0,z0\[8\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[8\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.d,z0'
+.*: Error: register element index out of range 0 to 7 at operand 2 -- `pmov p0.d,z31\[10\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.d'
+.*: Error: operand mismatch -- `pmov p15,z31.d\[12\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[12\]
+.*: Error: operand mismatch -- `pmov p7.d,z15.d'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.d, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.d,x15.d'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.d,w15'
+.*: Error: operand mismatch -- `pmov z0,p0'
+.*: Info: did you mean this\?
+.*: Info: pmov z0, p0.b
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.b'
+.*: Error: register element index must be 0 at operand 1 -- `pmov z31\[1\],p0.b'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.b'
+.*: Error: operand mismatch -- `pmov z31.b\[4\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[4\], p15.b
+.*: Error: operand mismatch -- `pmov z15.b,p7.b'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x15.b,p7.b'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w15.b,p7'
+.*: Error: operand mismatch -- `pmov z0\[3\],p0'
+.*: Info: did you mean this\?
+.*: Info: pmov z0\[3\], p0.b
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.h'
+.*: Error: register element index out of range 0 to 1 at operand 1 -- `pmov z31\[2\],p0.h'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.h'
+.*: Error: operand mismatch -- `pmov z31.h\[5\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[5\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.h,p7.h'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.h
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.h,p7.h'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.h,p7'
+.*: Error: register element index out of range 0 to 3 at operand 1 -- `pmov z0\[5\],p0.s'
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.s'
+.*: Error: register element index out of range 0 to 3 at operand 1 -- `pmov z31\[6\],p0.s'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.s'
+.*: Error: operand mismatch -- `pmov z31.s\[7\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[7\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.s,p7.s'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.s
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.s,p7.s'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.s,p7'
+.*: Error: register element index out of range 0 to 7 at operand 1 -- `pmov z0\[8\],p0.d'
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.d'
+.*: Error: register element index out of range 0 to 7 at operand 1 -- `pmov z31\[9\],p0.d'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.d'
+.*: Error: operand mismatch -- `pmov z31.d\[10\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[10\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.d,p7.d'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.d
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.d,p7.d'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.d,p7'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
new file mode 100644
index 00000000000..b83ef36ba8c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
@@ -0,0 +1,76 @@
+/* PMOV (to predicate). */
+pmov p0, z0
+pmov p16.b, z0
+pmov p0.b, z31[1]
+pmov p15.b
+pmov p15, z31.b[4]
+pmov p7, z15.b
+mov p7, w15.b
+mov p7.b, x15
+
+pmov p0, z0[3]
+pmov p16.h, z0
+pmov p0.h, z31[2]
+pmov p15.h
+pmov p15, z31.h[4]
+pmov p7.h, z15.h
+pmov p7.h, x15.h
+pmov p7.h, w15
+
+pmov p0, z0[4]
+pmov p16.s, z0
+pmov p0.s, z31[5]
+pmov p15.s
+pmov p15, z31.s[6]
+pmov p7.s, z15.s
+pmov p7.s, w15.s
+pmov p7.s, x15
+
+pmov p0, z0[8]
+pmov p16.d, z0
+pmov p0.d, z31[10]
+pmov p15.d
+pmov p15, z31.d[12]
+pmov p7.d, z15.d
+pmov p7.d, x15.d
+pmov p7.d, w15
+
+/* PMOV (to vector). */
+pmov z0, p0
+pmov z0, p16.b
+pmov z31[1], p0.b
+pmov p15.b
+pmov z31.b[4], p15
+pmov z15.b, p7.b
+pmov x15.b, p7.b
+pmov w15.b, p7
+
+pmov z0[3], p0
+pmov z0, p16.h
+pmov z31[2], p0.h
+pmov p15.h
+pmov z31.h[5], p15
+pmov z15, p7
+pmov z8.h, p7.h
+pmov x8.h, p7.h
+pmov w8.h, p7
+
+pmov z0[5], p0.s
+pmov z0, p16.s
+pmov z31[6], p0.s
+pmov p15.s
+pmov z31.s[7], p15
+pmov z15, p7
+pmov z8.s, p7.s
+pmov x8.s, p7.s
+pmov w8.s, p7
+
+pmov z0[8], p0.d
+pmov z0, p16.d
+pmov z31[9], p0.d
+pmov p15.d
+pmov z31.d[10], p15
+pmov z15, p7
+pmov z8.d, p7.d
+pmov w8.d, p7.d
+pmov x8.d, p7
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7.d b/gas/testsuite/gas/aarch64/sve2p1-7.d
new file mode 100644
index 00000000000..6bd1a22aaf4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7.d
@@ -0,0 +1,64 @@
+#name: Test of SVE2.1 pmov instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 052a3800 pmov p0.b, z0
+.*: 052a380f pmov p15.b, z0
+.*: 052a3be0 pmov p0.b, z31
+.*: 052a3bef pmov p15.b, z31
+.*: 052a3bef pmov p15.b, z31
+.*: 052a39e7 pmov p7.b, z15
+.*: 052c3800 pmov p0.h, z0
+.*: 052c380f pmov p15.h, z0
+.*: 052c3be0 pmov p0.h, z31
+.*: 052e3800 pmov p0.h, z0\[1\]
+.*: 052e3bef pmov p15.h, z31\[1\]
+.*: 052c39e7 pmov p7.h, z15
+.*: 052c3903 pmov p3.h, z8
+.*: 05683800 pmov p0.s, z0
+.*: 0568380f pmov p15.s, z0
+.*: 05683be0 pmov p0.s, z31
+.*: 056e3800 pmov p0.s, z0\[3\]
+.*: 056e3bef pmov p15.s, z31\[3\]
+.*: 056a39e7 pmov p7.s, z15\[1\]
+.*: 05683903 pmov p3.s, z8
+.*: 05a83800 pmov p0.d, z0
+.*: 05a8380f pmov p15.d, z0
+.*: 05a83be0 pmov p0.d, z31
+.*: 05ee3800 pmov p0.d, z0\[7\]
+.*: 05ee3bef pmov p15.d, z31\[7\]
+.*: 05ae39e7 pmov p7.d, z15\[3\]
+.*: 05a83903 pmov p3.d, z8
+.*: 052b3800 pmov z0, p0.b
+.*: 052b381f pmov z31, p0.b
+.*: 052b39e0 pmov z0, p15.b
+.*: 052b39ff pmov z31, p15.b
+.*: 052b38e0 pmov z0, p7.b
+.*: 052b38ef pmov z15, p7.b
+.*: 052d3800 pmov z0, p0.h
+.*: 052d381f pmov z31, p0.h
+.*: 052f3800 pmov z0\[1\], p0.h
+.*: 052d39e0 pmov z0, p15.h
+.*: 052f39ff pmov z31\[1\], p15.h
+.*: 052d39ef pmov z15, p15.h
+.*: 052d38e8 pmov z8, p7.h
+.*: 05693800 pmov z0, p0.s
+.*: 0569381f pmov z31, p0.s
+.*: 056f3800 pmov z0\[3\], p0.s
+.*: 056939e0 pmov z0, p15.s
+.*: 056f39ff pmov z31\[3\], p15.s
+.*: 056d39ef pmov z15\[2\], p15.s
+.*: 056938e8 pmov z8, p7.s
+.*: 05a93800 pmov z0, p0.d
+.*: 05a9381f pmov z31, p0.d
+.*: 05ef3800 pmov z0\[7\], p0.d
+.*: 05a939e0 pmov z0, p15.d
+.*: 05ef39ff pmov z31\[7\], p15.d
+.*: 05af39ef pmov z15\[3\], p15.d
+.*: 05a938e8 pmov z8, p7.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7.s b/gas/testsuite/gas/aarch64/sve2p1-7.s
new file mode 100644
index 00000000000..3d16548460a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7.s
@@ -0,0 +1,63 @@
+/* PMOV (to predicate). */
+pmov p0.b, z0
+pmov p15.b, z0
+pmov p0.b, z31
+pmov p15.b, z31
+pmov p15.b, z31[0]
+pmov p7.b, z15
+
+pmov p0.h, z0[0]
+pmov p15.h, z0[0]
+pmov p0.h, z31[0]
+pmov p0.h, z0[1]
+pmov p15.h, z31[1]
+pmov p7.h, z15[0]
+pmov p3.h, z8
+
+pmov p0.s, z0[0]
+pmov p15.s, z0[0]
+pmov p0.s, z31[0]
+pmov p0.s, z0[3]
+pmov p15.s, z31[3]
+pmov p7.s, z15[1]
+pmov p3.s, z8
+
+pmov p0.d, z0[0]
+pmov p15.d, z0[0]
+pmov p0.d, z31[0]
+pmov p0.d, z0[7]
+pmov p15.d, z31[7]
+pmov p7.d, z15[3]
+pmov p3.d, z8
+
+/* PMOV (to vector). */
+pmov z0, p0.b
+pmov z31, p0.b
+pmov z0, p15.b
+pmov z31, p15.b
+pmov z0[0], p7.b
+pmov z15[0], p7.b
+
+pmov z0[0], p0.h
+pmov z31[0], p0.h
+pmov z0[1], p0.h
+pmov z0[0], p15.h
+pmov z31[1], p15.h
+pmov z15[0], p15.h
+pmov z8, p7.h
+
+pmov z0[0], p0.s
+pmov z31[0], p0.s
+pmov z0[3], p0.s
+pmov z0[0], p15.s
+pmov z31[3], p15.s
+pmov z15[2], p15.s
+pmov z8, p7.s
+
+pmov z0[0], p0.d
+pmov z31[0], p0.d
+pmov z0[7], p0.d
+pmov z0[0], p15.d
+pmov z31[7], p15.d
+pmov z15[3], p15.d
+pmov z8, p7.d
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9daa911394f..5baa8edb0b5 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -857,6 +857,14 @@ enum aarch64_opnd
AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
+ AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
+ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
+ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
+ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
+ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
+ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
+ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
+ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 0b090557808..0e726102693 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -387,6 +387,8 @@ const aarch64_field fields[] =
{ 5, 14 }, /* imm14: in test bit and branch instructions. */
{ 0, 16 }, /* imm16_0: in udf instruction. */
{ 5, 16 }, /* imm16_5: in exception instructions. */
+ { 17, 1 }, /* imm17_1: in 1 bit element index. */
+ { 17, 2 }, /* imm17_2: in 2 bits element index. */
{ 5, 19 }, /* imm19: e.g. in CBZ. */
{ 0, 26 }, /* imm26: in unconditional branch instructions. */
{ 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
@@ -1874,6 +1876,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_Zn_INDEX3_14:
case AARCH64_OPND_SME_Zn_INDEX3_15:
case AARCH64_OPND_SME_Zn_INDEX4_14:
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
size = get_operand_fields_width (get_operand_from_code (type)) - 5;
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
0, (1 << size) - 1))
@@ -4248,11 +4258,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_Zt:
case AARCH64_OPND_SME_Zm:
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
- snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
+ snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
else
- snprintf (buf, size, "%s",
- style_reg (styler, "z%d.%s", opnd->reg.regno,
- aarch64_get_qualifier_name (opnd->qualifier)));
+ snprintf (buf, size, "%s",
+ style_reg (styler, "z%d.%s", opnd->reg.regno,
+ aarch64_get_qualifier_name (opnd->qualifier)));
break;
case AARCH64_OPND_SVE_ZnxN:
@@ -4307,6 +4317,22 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
style_imm (styler, "%" PRIi64, opnd->reglane.index));
break;
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
+ if (opnd->reglane.index == 0)
+ snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
+ else
+ snprintf (buf, size, "%s[%s]",
+ style_reg (styler, "z%d", opnd->reglane.regno),
+ style_imm (styler, "%" PRIi64, opnd->reglane.index));
+ break;
+
case AARCH64_OPND_SME_ZAda_1b:
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index e97ea5d27f2..49310960305 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -191,6 +191,8 @@ enum aarch64_field_kind
FLD_imm14,
FLD_imm16_0,
FLD_imm16_5,
+ FLD_imm17_1,
+ FLD_imm17_2,
FLD_imm19,
FLD_imm26,
FLD_immb,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0bd2cc0c34b..ad0d8ae7be6 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1567,6 +1567,10 @@
QLF3(S_B,P_Z,S_B), \
QLF3(S_B,P_M,S_B), \
}
+#define OP_SVE_BU \
+{ \
+ QLF2(S_B,NIL), \
+}
#define OP_SVE_BUB \
{ \
QLF3(S_B,NIL,S_B), \
@@ -1869,9 +1873,21 @@
{ \
QLF3(S_S,P_Z,NIL), \
}
-#define OP_SVE_UB \
-{ \
- QLF2(NIL,S_B), \
+#define OP_SVE_UB \
+{ \
+ QLF2(NIL,S_B), \
+}
+#define OP_SVE_UD \
+{ \
+ QLF2(NIL,S_D), \
+}
+#define OP_SVE_UH \
+{ \
+ QLF2(NIL,S_H), \
+}
+#define OP_SVE_US \
+{ \
+ QLF2(NIL,S_S), \
}
#define OP_SVE_UUD \
{ \
@@ -6649,6 +6665,16 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SVE2p1_INSN("zipq1",0x4400e000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
SVE2p1_INSN("zipq2",0x4400e400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
+ SVE2p1_INSN("pmov",0x052a3800, 0xfffffc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn0_INDEX), OP_SVE_BU, 0, 0),
+ SVE2p1_INSN("pmov",0x052c3800, 0xfffdfc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn1_17_INDEX), OP_SVE_HU, 0, 0),
+ SVE2p1_INSN("pmov",0x05683800, 0xfff9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn2_18_INDEX), OP_SVE_SU, 0, 0),
+ SVE2p1_INSN("pmov",0x05a83800, 0xffb9fc10, sve_misc, 0, OP2 (SVE_Pd, SVE_Zn3_22_INDEX), OP_SVE_DU, 0, 0),
+
+ SVE2p1_INSN("pmov",0x052b3800, 0xfffffe00, sve_misc, 0, OP2 (SVE_Zd0_INDEX, SVE_Pg4_5), OP_SVE_UB, 0, 0),
+ SVE2p1_INSN("pmov",0x052d3800, 0xfffdfe00, sve_misc, 0, OP2 (SVE_Zd1_17_INDEX, SVE_Pg4_5), OP_SVE_UH, 0, 0),
+ SVE2p1_INSN("pmov",0x05693800, 0xfff9fe00, sve_misc, 0, OP2 (SVE_Zd2_18_INDEX, SVE_Pg4_5), OP_SVE_US, 0, 0),
+ SVE2p1_INSN("pmov",0x05a93800, 0xffb9fe00, sve_misc, 0, OP2 (SVE_Zd3_22_INDEX, SVE_Pg4_5), OP_SVE_UD, 0, 0),
+
SVE2p1_INSN("ld1q",0xc400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_QZD, F_OD (1), 0),
SVE2p1_INSN("ld2q",0xa490e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_QZU, F_OD (2), 0),
SVE2p1_INSN("ld3q",0xa510e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x3xVL), OP_SVE_QZU, F_OD (3), 0),
@@ -7478,6 +7504,28 @@ const struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \
F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \
+ Y(SVE_REG, regno, "SVE_Zn0_INDEX", 0, F(FLD_SVE_Zn), \
+ "an SVE vector register with option zero index") \
+ Y(SVE_REG, simple_index, "SVE_Zn1_17_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_imm17_1), \
+ "an SVE vector register with optional one bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zn2_18_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_imm17_2), \
+ "an SVE vector register with optional two bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zn3_22_INDEX", 0, \
+ F(FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2), \
+ "an SVE vector register with optional three bit index") \
+ Y(SVE_REG, regno, "SVE_Zd0_INDEX", 0, F(FLD_SVE_Zd), \
+ "an SVE vector register with option zero index") \
+ Y(SVE_REG, simple_index, "SVE_Zd1_17_INDEX", 0, \
+ F(FLD_SVE_Zd, FLD_imm17_1), \
+ "an SVE vector register with optional one bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zd2_18_INDEX", 0, \
+ F(FLD_SVE_Zd, FLD_imm17_2), \
+ "an SVE vector register with optional two bit index") \
+ Y(SVE_REG, simple_index, "SVE_Zd3_22_INDEX", 0, \
+ F(FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2), \
+ "an SVE vector register with optional three bit index") \
Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \
"VLx2 or VLx4") \
Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v1 12/12] aarch64: Add support for sve2p1 pmov instruction (regenerated files).
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (10 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction Srinath Parvathaneni
@ 2024-07-04 12:40 ` Srinath Parvathaneni
2024-07-08 16:16 ` [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Richard Earnshaw (lists)
12 siblings, 0 replies; 15+ messages in thread
From: Srinath Parvathaneni @ 2024-07-04 12:40 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Srinath Parvathaneni
[-- Attachment #1: Type: text/plain, Size: 297 bytes --]
This patch includes the regenerated files for
aarch64: Add support for sve2p1 pmov instruction.
---
opcodes/aarch64-asm-2.c | 40 ++--
opcodes/aarch64-dis-2.c | 500 ++++++++++++++++++++++++----------------
opcodes/aarch64-opc-2.c | 8 +
3 files changed, 330 insertions(+), 218 deletions(-)
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: v1-0012-aarch64-Add-support-for-sve2p1-pmov-instruction-r.patch --]
[-- Type: text/x-patch; name="v1-0012-aarch64-Add-support-for-sve2p1-pmov-instruction-r.patch", Size: 123887 bytes --]
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 00d10f1e151..bfc2d8027c2 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -687,12 +687,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 267:
case 268:
case 269:
+ case 303:
+ case 307:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 305:
- case 308:
+ case 313:
+ case 316:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -707,7 +709,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 310:
+ case 318:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -734,6 +736,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
+ case 304:
+ case 305:
+ case 306:
+ case 308:
+ case 309:
+ case 310:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -784,13 +792,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 211:
case 212:
case 272:
- case 303:
- case 304:
- case 306:
- case 307:
- case 309:
+ case 311:
+ case 312:
case 314:
case 315:
+ case 317:
+ case 322:
+ case 323:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -1002,16 +1010,16 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 284:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 311:
- case 312:
- case 313:
- return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 316:
- case 317:
- case 318:
case 319:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 320:
+ case 321:
+ return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
+ case 325:
+ case 326:
+ case 327:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 328:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 6458bbca0e8..64407afaca4 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3401;
+ return 3409;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3402;
+ return 3410;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3403;
+ return 3411;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3469;
+ return 3477;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3468;
+ return 3476;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3462;
+ return 3470;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3447;
+ return 3455;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3461;
+ return 3469;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3454;
+ return 3462;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3453;
+ return 3461;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3460;
+ return 3468;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3440;
+ return 3448;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3441;
+ return 3449;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3452;
+ return 3460;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3471;
+ return 3479;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3446;
+ return 3454;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3470;
+ return 3478;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3472;
+ return 3480;
}
else
{
@@ -3155,7 +3155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3466;
+ return 3474;
}
else
{
@@ -3163,7 +3163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3467;
+ return 3475;
}
}
}
@@ -3218,7 +3218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3464;
+ return 3472;
}
else
{
@@ -3226,7 +3226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3465;
+ return 3473;
}
}
}
@@ -3280,7 +3280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3450;
+ return 3458;
}
else
{
@@ -3288,7 +3288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3451;
+ return 3459;
}
}
}
@@ -3350,7 +3350,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3458;
+ return 3466;
}
else
{
@@ -3358,7 +3358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3459;
+ return 3467;
}
}
}
@@ -3413,7 +3413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3456;
+ return 3464;
}
else
{
@@ -3421,7 +3421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3457;
+ return 3465;
}
}
}
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3463;
+ return 3471;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3455;
+ return 3463;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3404;
+ return 3412;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3405;
+ return 3413;
}
}
}
@@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3444;
+ return 3452;
}
else
{
@@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3445;
+ return 3453;
}
}
}
@@ -4038,7 +4038,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3448;
+ return 3456;
}
else
{
@@ -4046,7 +4046,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3449;
+ return 3457;
}
}
}
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3406;
+ return 3414;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3407;
+ return 3415;
}
}
}
@@ -4398,7 +4398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3442;
+ return 3450;
}
else
{
@@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3443;
+ return 3451;
}
}
}
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3378;
+ return 3386;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3375;
+ return 3383;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3370;
+ return 3378;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3376;
+ return 3384;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3377;
+ return 3385;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3371;
+ return 3379;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3372;
+ return 3380;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3366;
+ return 3374;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3367;
+ return 3375;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3373;
+ return 3381;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3374;
+ return 3382;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3368;
+ return 3376;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3369;
+ return 3377;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3380;
+ return 3388;
}
}
else
@@ -5774,7 +5774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3379;
+ return 3387;
}
else
{
@@ -5782,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3381;
+ return 3389;
}
}
}
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3382;
+ return 3390;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3383;
+ return 3391;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3384;
+ return 3392;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3385;
+ return 3393;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3386;
+ return 3394;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3388;
+ return 3396;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3387;
+ return 3395;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3389;
+ return 3397;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3391;
+ return 3399;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3390;
+ return 3398;
}
}
}
@@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3327;
+ return 3335;
}
else
{
@@ -16696,7 +16696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3336;
+ return 3344;
}
else
{
@@ -16706,7 +16706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3335;
+ return 3343;
}
else
{
@@ -16714,7 +16714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3337;
+ return 3345;
}
}
}
@@ -17380,7 +17380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3328;
+ return 3336;
}
}
}
@@ -17516,7 +17516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3331;
+ return 3339;
}
}
else
@@ -17661,7 +17661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3338;
+ return 3346;
}
}
else
@@ -17704,7 +17704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3339;
+ return 3347;
}
}
else
@@ -17745,7 +17745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3340;
+ return 3348;
}
}
}
@@ -17774,7 +17774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3427;
+ return 3435;
}
}
else
@@ -17783,7 +17783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3429;
+ return 3437;
}
}
else
@@ -17824,7 +17824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3439;
+ return 3447;
}
}
else
@@ -17857,7 +17857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3425;
+ return 3433;
}
}
else
@@ -17928,7 +17928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3430;
+ return 3438;
}
}
else
@@ -17937,7 +17937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3426;
+ return 3434;
}
}
else
@@ -17946,7 +17946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3431;
+ return 3439;
}
}
else
@@ -17955,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3432;
+ return 3440;
}
}
else
@@ -17982,7 +17982,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3428;
+ return 3436;
}
}
else
@@ -18000,7 +18000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3435;
+ return 3443;
}
}
else
@@ -18009,7 +18009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3438;
+ return 3446;
}
}
else
@@ -18042,7 +18042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3424;
+ return 3432;
}
}
else
@@ -18051,7 +18051,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3433;
+ return 3441;
}
}
else
@@ -18083,7 +18083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3437;
+ return 3445;
}
}
else
@@ -18382,7 +18382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3334;
+ return 3342;
}
}
else
@@ -18397,7 +18397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3434;
+ return 3442;
}
else
{
@@ -18405,7 +18405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3436;
+ return 3444;
}
}
else
@@ -19057,11 +19057,11 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 16) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
@@ -19082,59 +19082,147 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1x1000001110xxxxxxxxxx
- rev. */
- return 1869;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx100100001110xxxxxxxxxx
+ insr. */
+ return 1559;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx110100001110xxxxxxxxxx
+ insr. */
+ return 1560;
+ }
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx10x100001110xxxxxxxxxx
- insr. */
- return 1559;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx11x100001110xxxxxxxxxx
- insr. */
- return 1560;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x10001110xxxxxxxxxx
+ uunpklo. */
+ return 2080;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx10001110xxxxxxxxxx
- uunpklo. */
- return 2080;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001010x0001110xxxxxxxxxx
+ pmov. */
+ return 3327;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001011x0001110xxxxxxxxxx
+ pmov. */
+ return 3328;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x101101xx0001110xxxxxxxxxx
+ pmov. */
+ return 3329;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x11x101xx0001110xxxxxxxxxx
+ pmov. */
+ return 3330;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx111xx0001110xxxxxxxxxx
+ rev. */
+ return 1869;
+ }
}
}
else
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx01001110xxxxxxxxxx
- sunpkhi. */
- return 2016;
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x01001110xxxxxxxxxx
+ sunpkhi. */
+ return 2016;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x11001110xxxxxxxxxx
+ uunpkhi. */
+ return 2079;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx11001110xxxxxxxxxx
- uunpkhi. */
- return 2079;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001x10x1001110xxxxxxxxxx
+ pmov. */
+ return 3331;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001x11x1001110xxxxxxxxxx
+ pmov. */
+ return 3332;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1011x1xx1001110xxxxxxxxxx
+ pmov. */
+ return 3333;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x11x1x1xx1001110xxxxxxxxxx
+ pmov. */
+ return 3334;
+ }
}
}
}
@@ -20772,7 +20860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3396;
+ return 3404;
}
}
else
@@ -20781,7 +20869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3397;
+ return 3405;
}
}
else
@@ -20794,7 +20882,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3398;
+ return 3406;
}
else
{
@@ -20802,7 +20890,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101101xxxxxxxxxx
luti4. */
- return 3399;
+ return 3407;
}
}
else
@@ -20811,7 +20899,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x11xxxxxxxxxx
luti4. */
- return 3400;
+ return 3408;
}
}
}
@@ -21762,7 +21850,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x00xxxxxxxxxx
f1cvt. */
- return 3358;
+ return 3366;
}
else
{
@@ -21770,7 +21858,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x10xxxxxxxxxx
bf1cvt. */
- return 3354;
+ return 3362;
}
}
else
@@ -21781,7 +21869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x01xxxxxxxxxx
f2cvt. */
- return 3359;
+ return 3367;
}
else
{
@@ -21789,7 +21877,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx001000001x11xxxxxxxxxx
bf2cvt. */
- return 3355;
+ return 3363;
}
}
}
@@ -21834,7 +21922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x00xxxxxxxxxx
fcvtn. */
- return 3363;
+ return 3371;
}
else
{
@@ -21842,7 +21930,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x10xxxxxxxxxx
bfcvtn. */
- return 3362;
+ return 3370;
}
}
else
@@ -21853,7 +21941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x01xxxxxxxxxx
fcvtnb. */
- return 3364;
+ return 3372;
}
else
{
@@ -21861,7 +21949,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1010001x11xxxxxxxxxx
fcvtnt. */
- return 3365;
+ return 3373;
}
}
}
@@ -21922,7 +22010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x00xxxxxxxxxx
f1cvtlt. */
- return 3360;
+ return 3368;
}
else
{
@@ -21930,7 +22018,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x10xxxxxxxxxx
bf1cvtlt. */
- return 3356;
+ return 3364;
}
}
else
@@ -21941,7 +22029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x01xxxxxxxxxx
f2cvtlt. */
- return 3361;
+ return 3369;
}
else
{
@@ -21949,7 +22037,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x1xx0x1001001x11xxxxxxxxxx
bf2cvtlt. */
- return 3357;
+ return 3365;
}
}
}
@@ -23275,7 +23363,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x01xxxx111xxxxxxxxxxxxx
ld3q. */
- return 3329;
+ return 3337;
}
else
{
@@ -23283,7 +23371,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x01xxxx111xxxxxxxxxxxxx
ld4q. */
- return 3330;
+ return 3338;
}
}
}
@@ -24456,7 +24544,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x10x1xxxxx100xxxxxxxxxxxxx
ld3q. */
- return 3332;
+ return 3340;
}
else
{
@@ -24464,7 +24552,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x11x1xxxxx100xxxxxxxxxxxxx
ld4q. */
- return 3333;
+ return 3341;
}
}
else
@@ -26529,7 +26617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110100xxxxxxxx100xxxxxxxxxx
luti2. */
- return 3392;
+ return 3400;
}
}
}
@@ -26543,7 +26631,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx000xxxxxxxxxx
luti4. */
- return 3394;
+ return 3402;
}
else
{
@@ -26551,7 +26639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxxxx100xxxxxxxxxx
luti4. */
- return 3395;
+ return 3403;
}
}
else
@@ -26560,7 +26648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110110xxxxxxxxx00xxxxxxxxxx
luti2. */
- return 3393;
+ return 3401;
}
}
}
@@ -26676,7 +26764,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3416;
+ return 3424;
}
else
{
@@ -26684,7 +26772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3418;
+ return 3426;
}
}
else
@@ -26695,7 +26783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3417;
+ return 3425;
}
else
{
@@ -26703,7 +26791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3419;
+ return 3427;
}
}
}
@@ -26791,7 +26879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3349;
+ return 3357;
}
else
{
@@ -26799,7 +26887,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx11101xxxxxxxxxx
fcvtn2. */
- return 3350;
+ return 3358;
}
}
else
@@ -26808,7 +26896,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x10xxxxxx11101xxxxxxxxxx
fcvtn. */
- return 3351;
+ return 3359;
}
}
}
@@ -26951,7 +27039,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3408;
+ return 3416;
}
else
{
@@ -26961,7 +27049,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3410;
+ return 3418;
}
else
{
@@ -26971,7 +27059,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3412;
+ return 3420;
}
else
{
@@ -26979,7 +27067,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3413;
+ return 3421;
}
}
}
@@ -27253,7 +27341,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx101110110xxxxx0x1111xxxxxxxxxx
fscale. */
- return 3352;
+ return 3360;
}
}
}
@@ -28645,7 +28733,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110001xxxx1011110xxxxxxxxxx
f1cvtl. */
- return 3345;
+ return 3353;
}
else
{
@@ -28653,7 +28741,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110001xxxx1011110xxxxxxxxxx
f1cvtl2. */
- return 3346;
+ return 3354;
}
}
else
@@ -28664,7 +28752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110101xxxx1011110xxxxxxxxxx
bf1cvtl. */
- return 3341;
+ return 3349;
}
else
{
@@ -28672,7 +28760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110101xxxx1011110xxxxxxxxxx
bf1cvtl2. */
- return 3342;
+ return 3350;
}
}
}
@@ -28686,7 +28774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110011xxxx1011110xxxxxxxxxx
f2cvtl. */
- return 3347;
+ return 3355;
}
else
{
@@ -28694,7 +28782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110011xxxx1011110xxxxxxxxxx
f2cvtl2. */
- return 3348;
+ return 3356;
}
}
else
@@ -28705,7 +28793,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101110111xxxx1011110xxxxxxxxxx
bf2cvtl. */
- return 3343;
+ return 3351;
}
else
{
@@ -28713,7 +28801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101110111xxxx1011110xxxxxxxxxx
bf2cvtl2. */
- return 3344;
+ return 3352;
}
}
}
@@ -30712,7 +30800,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx1011101x1xxxxx111111xxxxxxxxxx
fscale. */
- return 3353;
+ return 3361;
}
}
}
@@ -32428,7 +32516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3409;
+ return 3417;
}
else
{
@@ -32458,7 +32546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3411;
+ return 3419;
}
else
{
@@ -32468,7 +32556,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3414;
+ return 3422;
}
else
{
@@ -32476,7 +32564,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3415;
+ return 3423;
}
}
}
@@ -33018,7 +33106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3420;
+ return 3428;
}
else
{
@@ -33026,7 +33114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3422;
+ return 3430;
}
}
else
@@ -33057,7 +33145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3421;
+ return 3429;
}
else
{
@@ -33065,7 +33153,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3423;
+ return 3431;
}
}
}
@@ -34553,12 +34641,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 267:
case 268:
case 269:
+ case 303:
+ case 307:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 305:
- case 308:
+ case 313:
+ case 316:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -34578,7 +34668,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 310:
+ case 318:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -34605,6 +34695,12 @@ aarch64_extract_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
+ case 304:
+ case 305:
+ case 306:
+ case 308:
+ case 309:
+ case 310:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -34656,13 +34752,13 @@ aarch64_extract_operand (const aarch64_operand *self,
case 211:
case 212:
case 272:
- case 303:
- case 304:
- case 306:
- case 307:
- case 309:
+ case 311:
+ case 312:
case 314:
case 315:
+ case 317:
+ case 322:
+ case 323:
return aarch64_ext_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -34876,16 +34972,16 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
case 284:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 311:
- case 312:
- case 313:
- return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
- case 316:
- case 317:
- case 318:
case 319:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 320:
+ case 321:
+ return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
+ case 325:
+ case 326:
+ case 327:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 328:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index d42fea40f60..926b310461f 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -327,6 +327,14 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register with option zero index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_1}, "an SVE vector register with optional one bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm17_2}, "an SVE vector register with optional two bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register with option zero index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_1}, "an SVE vector register with optional one bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_imm17_2}, "an SVE vector register with optional two bit index"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd, FLD_SVE_i3h, FLD_imm17_2}, "an SVE vector register with optional three bit index"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction.
2024-07-04 12:40 ` [PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction Srinath Parvathaneni
@ 2024-07-08 16:15 ` Richard Earnshaw (lists)
0 siblings, 0 replies; 15+ messages in thread
From: Richard Earnshaw (lists) @ 2024-07-08 16:15 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: nickc
On 04/07/2024 13:40, Srinath Parvathaneni wrote:
>
> This patch adds support for followign SVE2p1 instruction, spec is available here [1].
>
> 1. PMOV (to vector)
> 2. PMOV (to predicate)
>
> Both pmov (to vector) and pmov (to predicate) have destination scalable vector
> register and source scalable vector register respectively as an operand with no
> suffix and optional index. To handle this case we have added 8 new operands in
> this patch.
>
> AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
> AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
> AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
> AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
> AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
> AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
> AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
> AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
>
> Since the index of the <Zd> operand is optional, the index part is
> dropped in disassembly in both the cases of "no index" or "zero index".
>
> As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
> PMOV <Pn>.D, <Zd>{[<imm>]}
>
> Example1:
> Assembly: pmov z5[0], p6.d
> Disassembly: pmov z5, p6.d
>
> Assembly: pmov z5, p6.d
> Disassembly: pmov z5, p6.d
>
> Example2:
> Assembly: pmov p4.b, z5[0]
> Disassembly: pmov p4.b, z5
>
> Assembly: pmov p4.b, z5
> Disassembly: pmov p4.b, z5
> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
> ---
> gas/config/tc-aarch64.c | 28 ++++-
> gas/testsuite/gas/aarch64/sve2p1-7-invalid.d | 3 +
> gas/testsuite/gas/aarch64/sve2p1-7-invalid.l | 118 +++++++++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-7-invalid.s | 76 ++++++++++++
> gas/testsuite/gas/aarch64/sve2p1-7.d | 64 ++++++++++
> gas/testsuite/gas/aarch64/sve2p1-7.s | 63 ++++++++++
> include/opcode/aarch64.h | 8 ++
> opcodes/aarch64-opc.c | 34 +++++-
> opcodes/aarch64-opc.h | 2 +
> opcodes/aarch64-tbl.h | 54 ++++++++-
> 10 files changed, 440 insertions(+), 10 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.s
>
+ FLAGS includes PTR_OPTIONAL_INDEX, which has been introduced to parse
+ instructions with optional index operands. */
This will read strangely ten years from now. Just say:
FLAGS includes PTR_OPTIONAL_INDEX to handle instructions with optional index operands.
R.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions.
2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni
` (11 preceding siblings ...)
2024-07-04 12:40 ` [PATCH v1 12/12] aarch64: Add support for sve2p1 pmov instruction (regenerated files) Srinath Parvathaneni
@ 2024-07-08 16:16 ` Richard Earnshaw (lists)
12 siblings, 0 replies; 15+ messages in thread
From: Richard Earnshaw (lists) @ 2024-07-08 16:16 UTC (permalink / raw)
To: Srinath Parvathaneni, binutils; +Cc: nickc
On 04/07/2024 13:40, Srinath Parvathaneni wrote:
> Hi,
>
> This patch series adds the support for remaining aarch64 sve2p1 instructions
> and the spec can be found here [1].
>
> Srinath Parvathaneni (12):
> aarch64: Add support for sve2p1 orqv instruction.
> aarch64: Add support for sve2p1 orqv instruction (regenerated files).
> aarch64: Add support for sve2p1 tblq instruction.
> aarch64: Add support for sve2p1 tblq instruction (regenerated files).
> aarch64: Add support for sve2p1 uzpq[1-2] instructions.
> aarch64: Add support for sve2p1 uzpq[1-2] instructions (regenerated files).
> aarch64: Add support for sve2p1 zipq[1-2] instructions.
> aarch64: Add support for sve2p1 zipq[1-2] instructions (regenerated files).
> aarch64: Add support for sve2p1 tbxq instruction.
> aarch64: Add support for sve2p1 tbxq instruction (regenerated files).
> aarch64: Add support for sve2p1 pmov instruction.
> aarch64: Add support for sve2p1 pmov instruction (regenerated files).
>
> [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
>
> Ok for binutils-master?
>
> Regards,
> Srinath.
>
> gas/config/tc-aarch64.c | 28 +-
> gas/testsuite/gas/aarch64/sve2p1-5-invalid.d | 3 +
> gas/testsuite/gas/aarch64/sve2p1-5-invalid.l | 27 +
> gas/testsuite/gas/aarch64/sve2p1-5-invalid.s | 8 +
> gas/testsuite/gas/aarch64/sve2p1-5.d | 18 +
> gas/testsuite/gas/aarch64/sve2p1-5.s | 8 +
> gas/testsuite/gas/aarch64/sve2p1-6-invalid.d | 3 +
> gas/testsuite/gas/aarch64/sve2p1-6-invalid.l | 78 +++
> gas/testsuite/gas/aarch64/sve2p1-6-invalid.s | 36 +
> gas/testsuite/gas/aarch64/sve2p1-6.d | 58 ++
> gas/testsuite/gas/aarch64/sve2p1-6.s | 53 ++
> gas/testsuite/gas/aarch64/sve2p1-7-invalid.d | 3 +
> gas/testsuite/gas/aarch64/sve2p1-7-invalid.l | 118 ++++
> gas/testsuite/gas/aarch64/sve2p1-7-invalid.s | 76 +++
> gas/testsuite/gas/aarch64/sve2p1-7.d | 64 ++
> gas/testsuite/gas/aarch64/sve2p1-7.s | 63 ++
> include/opcode/aarch64.h | 8 +
> opcodes/aarch64-asm-2.c | 40 +-
> opcodes/aarch64-dis-2.c | 651 ++++++++++++-------
> opcodes/aarch64-opc-2.c | 8 +
> opcodes/aarch64-opc.c | 34 +-
> opcodes/aarch64-opc.h | 2 +
> opcodes/aarch64-tbl.h | 61 +-
> 23 files changed, 1183 insertions(+), 265 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-5.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-6.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p1-7.s
>
There's a small comment cleanup needed on 11/12, but otherwise this series is fine.
OK with that change.
R.
^ permalink raw reply [flat|nested] 15+ messages in threadend of thread, other threads:[~2024-07-08 16:16 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-07-04 12:40 [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 01/12] aarch64: Add support for sve2p1 orqv instruction Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 02/12] aarch64: Add support for sve2p1 orqv instruction (regenerated files) Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 03/12] aarch64: Add support for sve2p1 tblq instruction Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 04/12] aarch64: Add support for sve2p1 tblq instruction (regenerated files) Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 05/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 06/12] aarch64: Add support for sve2p1 uzpq[1-2] instructions (regenerated files) Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 07/12] aarch64: Add support for sve2p1 zipq[1-2] instructions Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 08/12] aarch64: Add support for sve2p1 zipq[1-2] instructions (regenerated files) Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 09/12] aarch64: Add support for sve2p1 tbxq instruction Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 10/12] aarch64: Add support for sve2p1 tbxq instruction (regenerated files) Srinath Parvathaneni 2024-07-04 12:40 ` [PATCH v1 11/12] aarch64: Add support for sve2p1 pmov instruction Srinath Parvathaneni 2024-07-08 16:15 ` Richard Earnshaw (lists) 2024-07-04 12:40 ` [PATCH v1 12/12] aarch64: Add support for sve2p1 pmov instruction (regenerated files) Srinath Parvathaneni 2024-07-08 16:16 ` [PATCH v1 0/12][Binutils] aarch64: Add support for remaining sve2p1 instructions Richard Earnshaw (lists)
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