[PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb

["Andre Vieira (lists)" <andre.simoesdiasvieira@arm.com>]

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Hi,

This patch adds support for MVE instructions VQDMULLT and VQDMULLB.

gas/ChangeLog:

2019-05-01  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum operand_parse_code): Add new operand.
	(parse_operands): Handle new operand.
	(do_mve_vqdmull): New encoding function.
         (insns): Add entry for MVE mnemonics.
	* testsuite/gas/arm/mve-vqdmull-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmull-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmull-bad.s: New test.

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diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index a684f949c961d9a6c5a80578bfdc9864718e4a38..6c4b11ced574ffc49dabde7f84edd0682982292b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6926,6 +6926,7 @@ enum operand_parse_code
 		   GPR (no SP/SP)  */
   OP_RMQ,	/* MVE vector register.  */
   OP_RMQRZ,	/* MVE vector or ARM register including ZR.  */
+  OP_RMQRR,     /* MVE vector or ARM register.  */
 
   /* New operands for Armv8.1-M Mainline.  */
   OP_LR,	/* ARM LR register */
@@ -7284,6 +7285,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 	  po_reg_or_fail (REG_TYPE_NSDQ);
 	  inst.error = 0;
 	  break;
+	case OP_RMQRR:
+	  po_reg_or_goto (REG_TYPE_RN, try_rmq);
+	  break;
+	try_rmq:
 	case OP_RMQ:
 	  po_reg_or_fail (REG_TYPE_MQ);
 	  break;
@@ -17285,6 +17290,35 @@ do_mve_vhcadd (void)
   inst.is_neon = 1;
 }
 
+static void
+do_mve_vqdmull (void)
+{
+  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
+  struct neon_type_el et
+    = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
+
+  if (et.size == 32
+      && (inst.operands[0].reg == inst.operands[1].reg
+	  || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
+    as_tsktsk (BAD_MVE_SRCDEST);
+
+  if (inst.cond > COND_ALWAYS)
+    inst.pred_insn_type = INSIDE_VPT_INSN;
+  else
+    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+  if (rs == NS_QQQ)
+    {
+      mve_encode_qqq (et.size == 32, 64);
+      inst.instruction |= 1;
+    }
+  else
+    {
+      mve_encode_qqr (64, et.size == 32, 0);
+      inst.instruction |= 0x3 << 5;
+    }
+}
+
 static void
 do_mve_vadc (void)
 {
@@ -24841,6 +24875,8 @@ static const struct asm_opcode insns[] =
  mToC("vqdmlah",   ee000e60,	3, (RMQ, RMQ, RR),		mve_vqdmlah),
  mToC("vqdmlash",  ee001e60,	3, (RMQ, RMQ, RR),		mve_vqdmlah),
  mToC("vqrdmlash", ee001e40,	3, (RMQ, RMQ, RR),		mve_vqdmlah),
+ mToC("vqdmullt",  ee301f00,	3, (RMQ, RMQ, RMQRR),		mve_vqdmull),
+ mToC("vqdmullb",  ee300f00,	3, (RMQ, RMQ, RMQRR),		mve_vqdmull),
 
 #undef THUMB_VARIANT
 #define THUMB_VARIANT & mve_fp_ext
diff --git a/gas/testsuite/gas/arm/mve-vqdmull-bad.d b/gas/testsuite/gas/arm/mve-vqdmull-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..4eb6fb2dfc665ee696426b1b2a5fff616f2da173
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmull-bad.d
@@ -0,0 +1,5 @@
+#name: bad MVE VQDMULLT and VQDMULLB instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vqdmull-bad.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vqdmull-bad.l b/gas/testsuite/gas/arm/mve-vqdmull-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..1ddc335a7ffc90c63147c046824b650a682abbac
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmull-bad.l
@@ -0,0 +1,61 @@
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,q2'
+[^:]*:11: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,q2'
+[^:]*:12: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,q2'
+[^:]*:13: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,q2'
+[^:]*:14: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,q2'
+[^:]*:15: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,q2'
+[^:]*:16: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,q2'
+[^:]*:17: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,q2'
+[^:]*:18: Error: bad type in SIMD instruction -- `vqdmullt.s8 q0,q1,r2'
+[^:]*:19: Error: bad type in SIMD instruction -- `vqdmullt.u8 q0,q1,r2'
+[^:]*:20: Error: bad type in SIMD instruction -- `vqdmullt.i16 q0,q1,r2'
+[^:]*:21: Error: bad type in SIMD instruction -- `vqdmullt.s64 q0,q1,r2'
+[^:]*:22: Error: bad type in SIMD instruction -- `vqdmullb.s8 q0,q1,r2'
+[^:]*:23: Error: bad type in SIMD instruction -- `vqdmullb.u8 q0,q1,r2'
+[^:]*:24: Error: bad type in SIMD instruction -- `vqdmullb.i16 q0,q1,r2'
+[^:]*:25: Error: bad type in SIMD instruction -- `vqdmullb.s64 q0,q1,r2'
+[^:]*:26: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:27: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:28: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:29: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:30: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:31: Warning: 32-bit element size and same destination and source operands makes instruction UNPREDICTABLE
+[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:34: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:41: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
+[^:]*:42: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
+[^:]*:44: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
+[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmulltt.s32 q0,q1,q2'
+[^:]*:47: Error: instruction missing MVE vector predication code -- `vqdmullt.s32 q0,q1,q2'
+[^:]*:49: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
+[^:]*:50: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
+[^:]*:52: Error: syntax error -- `vqdmullbeq.s32 q0,q1,q2'
+[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vqdmullbt.s32 q0,q1,q2'
+[^:]*:55: Error: instruction missing MVE vector predication code -- `vqdmullb.s32 q0,q1,q2'
diff --git a/gas/testsuite/gas/arm/mve-vqdmull-bad.s b/gas/testsuite/gas/arm/mve-vqdmull-bad.s
new file mode 100644
index 0000000000000000000000000000000000000000..fac7d5f157c6b1caf70acada5db48127bd8eec26
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vqdmull-bad.s
@@ -0,0 +1,55 @@
+.macro cond op, lastreg
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\op\().s16 q0, q1, \lastreg
+.endr
+.endm
+
+.syntax unified
+.thumb
+vqdmullt.s8 q0, q1, q2
+vqdmullt.u8 q0, q1, q2
+vqdmullt.i16 q0, q1, q2
+vqdmullt.s64 q0, q1, q2
+vqdmullb.s8 q0, q1, q2
+vqdmullb.u8 q0, q1, q2
+vqdmullb.i16 q0, q1, q2
+vqdmullb.s64 q0, q1, q2
+vqdmullt.s8 q0, q1, r2
+vqdmullt.u8 q0, q1, r2
+vqdmullt.i16 q0, q1, r2
+vqdmullt.s64 q0, q1, r2
+vqdmullb.s8 q0, q1, r2
+vqdmullb.u8 q0, q1, r2
+vqdmullb.i16 q0, q1, r2
+vqdmullb.s64 q0, q1, r2
+vqdmullt.s32 q0, q0, q2
+vqdmullt.s32 q0, q1, q0
+vqdmullb.s32 q0, q0, q2
+vqdmullb.s32 q0, q1, q0
+vqdmullt.s32 q0, q0, r2
+vqdmullb.s32 q0, q0, r2
+vqdmullt.s16 q0, q0, sp
+vqdmullt.s16 q0, q0, pc
+vqdmullb.s16 q0, q0, sp
+vqdmullb.s16 q0, q0, pc
+cond vqdmullt, q2
+cond vqdmullb, q2
+cond vqdmullt, r2
+cond vqdmullb, r2
+it eq
+vqdmullteq.s32 q0, q1, q2
+vqdmullteq.s32 q0, q1, q2
+vpst
+vqdmullteq.s32 q0, q1, q2
+vqdmulltt.s32 q0, q1, q2
+vpst
+vqdmullt.s32 q0, q1, q2
+it eq
+vqdmullbeq.s32 q0, q1, q2
+vqdmullbeq.s32 q0, q1, q2
+vpst
+vqdmullbeq.s32 q0, q1, q2
+vqdmullbt.s32 q0, q1, q2
+vpst
+vqdmullb.s32 q0, q1, q2