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[PATCH 0/4] RISC-V: Fix disassembler types and styles
 2022-10-05 22:37 UTC  (21+ messages)
` [PATCH v2 0/6] "
  ` [PATCH v2 5/6] RISC-V: Fix T-Head immediate types on printing
  ` [PATCH v2 6/6] RISC-V: Print XTheadMemPair literal as "immediate"
  ` [PATCH v3 0/6] RISC-V: Fix disassembler types and styles
    ` [PATCH v3 1/6] RISC-V: Fix immediates to have "immediate" style
    ` [PATCH v3 2/6] RISC-V: Fix printf argument types corresponding %x
    ` [PATCH v3 3/6] RISC-V: Optimize riscv_disassemble_data printf
    ` [PATCH v3 4/6] RISC-V: Print comma and tabs as the "text" style
    ` [PATCH v3 5/6] RISC-V: Fix T-Head immediate types on printing
    ` [PATCH v3 6/6] RISC-V: Print XTheadMemPair literal as "immediate"

Support objcopy changing compression to or from zstd
 2022-10-05 21:04 UTC  (4+ messages)

Question regarding min reqd dejagnu version
 2022-10-05 18:28 UTC  (9+ messages)

[PATCH] Arm64: support CLEARBHB alias
 2022-10-05 17:48 UTC  (3+ messages)
` Ping: "

RFC: Sort tarballs created by the src-release.sh script
 2022-10-05 13:00 UTC  (16+ messages)

[RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Oct 06, 2022)
 2022-10-05 12:01 UTC 

[PATCH] bfd: xtensa: fix __stop_SECTION literal drop,
 2022-10-05 11:15 UTC  (2+ messages)

[PATCH] x86: drop "regmask" static variable
 2022-10-05  7:40 UTC 

☺ Buildbot (GNU Toolchain): binutils-gdb - build successful (master)
 2022-10-05  7:34 UTC 

[PATCH v3 0/7] x86: suffix handling changes
 2022-10-05  7:25 UTC  (8+ messages)
` [PATCH v3 1/7] x86: constify parse_insn()'s input
` [PATCH v3 2/7] x86: introduce Pass2 insn attribute
` [PATCH v3 3/7] x86: re-work insn/suffix recognition
` [PATCH v3 4/7] x86-64: further re-work insn/suffix recognition to also cover MOVSL
` [PATCH v3 5/7] ix86: don't recognize/derive Q suffix in the common case
` [PATCH v3 6/7] x86-64: allow HLE store of accumulator to absolute 32-bit address
` [PATCH v3 7/7] x86: move bad-use-of-TLS-reloc check

☠ Buildbot (GNU Toolchain): binutils-gdb - failed update (failure) (master)
 2022-10-05  4:52 UTC 

☺ Buildbot (GNU Toolchain): binutils-gdb - build successful (master)
 2022-10-05  4:41 UTC 

PR29647, objdump -S looping
 2022-10-05  4:23 UTC 

stab nearest_line bfd_malloc_and_get_section
 2022-10-05  4:22 UTC 

[PATCH 1/2] ld: Add --pdb option
 2022-10-05  4:20 UTC  (6+ messages)
` [PATCH 2/2] ld: Add minimal pdb generation

[RFC PATCH] bfd: use bfd_vma for the 64-bit version of put[lb] and get[lb]
 2022-10-05  2:59 UTC  (2+ messages)

☠ Buildbot (GNU Toolchain): binutils-gdb - failed update (failure) (master)
 2022-10-05  0:19 UTC 

[PATCH] gas: NEWS: Mention the T-Head extensions that were recently added
 2022-10-04 20:35 UTC  (3+ messages)

The GNU Toolchain Infrastructure Project
 2022-10-04 19:10 UTC  (14+ messages)

[PATCH] gprofng: fix build with --enable-pgo-build=lto
 2022-10-04 16:17 UTC 

[PATCH] RISC-V: Zicbo{m,p,z} adjustments to riscv_multi_subset_supports_ext()
 2022-10-04 16:08 UTC  (2+ messages)

ARMV7a: selected processor does not support requested special purpose register
 2022-10-04 15:10 UTC  (6+ messages)

☺ Buildbot (GNU Toolchain): binutils-gdb - build successful (master)
 2022-10-04 13:52 UTC 

[PATCH] compress .gnu.debuglto_.debug_* sections if requested
 2022-10-04 13:41 UTC  (6+ messages)

☠ Buildbot (GNU Toolchain): binutils-gdb - failed update (failure) (master)
 2022-10-04 13:34 UTC 

[PATCH 0/2] RISC-V: Fix buffer overflow after long instruction support
 2022-10-04 13:20 UTC  (20+ messages)
` [PATCH 1/2] RISC-V: Fix buffer overflow on print_insn_riscv
` [PATCH 2/2] gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction
` [PATCH v2 0/2] RISC-V: Fix buffer overflow after 176-bit instruction support
  ` [PATCH v2 1/2] RISC-V: Fix buffer overflow on print_insn_riscv
  ` [PATCH v2 2/2] gdb/riscv: Partial support for instructions up to 176-bits
  ` [PATCH v3 0/2] RISC-V: Fix buffer overflow after 176-bit instruction support
    ` [PATCH v3 1/2] RISC-V: Fix buffer overflow on print_insn_riscv
    ` [PATCH v3 2/2] gdb/riscv: Partial support for instructions up to 176-bit

[PATCH] RISC-V: Renamed INSN_CLASS for floating point in integer extensions
 2022-10-04 13:18 UTC 

[PATCH] opcodes/riscv: style csr names as registers
 2022-10-04  8:53 UTC  (4+ messages)

☺ Buildbot (GNU Toolchain): binutils-gdb - build successful (master)
 2022-10-04  8:25 UTC 

[PATCH V2] Ignore DWARF debug information for -gsplit-dwarf with dwarf-5
 2022-10-04  7:47 UTC  (3+ messages)

[PATCH v2] RISC-V: Add zhinx extension supports
 2022-10-04  7:46 UTC  (4+ messages)

[PATCH] ld/testsuite: consistently add board_ldflags when linking with GCC
 2022-10-04  7:36 UTC  (3+ messages)

[PATCH,V6 00/10] Definition and Implementation of CTF Frame format
 2022-10-04  6:53 UTC  (14+ messages)
` [PATCH,V1 00/14] Definition and support for SFrame unwind format
  ` [PATCH,V1 06/14] bfd: linker: merge .sframe sections
  ` [PATCH,V1 07/14] readelf/objdump: support for SFrame section

The GNU Toolchain Infrastructure Project
 2022-10-03 19:24 UTC  (4+ messages)

Risc - V failures inside ld-undefined
 2022-10-03 17:10 UTC  (4+ messages)

[PATCH 0/2] Disassembler styling for ARM
 2022-10-03 16:37 UTC  (5+ messages)
` [PATCHv2 "
  ` [PATCHv2 1/2] opcodes/arm: use '@' consistently for the comment character
  ` [PATCHv2 2/2] opcodes/arm: add disassembler styling for arm

[PATCH] diagnostics.h: GCC 13 got -Wself-move, breaks GDB build
 2022-10-03 14:36 UTC  (4+ messages)

☺ Buildbot (GNU Toolchain): binutils-gdb - build successful (master)
 2022-10-03 12:21 UTC 

Commit: readelf: Do not load section data from offset 0
 2022-10-03 12:19 UTC 

☠ Buildbot (GNU Toolchain): binutils-gdb - failed update (failure) (master)
 2022-10-03 11:59 UTC 

[PATCH 1/2] RISC-V: Output mapping symbols with ISA string
 2022-10-03 11:17 UTC  (2+ messages)

[PATCH v3] binutils, gdb: support zstd compressed debug sections
 2022-10-03  7:50 UTC  (8+ messages)
` [PATCH][RFC] add --enable-zstd-compressed-debug-sections configure option
          ` [PATCH 1/2] refactor usage of compressed_debug_section_type
          ` [PATCH 2/2] add --enable-default-compressed-debug-sections-algorithm configure option

[PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers
 2022-10-03  4:31 UTC  (7+ messages)

[RFC PATCH 0/1] RISC-V: Implement "extension variants" for diagnostics
 2022-10-01  8:25 UTC  (4+ messages)
` [RFC PATCH 1/1] RISC-V: Implement extension variants

[PATCH 0/1] RISC-V: Move supervisor instructions after all unprivileged ones
 2022-10-01  8:15 UTC  (4+ messages)
` [PATCH 1/1] "

[RFC PATCH 0/1] RISC-V: Common register pair framework
 2022-10-01  7:17 UTC  (3+ messages)
` [RFC PATCH 1/1] RISC-V: Implement common "

[PATCH] readelf: support zstd compressed debug sections [PR 29640]
 2022-10-01  6:20 UTC 

[PATCH] gold: add --compress-debug-sections=zstd [PR 29641]
 2022-10-01  2:38 UTC 

[PATCH] gold, dwp: support zstd compressed input debug sections [PR 29641]
 2022-10-01  1:44 UTC 

[PATCH] RISC-V: fix build after "Add support for arbitrary immediate encoding formats"
 2022-09-30 22:17 UTC  (2+ messages)

[PATCH] RISC-V: Eliminate long-casts of X_add_number in diagnostics
 2022-09-30 19:26 UTC  (5+ messages)

[RFC PATCH 0/1] RISC-V: Add privileged extensions without instructions/CSRs
 2022-09-30 15:44 UTC  (5+ messages)
` [RFC PATCH 1/1] "

[PATCH 0/2] RISC-V: Zfinx-related improvements (testcases and fmv.[sdq]) - SPLITTED
 2022-09-30 15:39 UTC  (6+ messages)
` [PATCH 1/2] RISC-V: Reorganize and enhance 'Zfinx' tests
` [PATCH 2/2] RISC-V: Relax "fmv.[sdq]" requirements

[PATCH RESEND v2] Aarch64: Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}
 2022-09-30 14:54 UTC  (4+ messages)

[PATCH 0/3] RISC-V: alias insn adjustments
 2022-09-30 14:43 UTC  (3+ messages)
` [PATCH] RISC-V: don't cast expressions' X_add_number to long in diagnostics

[PATCH 0/4] RISC-V/gas: assorted adjustments
 2022-09-30 14:39 UTC  (6+ messages)
` [PATCH 1/4] RISC-V/gas: drop riscv_subsets static variable
` [PATCH 2/4] RISC-V/gas: drop stray call to install_insn()
` [PATCH 3/4] RISC-V/gas: don't open-code insn_length()
` [PATCH 4/4] RISC-V/gas: allow generating up to 176-bit instructions with .insn

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