From: Yury Khrustalev <Yury.Khrustalev@arm.com>
To: "binutils@sourceware.org" <binutils@sourceware.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,
"nickc@redhat.com" <nickc@redhat.com>
Subject: [PATCH 2/2] aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructions
Date: Tue, 5 Mar 2024 13:54:29 +0000 [thread overview]
Message-ID: <A6279C0C-F21C-4743-8C9E-578D77CEF6A3@arm.com> (raw)
In-Reply-To: <4A36B5D7-1175-47DF-97CD-DA49D77842ED@arm.com>
From 0bc43890ea8e76a8d0a652a4591abfac2c90c7a3 Mon Sep 17 00:00:00 2001
From: Yury Khrustalev <yury.khrustalev@arm.com>
Date: Mon, 26 Feb 2024 13:43:48 +0000
Subject: [PATCH 2/2] aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT
instructions
The following instructions are added in this patch:
- ADDPT (predicated): Add checked pointer vectors (predicated).
- ADDPT (unpredicated): Add checked pointer vectors (unpredicated).
- SUBPT (predicated): Subtract checked pointer vectors (predicated).
- SUBPT (unpredicated): Subtract checked pointer vectors (unpredicated).
- MADPT: Multiply-add checked pointer vectors, writing multiplicand
- MLAPT: Multiply-add checked pointer vectors, writing addend
These instructions are part of Checked Pointer Arithmetic extension
and are enabled when both CPA and SVE are enabled. To achieve this,
both flag "+sve" and "+cpa" should be active.
This patch adds assembler and disassembler support for these instructions
with relevant checks. Tests are included as well.
Regression tested on the aarch64-none-linux-gnu target and no regressions
have been found.
---
gas/testsuite/gas/aarch64/cpa-addsub-bad.l | 4 +-
gas/testsuite/gas/aarch64/cpa-sve-bad.d | 4 +
gas/testsuite/gas/aarch64/cpa-sve-bad.l | 92 ++++++++++++++++++++++
gas/testsuite/gas/aarch64/cpa-sve-bad.s | 67 ++++++++++++++++
gas/testsuite/gas/aarch64/cpa-sve-neg.d | 7 ++
gas/testsuite/gas/aarch64/cpa-sve-neg.l | 7 ++
gas/testsuite/gas/aarch64/cpa-sve-neg.s | 6 ++
gas/testsuite/gas/aarch64/cpa-sve.d | 66 ++++++++++++++++
gas/testsuite/gas/aarch64/cpa-sve.s | 60 ++++++++++++++
opcodes/aarch64-tbl.h | 18 +++++
10 files changed, 329 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve-bad.d
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve-bad.l
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve-bad.s
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve-neg.d
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve-neg.l
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve-neg.s
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve.d
create mode 100644 gas/testsuite/gas/aarch64/cpa-sve.s
diff --git a/gas/testsuite/gas/aarch64/cpa-addsub-bad.l b/gas/testsuite/gas/aarch64/cpa-addsub-bad.l
index f5e8967662c..c0c671bbfdf 100644
--- a/gas/testsuite/gas/aarch64/cpa-addsub-bad.l
+++ b/gas/testsuite/gas/aarch64/cpa-addsub-bad.l
@@ -5,7 +5,7 @@
.*: Error: only 'LSL' shift is permitted at operand 3 -- `addpt x5,x8,x0,asr#6'
.*: Error: shift amount out of range 0 to 7 at operand 3 -- `addpt x5,x8,x0,lsl#9'
.*: Error: expected an integer or zero register at operand 3 -- `addpt x5,x8,sp,lsl#5'
-.*: Error: expected an integer or stack pointer register at operand 1 -- `addpt xzr,x8,x0,lsl#3'
+.*: Error: unexpected register type at operand 1 -- `addpt xzr,x8,x0,lsl#3'
.*: Error: operand mismatch -- `subpt w5,w8,w0'
.*: Info:\s+did you mean this\?
@@ -13,7 +13,7 @@
.*: Error: only 'LSL' shift is permitted at operand 3 -- `subpt x5,x8,x0,asr#6'
.*: Error: shift amount out of range 0 to 7 at operand 3 -- `subpt x5,x8,x0,lsl#9'
.*: Error: expected an integer or zero register at operand 3 -- `subpt x5,x8,sp,lsl#5'
-.*: Error: expected an integer or stack pointer register at operand 1 -- `subpt xzr,x8,x0,lsl#3'
+.*: Error: unexpected register type at operand 1 -- `subpt xzr,x8,x0,lsl#3'
.*: Error: operand mismatch -- `maddpt w1,x2,x3,x4'
.*: Info:\s+did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/cpa-sve-bad.d b/gas/testsuite/gas/aarch64/cpa-sve-bad.d
new file mode 100644
index 00000000000..0abecd55ca5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve-bad.d
@@ -0,0 +1,4 @@
+#name: Incorrect input test for CPA+SVE instructions.
+#as: -march=armv8-a+sve+cpa
+#source: cpa-sve-bad.s
+#error_output: cpa-sve-bad.l
diff --git a/gas/testsuite/gas/aarch64/cpa-sve-bad.l b/gas/testsuite/gas/aarch64/cpa-sve-bad.l
new file mode 100644
index 00000000000..d7e3250d463
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve-bad.l
@@ -0,0 +1,92 @@
+.*: Assembler messages:
+
+.*: Error: operand mismatch -- `addpt z0.b,p0/m,z0.b,z0.b'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+addpt z0.d, p0/m, z0.d, z0.d
+.*: Error: operand 3 must be the same register as operand 1 -- `addpt z0.d,p0/m,z1.d,z0.d'
+.*: Error: operand mismatch -- `addpt z0.d,p0/m,z0.d,z0.s'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+addpt z0.d, p0/m, z0.d, z0.d
+.*: Error: operand mismatch -- `addpt z0.h,p0/m,z0.h,z0.d'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+addpt z0.d, p0/m, z0.d, z0.d
+.*: Error: expected an integer or stack pointer register at operand 2 -- `addpt x1,p0/m,z0.d,z0.d'
+.*: Error: expected an SVE vector or predicate register at operand 2 -- `addpt z0.d,x1,z0.d,z0.d'
+.*: Error: expected an SVE vector register at operand 3 -- `addpt z0.d,p0/m,x1,z0.d'
+.*: Error: expected an SVE vector register at operand 4 -- `addpt z0.d,p0/m,z0.d,x1'
+
+.*: Error: operand mismatch -- `subpt z0.b,p0/m,z0.b,z0.b'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+subpt z0.d, p0/m, z0.d, z0.d
+.*: Error: operand 3 must be the same register as operand 1 -- `subpt z0.d,p0/m,z1.d,z0.d'
+.*: Error: operand mismatch -- `subpt z0.d,p0/m,z0.d,z0.s'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+subpt z0.d, p0/m, z0.d, z0.d
+.*: Error: operand mismatch -- `subpt z0.h,p0/m,z0.h,z0.d'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+subpt z0.d, p0/m, z0.d, z0.d
+.*: Error: expected an integer or stack pointer register at operand 2 -- `subpt x1,p0/m,z0.d,z0.d'
+.*: Error: expected an SVE vector or predicate register at operand 2 -- `subpt z0.d,x1,z0.d,z0.d'
+.*: Error: expected an SVE vector register at operand 3 -- `subpt z0.d,p0/m,x1,z0.d'
+.*: Error: expected an SVE vector register at operand 4 -- `subpt z0.d,p0/m,z0.d,x1'
+
+.*: Error: operand mismatch -- `addpt z0.b,z0.b,z0.b'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+addpt z0.d, z0.d, z0.d
+.*: Error: operand mismatch -- `addpt z0.h,z0.h,z0.h'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+addpt z0.d, z0.d, z0.d
+.*: Error: operand mismatch -- `addpt z0.s,z0.s,z0.s'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+addpt z0.d, z0.d, z0.d
+.*: Error: expected an integer or stack pointer register at operand 2 -- `addpt x15,z0.d,z0.d'
+.*: Error: expected an SVE vector or predicate register at operand 2 -- `addpt z0.d,x15,z0.d'
+.*: Error: expected an SVE vector register at operand 3 -- `addpt z0.d,z0.d,x15'
+
+.*: Error: operand mismatch -- `subpt z0.b,z0.b,z0.b'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+subpt z0.d, z0.d, z0.d
+.*: Error: operand mismatch -- `subpt z0.h,z0.h,z0.h'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+subpt z0.d, z0.d, z0.d
+.*: Error: operand mismatch -- `subpt z0.s,z0.s,z0.s'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+subpt z0.d, z0.d, z0.d
+.*: Error: expected an integer or stack pointer register at operand 2 -- `subpt x9,z0.d,z0.d'
+.*: Error: expected an SVE vector or predicate register at operand 2 -- `subpt z0.d,x9,z0.d'
+.*: Error: expected an SVE vector register at operand 3 -- `subpt z0.d,z0.d,x9'
+
+.*: Error: expected an SVE vector register at operand 2 -- `madpt z0.d,p0/m,z0.d,z0.d'
+.*: Error: operand mismatch -- `madpt z10.b,z20.b,z30.b'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+madpt z10.d, z20.d, z30.d
+.*: Error: operand mismatch -- `madpt z20.h,z20.h,z30.h'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+madpt z20.d, z20.d, z30.d
+.*: Error: operand mismatch -- `madpt z20.s,z20.s,z30.s'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+madpt z20.d, z20.d, z30.d
+.*: Error: expected an SVE vector register at operand 1 -- `madpt w9,z0.d,z0.d'
+.*: Error: expected an SVE vector register at operand 2 -- `madpt z0.d,w9,z0.d'
+.*: Error: expected an SVE vector register at operand 3 -- `madpt z0.d,z0.d,w9'
+
+.*: Error: expected an SVE vector register at operand 2 -- `mlapt z0.d,p3/m,z0.d,z0.d'
+.*: Error: operand mismatch -- `mlapt z10.b,z20.b,z30.b'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+mlapt z10.d, z20.d, z30.d
+.*: Error: operand mismatch -- `mlapt z20.h,z20.h,z30.h'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+mlapt z20.d, z20.d, z30.d
+.*: Error: operand mismatch -- `mlapt z20.s,z20.s,z30.s'
+.*: Info:\s+did you mean this\?
+.*: Info:\s+mlapt z20.d, z20.d, z30.d
+.*: Error: expected an SVE vector register at operand 1 -- `mlapt w7,z0.d,z0.d'
+.*: Error: expected an SVE vector register at operand 2 -- `mlapt z0.d,w7,z0.d'
+.*: Error: expected an SVE vector register at operand 3 -- `mlapt z0.d,z0.d,w7'
+
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `addpt z1.d,p0/m,z1.d,z2.d'
+.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `addpt z1.d,p3/m,z1.d,z2.d'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `subpt z1.d,p0/m,z1.d,z2.d'
+.*: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `subpt z1.d,p3/m,z1.d,z2.d'
+.*: Warning: predicated instruction expected after `movprfx' -- `madpt z10.d,z20.d,z30.d'
+.*: Warning: predicated instruction expected after `movprfx' -- `mlapt z10.d,z20.d,z30.d'
diff --git a/gas/testsuite/gas/aarch64/cpa-sve-bad.s b/gas/testsuite/gas/aarch64/cpa-sve-bad.s
new file mode 100644
index 00000000000..e5d33c59d04
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve-bad.s
@@ -0,0 +1,67 @@
+/* General incorrect input tests for CPA+SVE instructions. */
+
+addpt z0.b, p0/m, z0.b, z0.b
+addpt z0.d, p0/m, z1.d, z0.d
+addpt z0.d, p0/m, z0.d, z0.s
+addpt z0.h, p0/m, z0.h, z0.d
+addpt x1, p0/m, z0.d, z0.d
+addpt z0.d, x1, z0.d, z0.d
+addpt z0.d, p0/m, x1, z0.d
+addpt z0.d, p0/m, z0.d, x1
+
+subpt z0.b, p0/m, z0.b, z0.b
+subpt z0.d, p0/m, z1.d, z0.d
+subpt z0.d, p0/m, z0.d, z0.s
+subpt z0.h, p0/m, z0.h, z0.d
+subpt x1, p0/m, z0.d, z0.d
+subpt z0.d, x1, z0.d, z0.d
+subpt z0.d, p0/m, x1, z0.d
+subpt z0.d, p0/m, z0.d, x1
+
+addpt z0.b, z0.b, z0.b
+addpt z0.h, z0.h, z0.h
+addpt z0.s, z0.s, z0.s
+addpt x15, z0.d, z0.d
+addpt z0.d, x15, z0.d
+addpt z0.d, z0.d, x15
+
+subpt z0.b, z0.b, z0.b
+subpt z0.h, z0.h, z0.h
+subpt z0.s, z0.s, z0.s
+subpt x9, z0.d, z0.d
+subpt z0.d, x9, z0.d
+subpt z0.d, z0.d, x9
+
+madpt z0.d, p0/m, z0.d, z0.d
+madpt z10.b, z20.b, z30.b
+madpt z20.h, z20.h, z30.h
+madpt z20.s, z20.s, z30.s
+madpt w9, z0.d, z0.d
+madpt z0.d, w9, z0.d
+madpt z0.d, z0.d, w9
+
+mlapt z0.d, p3/m, z0.d, z0.d
+mlapt z10.b, z20.b, z30.b
+mlapt z20.h, z20.h, z30.h
+mlapt z20.s, z20.s, z30.s
+mlapt w7, z0.d, z0.d
+mlapt z0.d, w7, z0.d
+mlapt z0.d, z0.d, w7
+
+/* MOVPRFX incorrect tests for CPA+SVE instructions. */
+
+movprfx z2, z10
+addpt z1.d, p0/m, z1.d, z2.d
+movprfx z1.d, p4/m, z10.d
+addpt z1.d, p3/m, z1.d, z2.d
+
+movprfx z2, z10
+subpt z1.d, p0/m, z1.d, z2.d
+movprfx z1.d, p4/m, z10.d
+subpt z1.d, p3/m, z1.d, z2.d
+
+movprfx z10.d, p4/m, z11.d
+madpt z10.d, z20.d, z30.d
+
+movprfx z10.d, p4/m, z11.d
+mlapt z10.d, z20.d, z30.d
diff --git a/gas/testsuite/gas/aarch64/cpa-sve-neg.d b/gas/testsuite/gas/aarch64/cpa-sve-neg.d
new file mode 100644
index 00000000000..cf295fe8259
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve-neg.d
@@ -0,0 +1,7 @@
+#name: Negative tests for CPA+SVE instructions.
+#as: -march=armv8-a
+#as: -march=armv8-a+sve
+#as: -march=armv8-a+cpa
+#as: -march=armv9-a
+#source: cpa-sve-neg.s
+#error_output: cpa-sve-neg.l
diff --git a/gas/testsuite/gas/aarch64/cpa-sve-neg.l b/gas/testsuite/gas/aarch64/cpa-sve-neg.l
new file mode 100644
index 00000000000..ed866499169
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve-neg.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support `addpt z0.d,p0/m,z0.d,z0.d'
+.*: Error: selected processor does not support `subpt z0.d,p0/m,z0.d,z0.d'
+.*: Error: selected processor does not support `addpt z0.d,z0.d,z0.d'
+.*: Error: selected processor does not support `subpt z0.d,z0.d,z0.d'
+.*: Error: selected processor does not support `madpt z0.d,z0.d,z0.d'
+.*: Error: selected processor does not support `mlapt z0.d,z0.d,z0.d'
diff --git a/gas/testsuite/gas/aarch64/cpa-sve-neg.s b/gas/testsuite/gas/aarch64/cpa-sve-neg.s
new file mode 100644
index 00000000000..ab7a7b980dd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve-neg.s
@@ -0,0 +1,6 @@
+addpt z0.d, p0/m, z0.d, z0.d
+subpt z0.d, p0/m, z0.d, z0.d
+addpt z0.d, z0.d, z0.d
+subpt z0.d, z0.d, z0.d
+madpt z0.d, z0.d, z0.d
+mlapt z0.d, z0.d, z0.d
diff --git a/gas/testsuite/gas/aarch64/cpa-sve.d b/gas/testsuite/gas/aarch64/cpa-sve.d
new file mode 100644
index 00000000000..e2bf48a35bf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve.d
@@ -0,0 +1,66 @@
+#name: Tests for CPA+SVE instructions.
+#as: -march=armv8-a+sve+cpa
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 04c40000 addpt z0.d, p0/m, z0.d, z0.d
+.*: 04c4001f addpt z31.d, p0/m, z31.d, z0.d
+.*: 04c41c00 addpt z0.d, p7/m, z0.d, z0.d
+.*: 04c403e0 addpt z0.d, p0/m, z0.d, z31.d
+.*: 04c41fff addpt z31.d, p7/m, z31.d, z31.d
+.*: 04c41229 addpt z9.d, p4/m, z9.d, z17.d
+
+.*: 04c50000 subpt z0.d, p0/m, z0.d, z0.d
+.*: 04c5001f subpt z31.d, p0/m, z31.d, z0.d
+.*: 04c51c00 subpt z0.d, p7/m, z0.d, z0.d
+.*: 04c503e0 subpt z0.d, p0/m, z0.d, z31.d
+.*: 04c51fff subpt z31.d, p7/m, z31.d, z31.d
+.*: 04c50c5c subpt z28.d, p3/m, z28.d, z2.d
+
+.*: 04e00800 addpt z0.d, z0.d, z0.d
+.*: 04e0081f addpt z31.d, z0.d, z0.d
+.*: 04e00be0 addpt z0.d, z31.d, z0.d
+.*: 04ff0800 addpt z0.d, z0.d, z31.d
+.*: 04ff0bff addpt z31.d, z31.d, z31.d
+.*: 04e90acd addpt z13.d, z22.d, z9.d
+
+.*: 04e00c00 subpt z0.d, z0.d, z0.d
+.*: 04e00c1f subpt z31.d, z0.d, z0.d
+.*: 04e00fe0 subpt z0.d, z31.d, z0.d
+.*: 04ff0c00 subpt z0.d, z0.d, z31.d
+.*: 04ff0fff subpt z31.d, z31.d, z31.d
+.*: 04f00d3e subpt z30.d, z9.d, z16.d
+
+.*: 44c0d800 madpt z0.d, z0.d, z0.d
+.*: 44c0d81f madpt z31.d, z0.d, z0.d
+.*: 44dfd800 madpt z0.d, z31.d, z0.d
+.*: 44c0dbe0 madpt z0.d, z0.d, z31.d
+.*: 44dfdbff madpt z31.d, z31.d, z31.d
+.*: 44cbdb44 madpt z4.d, z11.d, z26.d
+
+.*: 44c0d000 mlapt z0.d, z0.d, z0.d
+.*: 44c0d01f mlapt z31.d, z0.d, z0.d
+.*: 44c0d3e0 mlapt z0.d, z31.d, z0.d
+.*: 44dfd000 mlapt z0.d, z0.d, z31.d
+.*: 44dfd3ff mlapt z31.d, z31.d, z31.d
+.*: 44c6d26a mlapt z10.d, z19.d, z6.d
+
+.*: 0420bd41 movprfx z1, z10
+.*: 04c40041 addpt z1.d, p0/m, z1.d, z2.d
+.*: 04d13141 movprfx z1.d, p4/m, z10.d
+.*: 04c41041 addpt z1.d, p4/m, z1.d, z2.d
+
+.*: 0420bc01 movprfx z1, z0
+.*: 04c50041 subpt z1.d, p0/m, z1.d, z2.d
+.*: 04d13141 movprfx z1.d, p4/m, z10.d
+.*: 04c51041 subpt z1.d, p4/m, z1.d, z2.d
+
+.*: 0420bc01 movprfx z1, z0
+.*: 44c2d861 madpt z1.d, z2.d, z3.d
+.*: 0420bc01 movprfx z1, z0
+.*: 44c3d041 mlapt z1.d, z2.d, z3.d
diff --git a/gas/testsuite/gas/aarch64/cpa-sve.s b/gas/testsuite/gas/aarch64/cpa-sve.s
new file mode 100644
index 00000000000..6550306ffb6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cpa-sve.s
@@ -0,0 +1,60 @@
+/* General tests for CPA+SVE instructions. */
+
+addpt z0.d, p0/m, z0.d, z0.d
+addpt z31.d, p0/m, z31.d, z0.d
+addpt z0.d, p7/m, z0.d, z0.d
+addpt z0.d, p0/m, z0.d, z31.d
+addpt z31.d, p7/m, z31.d, z31.d
+addpt z9.d, p4/m, z9.d, z17.d
+
+subpt z0.d, p0/m, z0.d, z0.d
+subpt z31.d, p0/m, z31.d, z0.d
+subpt z0.d, p7/m, z0.d, z0.d
+subpt z0.d, p0/m, z0.d, z31.d
+subpt z31.d, p7/m, z31.d, z31.d
+subpt z28.d, p3/m, z28.d, z2.d
+
+addpt z0.d, z0.d, z0.d
+addpt z31.d, z0.d, z0.d
+addpt z0.d, z31.d, z0.d
+addpt z0.d, z0.d, z31.d
+addpt z31.d, z31.d, z31.d
+addpt z13.d, z22.d, z9.d
+
+subpt z0.d, z0.d, z0.d
+subpt z31.d, z0.d, z0.d
+subpt z0.d, z31.d, z0.d
+subpt z0.d, z0.d, z31.d
+subpt z31.d, z31.d, z31.d
+subpt z30.d, z9.d, z16.d
+
+madpt z0.d, z0.d, z0.d
+madpt z31.d, z0.d, z0.d
+madpt z0.d, z31.d, z0.d
+madpt z0.d, z0.d, z31.d
+madpt z31.d, z31.d, z31.d
+madpt z4.d, z11.d, z26.d
+
+mlapt z0.d, z0.d, z0.d
+mlapt z31.d, z0.d, z0.d
+mlapt z0.d, z31.d, z0.d
+mlapt z0.d, z0.d, z31.d
+mlapt z31.d, z31.d, z31.d
+mlapt z10.d, z19.d, z6.d
+
+/* MOVPRFX tests for CPA+SVE instructions. */
+
+movprfx z1, z10
+addpt z1.d, p0/m, z1.d, z2.d
+movprfx z1.d, p4/m, z10.d
+addpt z1.d, p4/m, z1.d, z2.d
+
+movprfx z1, z0
+subpt z1.d, p0/m, z1.d, z2.d
+movprfx z1.d, p4/m, z10.d
+subpt z1.d, p4/m, z1.d, z2.d
+
+movprfx z1, z0
+madpt z1.d, z2.d, z3.d
+movprfx z1, z0
+mlapt z1.d, z2.d, z3.d
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7232d6a9f35..f4626abb3bb 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1885,6 +1885,10 @@
QLF4(S_S,P_M,S_S,S_S), \
QLF4(S_D,P_M,S_D,S_D), \
}
+#define OP_SVE_VMVV_D \
+{ \
+ QLF4(S_D,P_M,S_D,S_D), \
+}
#define OP_SVE_VMVVU_HSD \
{ \
QLF5(S_H,P_M,S_H,S_H,NIL), \
@@ -2657,6 +2661,8 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
AARCH64_FEATURE (RCPC3);
static const aarch64_feature_set aarch64_feature_cpa =
AARCH64_FEATURE (CPA);
+static const aarch64_feature_set aarch64_feature_cpa_sve =
+ AARCH64_FEATURES (2, CPA, SVE);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2724,6 +2730,7 @@ static const aarch64_feature_set aarch64_feature_cpa =
#define SVE2p1 &aarch64_feature_sve2p1
#define RCPC3 &aarch64_feature_rcpc3
#define CPA &aarch64_feature_cpa
+#define CPA_SVE &aarch64_feature_cpa_sve
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2898,6 +2905,9 @@ static const aarch64_feature_set aarch64_feature_cpa =
{ NAME, OPCODE, MASK, CLASS, 0, RCPC3, OPS, QUALS, FLAGS, 0, 0, NULL }
#define CPA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS) \
{ NAME, OPCODE, MASK, CLASS, 0, CPA, OPS, QUALS, 0, 0, 0, NULL }
+#define CPA_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,CONSTRAINTS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, 0, CPA_SVE, OPS, QUALS, \
+ F_STRICT, CONSTRAINTS, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -6408,6 +6418,14 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CPA_INSN ("maddpt", 0x9b600000, 0xffe08000, aarch64_misc, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEX),
CPA_INSN ("msubpt", 0x9b608000, 0xffe08000, aarch64_misc, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEX),
+ CPA_SVE_INSNC ("addpt", 0x04c40000, 0xffffe000, sve_misc, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_D, C_SCAN_MOVPRFX, 2),
+ CPA_SVE_INSNC ("addpt", 0x04e00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, 0),
+ CPA_SVE_INSNC ("subpt", 0x04c50000, 0xffffe000, sve_misc, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_D, C_SCAN_MOVPRFX, 2),
+ CPA_SVE_INSNC ("subpt", 0x04e00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, 0),
+
+ CPA_SVE_INSNC ("madpt", 0x44c0d800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zm_16, SVE_Za_5), OP_SVE_VVV_D, C_SCAN_MOVPRFX, 0),
+ CPA_SVE_INSNC ("mlapt", 0x44c0d000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, C_SCAN_MOVPRFX, 0),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
--
2.39.3
next prev parent reply other threads:[~2024-03-05 13:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-05 13:53 [PATCH 0/2] aarch64: Add support for CPA instructions Yury Khrustalev
2024-03-05 13:54 ` [PATCH 1/2] aarch64: Add support for (M)ADDPT and (M)SUBPT instructions Yury Khrustalev
2024-03-05 13:54 ` Yury Khrustalev [this message]
2024-03-15 9:18 ` [PATCH 0/2] aarch64: Add support for CPA instructions Yury Khrustalev
2024-03-18 18:39 ` Nick Clifton
2024-03-18 18:55 ` Yury Khrustalev
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