[PATCH] AMD bdver2 processors 1/2

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* [PATCH] AMD bdver2 processors 1/2 - BMI
@ 2010-12-20 22:33 Quentin Neill
  2010-12-20 22:56 ` Sebastian Pop
  0 siblings, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2010-12-20 22:33 UTC (permalink / raw)
  To: binutils

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These two patches add support for BMI and TBM ISAs to be introduced in
AMD bdver2 processors.

The full encoding specification is delayed, however I have posted
abbreviated specs on the gcc mailing list:
BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html

Tested on x86-64 with "make -k check RUNTESTFLAGS=i386.exp".

Okay to commit?
-- 
Quentin

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diff --git a/gas/ChangeLog b/gas/ChangeLog
index 08f908d..50216fd 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,10 +1,3 @@
-2010-12-20  Quentin Neill  <quentin.neill@amd.com>
-
-	* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
-	(build_modrm_byte): Add BMI instruction encoding.
-
-	* doc/c-i386.texi (i386-BMI): New section.
-
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* config/tc-mips.c (insn_uses_reg): Handle the new flags
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 4c12e9f..9c33cf9 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -715,8 +715,6 @@ static const arch_entry cpu_arch[] =
     CPU_SSE4A_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
     CPU_ABM_FLAGS, 0, 0 },
-  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
-    CPU_BMI_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF
@@ -5552,8 +5550,7 @@ build_modrm_byte (void)
       else
 	mem = ~0;
 
-      if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
-          || (i.tm.opcode_modifier.vexsources == XOP2REVSOURCES))
+      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
 	{
 	  if (operand_type_check (i.types[0], imm))
 	    i.vex.register_specifier = NULL;
@@ -5561,8 +5558,7 @@ build_modrm_byte (void)
 	    {
 	      /* VEX.vvvv encodes one of the sources when the first
 		 operand is not an immediate.  */
-              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
-                  && (i.tm.opcode_modifier.vexw == VEXW0))
+	      if (i.tm.opcode_modifier.vexw == VEXW0)
 		i.vex.register_specifier = i.op[0].regs;
 	      else
 		i.vex.register_specifier = i.op[1].regs;
@@ -5579,8 +5575,7 @@ build_modrm_byte (void)
 	    {
 	      i.rm.mode = 3;
 
-              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
-                  && (i.tm.opcode_modifier.vexw == VEXW0))
+	      if (i.tm.opcode_modifier.vexw == VEXW0)
 		i.rm.regmem = i.op[1].regs->reg_num;
 	      else
 		i.rm.regmem = i.op[0].regs->reg_num;
@@ -5589,32 +5584,17 @@ build_modrm_byte (void)
 		i.rex |= REX_B;
 	    }
 	}
-      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)
+      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
 	{
-	  unsigned int regspec_op = MAX_OPERANDS;
-	  unsigned int regmem_op = MAX_OPERANDS; 
-	  if (i.tm.opcode_modifier.modrmregext)
-	    {
-	      i.rm.reg = i.tm.extension_opcode;
-	      regspec_op = 1;
-	      regmem_op = 0;
-	    }
-	  else
-	    {
-	      regspec_op = 2;
-	      regmem_op = 1;
-	    }
-
-	  i.vex.register_specifier = i.op[regspec_op].regs;
+	  i.vex.register_specifier = i.op[2].regs;
 	  if (!i.mem_operands)
 	    {
 	      i.rm.mode = 3;
-	      i.rm.regmem = i.op[regmem_op].regs->reg_num;
-	      if ((i.op[regmem_op].regs->reg_flags & RegRex) != 0)
+	      i.rm.regmem = i.op[1].regs->reg_num;
+	      if ((i.op[1].regs->reg_flags & RegRex) != 0)
 		i.rex |= REX_B;
 	    }
 	}
-
       /* Fill in i.rm.reg or i.rm.regmem field with register operand
 	 (if any) based on i.tm.extension_opcode.  Again, we must be
 	 careful to make sure that segment/control/debug/test/MMX
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index fd315b0..1c6175b 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,7 +35,6 @@ extending the Intel architecture to 64-bits.
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-LWP::                    AMD's Lightweight Profiling Instructions
-* i386-BMI::                    Bit Manipulation Instructions
 * i386-16bit::                  Writing 16-bit Code
 * i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
@@ -843,20 +842,6 @@ For detailed information on the LWP instruction set, see the
 @cite{AMD Lightweight Profiling Specification} available at
 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
 
-@node i386-BMI
-@section Bit Manipulation Instructions
-
-@cindex BMI, i386
-@cindex BMI, x86-64
-
-@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
-
-BMI instructions provide several instructions implementing individual
-bit manipulation operations such as isolation, masking, setting, or
-resetting.  
-
-@c Need to add a specification citation here.
-
 @node i386-16bit
 @section Writing 16-bit Code
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 01faa8d..0cf93d6 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,20 +1,3 @@
-2010-12-20  Quentin Neill  <quentin.neill@amd.com>
-
-	* gas/i386/i386.exp: Run bmi and x86-64-bmi.
-	* gas/i386/bmi.d: New.
-	* gas/i386/bmi.s: New.
-	* gas/i386/x86-64-bmi.d: New.
-	* gas/i386/x86-64-bmi.s: New.
-	* gas/i386/arch-10.s: Add a BMI instruction.
-	* gas/i386/x86-64-arch-2.s: Likewise.
-	* gas/i386/arch-10.d: Add bmi flag and BMI instruction pattern.
-	* gas/i386/x86-64-arch-2.d: Likewise.
-	* gas/i386/arch-10-1.l: Add BMI instruction pattern.
-	* gas/i386/arch-10-2.l: Likewise.
-	* gas/i386/arch-10-3.l: Likewise.
-	* gas/i386/arch-10-4.l: Likewise.
-
-
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 95f4425..0b78958 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -29,7 +29,6 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
-.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -97,7 +96,5 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# BMI
-[ 	]*62[ 	]+blsr %ecx,%ebx
-[ 	]*63[ 	]+\# nop
-[ 	]*64[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# nop
+[ 	]*62[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index 3e9d68f..d9e1b51 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -28,7 +28,6 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
-.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -96,7 +95,5 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# BMI
-[ 	]*62[ 	]+blsr %ecx,%ebx
-[ 	]*63[ 	]+\# nop
-[ 	]*64[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# nop
+[ 	]*62[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 7183ea0..75c07ec 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -21,7 +21,6 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
-.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -92,7 +91,5 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# BMI
-[ 	]*62[ 	]+blsr %ecx,%ebx
-[ 	]*63[ 	]+\# nop
-[ 	]*64[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# nop
+[ 	]*62[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 7cd68a3..3c40045 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -19,7 +19,6 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
-.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -90,7 +89,5 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# BMI
-[ 	]*62[ 	]+blsr %ecx,%ebx
-[ 	]*63[ 	]+\# nop
-[ 	]*64[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# nop
+[ 	]*62[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 6e40abd..3efd52d 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
 #objdump: -dw
 #name: i386 arch 10
 
@@ -36,6 +36,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
-[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
 #pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index 7c669eb..d0fb12b 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -58,7 +58,5 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
-# BMI
-blsr %ecx,%ebx
 # nop
 nopl (%eax)
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
deleted file mode 100644
index 1f89b7c..0000000
--- a/gas/testsuite/gas/i386/bmi.d
+++ /dev/null
@@ -1,153 +0,0 @@
-#objdump: -dw
-#name: i386 BMI
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ 	]*[a-f0-9]+:	c4 e2 78 f2 ff       	andn   %edi,%eax,%edi
-[ 	]*[a-f0-9]+:	c4 e2 70 f2 0c fa    	andn   \(%edx,%edi,8\),%ecx,%ecx
-[ 	]*[a-f0-9]+:	c4 e2 58 f2 c3       	andn   %ebx,%esp,%eax
-[ 	]*[a-f0-9]+:	c4 e2 50 f2 14 9b    	andn   \(%ebx,%ebx,4\),%ebp,%edx
-[ 	]*[a-f0-9]+:	c4 e2 40 f2 b1 dc 36 00 00 	andn   0x36dc\(%ecx\),%edi,%esi
-[ 	]*[a-f0-9]+:	c4 e2 48 f2 1b       	andn   \(%ebx\),%esi,%ebx
-[ 	]*[a-f0-9]+:	c4 e2 60 f2 f8       	andn   %eax,%ebx,%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f2 c1       	andn   %ecx,%eax,%eax
-[ 	]*[a-f0-9]+:	c4 e2 68 f2 a4 5e 86 a9 9d ae 	andn   -0x5162567a\(%esi,%ebx,2\),%edx,%esp
-[ 	]*[a-f0-9]+:	c4 e2 68 f2 2e       	andn   \(%esi\),%edx,%ebp
-[ 	]*[a-f0-9]+:	c4 e2 58 f2 c2       	andn   %edx,%esp,%eax
-[ 	]*[a-f0-9]+:	c4 e2 50 f2 d6       	andn   %esi,%ebp,%edx
-[ 	]*[a-f0-9]+:	c4 e2 40 f2 be 53 21 ff ff 	andn   -0xdead\(%esi\),%edi,%edi
-[ 	]*[a-f0-9]+:	c4 e2 58 f2 74 19 0a 	andn   0xa\(%ecx,%ebx,1\),%esp,%esi
-[ 	]*[a-f0-9]+:	c4 e2 40 f2 00       	andn   \(%eax\),%edi,%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f2 7c 13 ce 	andn   -0x32\(%ebx,%edx,1\),%edi,%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f7 3b       	bextr  %eax,\(%ebx\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 40 f7 31       	bextr  %edi,\(%ecx\),%esi
-[ 	]*[a-f0-9]+:	c4 e2 58 f7 cf       	bextr  %esp,%edi,%ecx
-[ 	]*[a-f0-9]+:	c4 e2 50 f7 c1       	bextr  %ebp,%ecx,%eax
-[ 	]*[a-f0-9]+:	c4 e2 60 f7 f8       	bextr  %ebx,%eax,%edi
-[ 	]*[a-f0-9]+:	c4 e2 48 f7 d3       	bextr  %esi,%ebx,%edx
-[ 	]*[a-f0-9]+:	c4 e2 68 f7 04 07    	bextr  %edx,\(%edi,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f7 2f       	bextr  %edi,\(%edi\),%ebp
-[ 	]*[a-f0-9]+:	c4 e2 70 f7 e6       	bextr  %ecx,%esi,%esp
-[ 	]*[a-f0-9]+:	c4 e2 40 f7 18       	bextr  %edi,\(%eax\),%ebx
-[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 05 00 00 00 00 	bextr  %eax,0x0\(,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 50 f7 22       	bextr  %ebp,\(%edx\),%esp
-[ 	]*[a-f0-9]+:	c4 e2 48 f7 2c 85 0f a9 00 00 	bextr  %esi,0xa90f\(,%eax,4\),%ebp
-[ 	]*[a-f0-9]+:	c4 e2 60 f7 7c 03 03 	bextr  %ebx,0x3\(%ebx,%eax,1\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 40 f7 b9 ff ff ff 3f 	bextr  %edi,0x3fffffff\(%ecx\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 12    	bextr  %eax,\(%edx,%edx,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 df       	blsi   %edi,%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 1b       	blsi   \(%ebx\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 de       	blsi   %esi,%esp
-[ 	]*[a-f0-9]+:	c4 e2 68 f3 da       	blsi   %edx,%edx
-[ 	]*[a-f0-9]+:	c4 e2 48 f3 1f       	blsi   \(%edi\),%esi
-[ 	]*[a-f0-9]+:	c4 e2 60 f3 59 08    	blsi   0x8\(%ecx\),%ebx
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 1a       	blsi   \(%edx\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 19       	blsi   \(%ecx\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 dd       	blsi   %ebp,%esp
-[ 	]*[a-f0-9]+:	c4 e2 50 f3 1c 19    	blsi   \(%ecx,%ebx,1\),%ebp
-[ 	]*[a-f0-9]+:	c4 e2 70 f3 1c 4d 03 00 00 00 	blsi   0x3\(,%ecx,2\),%ecx
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 1c 02    	blsi   \(%edx,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 71    	blsi   \(%ecx,%esi,2\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%eax\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 50 f3 d2       	blsmsk %edx,%ebp
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 d7       	blsmsk %edi,%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
-[ 	]*[a-f0-9]+:	c4 e2 68 f3 d5       	blsmsk %ebp,%edx
-[ 	]*[a-f0-9]+:	c4 e2 48 f3 d3       	blsmsk %ebx,%esi
-[ 	]*[a-f0-9]+:	c4 e2 70 f3 17       	blsmsk \(%edi\),%ecx
-[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 14 85 00 00 00 00 	blsmsk 0x0\(,%eax,4\),%esp
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 d4       	blsmsk %esp,%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 13       	blsmsk \(%ebx\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 d3    	blsmsk \(%ebx,%edx,8\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 d6       	blsmsk %esi,%esp
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 94 7f af e6 3d a1 	blsmsk -0x5ec21951\(%edi,%edi,2\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 48    	blsmsk \(%eax,%ecx,2\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 1b    	blsmsk \(%ebx,%ebx,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 14 83    	blsmsk \(%ebx,%eax,4\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 8c 92 fe ca 00 00 	blsr   0xcafe\(%edx,%edx,4\),%esp
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 cf       	blsr   %edi,%eax
-[ 	]*[a-f0-9]+:	c4 e2 48 f3 0c cd 00 00 00 00 	blsr   0x0\(,%ecx,8\),%esi
-[ 	]*[a-f0-9]+:	c4 e2 68 f3 c8       	blsr   %eax,%edx
-[ 	]*[a-f0-9]+:	c4 e2 70 f3 0e       	blsr   \(%esi\),%ecx
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 9d 51 35 b0 66 	blsr   0x66b03551\(,%ebx,4\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 50 f3 0c 85 0a ff ff ff 	blsr   -0xf6\(,%eax,4\),%ebp
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 ce       	blsr   %esi,%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 0b       	blsr   \(%ebx\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 60 f3 8c 7b 3a f2 00 00 	blsr   0xf23a\(%ebx,%edi,2\),%ebx
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 09       	blsr   \(%ecx\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 0c 05 05 00 00 00 	blsr   0x5\(,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 cd       	blsr   %ebp,%eax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 8c 03 c3 41 00 00 	blsr   0x41c3\(%ebx,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 5d 03 00 00 00 	blsr   0x3\(,%ebx,2\),%edi
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 49 5a    	blsr   0x5a\(%ecx\),%edi
-[ 	]*[a-f0-9]+:	66 f3 0f bd 38       	lzcnt  \(%eax\),%di
-[ 	]*[a-f0-9]+:	66 f3 0f bd e7       	lzcnt  %di,%sp
-[ 	]*[a-f0-9]+:	66 f3 0f bd 06       	lzcnt  \(%esi\),%ax
-[ 	]*[a-f0-9]+:	66 f3 0f bd 14 cd 00 00 00 00 	lzcnt  0x0\(,%ecx,8\),%dx
-[ 	]*[a-f0-9]+:	66 f3 0f bd fc       	lzcnt  %sp,%di
-[ 	]*[a-f0-9]+:	66 f3 0f bd 14 35 09 60 ff ff 	lzcnt  -0x9ff7\(,%esi,1\),%dx
-[ 	]*[a-f0-9]+:	66 f3 0f bd bc cb 4d 6e 00 00 	lzcnt  0x6e4d\(%ebx,%ecx,8\),%di
-[ 	]*[a-f0-9]+:	66 f3 0f bd 2a       	lzcnt  \(%edx\),%bp
-[ 	]*[a-f0-9]+:	66 f3 0f bd c9       	lzcnt  %cx,%cx
-[ 	]*[a-f0-9]+:	66 f3 0f bd dd       	lzcnt  %bp,%bx
-[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
-[ 	]*[a-f0-9]+:	66 f3 0f bd 04 05 00 00 00 00 	lzcnt  0x0\(,%eax,1\),%ax
-[ 	]*[a-f0-9]+:	66 f3 0f bd f8       	lzcnt  %ax,%di
-[ 	]*[a-f0-9]+:	66 f3 0f bd db       	lzcnt  %bx,%bx
-[ 	]*[a-f0-9]+:	66 f3 0f bd fa       	lzcnt  %dx,%di
-[ 	]*[a-f0-9]+:	66 f3 0f bd 1f       	lzcnt  \(%edi\),%bx
-[ 	]*[a-f0-9]+:	f3 0f bd db          	lzcnt  %ebx,%ebx
-[ 	]*[a-f0-9]+:	f3 0f bd f9          	lzcnt  %ecx,%edi
-[ 	]*[a-f0-9]+:	f3 0f bd 14 09       	lzcnt  \(%ecx,%ecx,1\),%edx
-[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
-[ 	]*[a-f0-9]+:	f3 0f bd cf          	lzcnt  %edi,%ecx
-[ 	]*[a-f0-9]+:	f3 0f bd fc          	lzcnt  %esp,%edi
-[ 	]*[a-f0-9]+:	f3 0f bd 34 7d 00 00 00 00 	lzcnt  0x0\(,%edi,2\),%esi
-[ 	]*[a-f0-9]+:	f3 0f bd 03          	lzcnt  \(%ebx\),%eax
-[ 	]*[a-f0-9]+:	f3 0f bd 3c 43       	lzcnt  \(%ebx,%eax,2\),%edi
-[ 	]*[a-f0-9]+:	f3 0f bd 1f          	lzcnt  \(%edi\),%ebx
-[ 	]*[a-f0-9]+:	f3 0f bd ed          	lzcnt  %ebp,%ebp
-[ 	]*[a-f0-9]+:	f3 0f bd a3 ad de 00 00 	lzcnt  0xdead\(%ebx\),%esp
-[ 	]*[a-f0-9]+:	f3 0f bd c6          	lzcnt  %esi,%eax
-[ 	]*[a-f0-9]+:	f3 0f bd bc 00 05 63 00 00 	lzcnt  0x6305\(%eax,%eax,1\),%edi
-[ 	]*[a-f0-9]+:	f3 0f bd bc 07 74 8f ff ff 	lzcnt  -0x708c\(%edi,%eax,1\),%edi
-[ 	]*[a-f0-9]+:	f3 0f bd 06          	lzcnt  \(%esi\),%eax
-[ 	]*[a-f0-9]+:	66 f3 0f bc eb       	tzcnt  %bx,%bp
-[ 	]*[a-f0-9]+:	66 f3 0f bc c7       	tzcnt  %di,%ax
-[ 	]*[a-f0-9]+:	66 f3 0f bc fd       	tzcnt  %bp,%di
-[ 	]*[a-f0-9]+:	66 f3 0f bc 14 16    	tzcnt  \(%esi,%edx,1\),%dx
-[ 	]*[a-f0-9]+:	66 f3 0f bc 0f       	tzcnt  \(%edi\),%cx
-[ 	]*[a-f0-9]+:	66 f3 0f bc 0a       	tzcnt  \(%edx\),%cx
-[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
-[ 	]*[a-f0-9]+:	66 f3 0f bc 24 8d 00 00 00 00 	tzcnt  0x0\(,%ecx,4\),%sp
-[ 	]*[a-f0-9]+:	66 f3 0f bc 31       	tzcnt  \(%ecx\),%si
-[ 	]*[a-f0-9]+:	66 f3 0f bc 03       	tzcnt  \(%ebx\),%ax
-[ 	]*[a-f0-9]+:	66 f3 0f bc 3c c7    	tzcnt  \(%edi,%eax,8\),%di
-[ 	]*[a-f0-9]+:	66 f3 0f bc 1c 3b    	tzcnt  \(%ebx,%edi,1\),%bx
-[ 	]*[a-f0-9]+:	66 f3 0f bc c1       	tzcnt  %cx,%ax
-[ 	]*[a-f0-9]+:	66 f3 0f bc b9 63 27 ff ff 	tzcnt  -0xd89d\(%ecx\),%di
-[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
-[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
-[ 	]*[a-f0-9]+:	f3 0f bc f8          	tzcnt  %eax,%edi
-[ 	]*[a-f0-9]+:	f3 0f bc f7          	tzcnt  %edi,%esi
-[ 	]*[a-f0-9]+:	f3 0f bc 44 3b 61    	tzcnt  0x61\(%ebx,%edi,1\),%eax
-[ 	]*[a-f0-9]+:	f3 0f bc de          	tzcnt  %esi,%ebx
-[ 	]*[a-f0-9]+:	f3 0f bc 2a          	tzcnt  \(%edx\),%ebp
-[ 	]*[a-f0-9]+:	f3 0f bc 16          	tzcnt  \(%esi\),%edx
-[ 	]*[a-f0-9]+:	f3 0f bc 0c 0f       	tzcnt  \(%edi,%ecx,1\),%ecx
-[ 	]*[a-f0-9]+:	f3 0f bc f5          	tzcnt  %ebp,%esi
-[ 	]*[a-f0-9]+:	f3 0f bc 07          	tzcnt  \(%edi\),%eax
-[ 	]*[a-f0-9]+:	f3 0f bc 3c 07       	tzcnt  \(%edi,%eax,1\),%edi
-[ 	]*[a-f0-9]+:	f3 0f bc 24 00       	tzcnt  \(%eax,%eax,1\),%esp
-[ 	]*[a-f0-9]+:	f3 0f bc 00          	tzcnt  \(%eax\),%eax
-[ 	]*[a-f0-9]+:	f3 0f bc 3c 45 bf ff ff ff 	tzcnt  -0x41\(,%eax,2\),%edi
-[ 	]*[a-f0-9]+:	f3 0f bc 24 1d 01 00 00 c0 	tzcnt  -0x3fffffff\(,%ebx,1\),%esp
-[ 	]*[a-f0-9]+:	f3 0f bc c3          	tzcnt  %ebx,%eax
-[ 	]*[a-f0-9]+:	f3 0f bc 3b          	tzcnt  \(%ebx\),%edi
-
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
deleted file mode 100644
index f3f9c38..0000000
--- a/gas/testsuite/gas/i386/bmi.s
+++ /dev/null
@@ -1,151 +0,0 @@
-
-	.allow_index_reg
-	.text
-	
-_start:
-
-    ANDN     %edi,%eax,%edi
-    ANDN     (%edx,%edi,8),%ecx,%ecx
-    ANDN     %ebx,%esp,%eax
-    ANDN     (%ebx,%ebx,4),%ebp,%edx
-    ANDN     0x36DC(%ecx),%edi,%esi
-    ANDN     (%ebx),%esi,%ebx
-    ANDN     %eax,%ebx,%edi
-    ANDN     %ecx,%eax,%eax
-    ANDN     -0x5162567A(%esi,%ebx,2),%edx,%esp
-    ANDN     (%esi),%edx,%ebp
-    ANDN     %edx,%esp,%eax
-    ANDN     %esi,%ebp,%edx
-    ANDN     -0xDEAD(%esi),%edi,%edi
-    ANDN     0xA(%ecx,%ebx),%esp,%esi
-    ANDN     (%eax),%edi,%eax
-    ANDN     -0x32(%ebx,%edx),%edi,%edi
-    BEXTR    %eax,(%ebx),%edi
-    BEXTR    %edi,(%ecx),%esi
-    BEXTR    %esp,%edi,%ecx
-    BEXTR    %ebp,%ecx,%eax
-    BEXTR    %ebx,%eax,%edi
-    BEXTR    %esi,%ebx,%edx
-    BEXTR    %edx,(%edi,%eax),%eax
-    BEXTR    %edi,(%edi),%ebp
-    BEXTR    %ecx,%esi,%esp
-    BEXTR    %edi,0x0(%eax),%ebx
-    BEXTR    %eax,(,%eax,1),%eax
-    BEXTR    %ebp,(%edx),%esp
-    BEXTR    %esi,0xA90F(,%eax,4),%ebp
-    BEXTR    %ebx,0x3(%ebx,%eax),%edi
-    BEXTR    %edi,0x3FFFFFFF(%ecx),%edi
-    BEXTR    %eax,(%edx,%edx),%eax
-    BLSI     %edi,%eax
-    BLSI     %eax,%edi
-    BLSI     (%ebx),%edi
-    BLSI     %esi,%esp
-    BLSI     %edx,%edx
-    BLSI     (%edi),%esi
-    BLSI     0x8(%ecx),%ebx
-    BLSI     (%edx),%eax
-    BLSI     (%ecx),%eax
-    BLSI     %ebp,%esp
-    BLSI     (%ecx,%ebx),%ebp
-    BLSI     0x3(,%ecx,2),%ecx
-    BLSI     (%edx,%eax),%eax
-    BLSI     (%ecx,%esi,2),%edi
-    BLSI     %eax,%edi
-    BLSI     (%eax),%eax
-    BLSMSK   %edx,%ebp
-    BLSMSK   %edi,%edi
-    BLSMSK   %eax,%eax
-    BLSMSK   %ebp,%edx
-    BLSMSK   %ebx,%esi
-    BLSMSK   (%edi),%ecx
-    BLSMSK   (%ecx),%ebx
-    BLSMSK   (,%eax,4),%esp
-    BLSMSK   %esp,%eax
-    BLSMSK   (%ebx),%eax
-    BLSMSK   (%ebx,%edx,8),%eax
-    BLSMSK   %esi,%esp
-    BLSMSK   -0x5EC21951(%edi,%edi,2),%edi
-    BLSMSK   (%eax,%ecx,2),%eax
-    BLSMSK   (%ebx,%ebx),%eax
-    BLSMSK   (%ebx,%eax,4),%edi
-    BLSR     0xCAFE(%edx,%edx,4),%esp
-    BLSR     %edi,%eax
-    BLSR     (,%ecx,8),%esi
-    BLSR     %eax,%edx
-    BLSR     (%esi),%ecx
-    BLSR     0x66B03551(,%ebx,4),%edi
-    BLSR     -0xF6(,%eax,4),%ebp
-    BLSR     %esi,%edi
-    BLSR     (%ebx),%eax
-    BLSR     0xF23A(%ebx,%edi,2),%ebx
-    BLSR     (%ecx),%edi
-    BLSR     0x5(,%eax),%eax
-    BLSR     %ebp,%eax
-    BLSR     0x41C3(%ebx,%eax),%eax
-    BLSR     0x3(,%ebx,2),%edi
-    BLSR     0x5A(%ecx),%edi
-    LZCNT    (%eax),%di
-    LZCNT    %di,%sp
-    LZCNT    (%esi),%ax
-    LZCNT    (,%ecx,8),%dx
-    LZCNT    %sp,%di
-    LZCNT    -0x9FF7(,%esi),%dx
-    LZCNT    0x6E4D(%ebx,%ecx,8),%di
-    LZCNT    (%edx),%bp
-    LZCNT    %cx,%cx
-    LZCNT    %bp,%bx
-    LZCNT    %si,%si
-    LZCNT    (,%eax,1),%ax
-    LZCNT    %ax,%di
-    LZCNT    %bx,%bx
-    LZCNT    %dx,%di
-    LZCNT    (%edi),%bx
-    LZCNT    %ebx,%ebx
-    LZCNT    %ecx,%edi
-    LZCNT    (%ecx,%ecx),%edx
-    LZCNT    %eax,%eax
-    LZCNT    %edi,%ecx
-    LZCNT    %esp,%edi
-    LZCNT    (,%edi,2),%esi
-    LZCNT    (%ebx),%eax
-    LZCNT    (%ebx,%eax,2),%edi
-    LZCNT    (%edi),%ebx
-    LZCNT    %ebp,%ebp
-    LZCNT    0xDEAD(%ebx),%esp
-    LZCNT    %esi,%eax
-    LZCNT    0x6305(%eax,%eax,1),%edi
-    LZCNT    -0x708C(%edi,%eax),%edi
-    LZCNT    (%esi),%eax
-    TZCNT    %bx,%bp
-    TZCNT    %di,%ax
-    TZCNT    %bp,%di
-    TZCNT    (%esi,%edx,1),%dx
-    TZCNT    (%edi),%cx
-    TZCNT    (%edx),%cx
-    TZCNT    %ax,%bx
-    TZCNT    (,%ecx,4),%sp
-    TZCNT    (%ecx),%si
-    TZCNT    (%ebx),%ax
-    TZCNT    (%edi,%eax,8),%di
-    TZCNT    (%ebx,%edi),%bx
-    TZCNT    %cx,%ax
-    TZCNT    -0xD89D(%ecx),%di
-    TZCNT    %bp,%ax
-    TZCNT    %bp,%ax
-    TZCNT    %eax,%edi
-    TZCNT    %edi,%esi
-    TZCNT    0x61(%ebx,%edi),%eax
-    TZCNT    %esi,%ebx
-    TZCNT    (%edx),%ebp
-    TZCNT    (%esi),%edx
-    TZCNT    (%edi,%ecx),%ecx
-    TZCNT    %ebp,%esi
-    TZCNT    (%edi),%eax
-    TZCNT    (%edi,%eax,1),%edi
-    TZCNT    (%eax,%eax),%esp
-    TZCNT    (%eax),%eax
-    TZCNT    -0x41(,%eax,2),%edi
-    TZCNT    -0x3FFFFFFF(,%ebx),%esp
-    TZCNT    %ebx,%eax
-    TZCNT    (%ebx),%edi
-
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 01a3ecb..3a966d7 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,7 +173,6 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
-    run_dump_test "bmi"
     run_dump_test "f16c"
     run_dump_test "f16c-intel"
     run_dump_test "fsgs"
@@ -373,7 +372,6 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
-    run_dump_test "x86-64-bmi"
     run_dump_test "x86-64-f16c"
     run_dump_test "x86-64-f16c-intel"
     run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index ac09453..9cd1306 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
 #objdump: -dw
 #name: x86-64 arch 2
 
@@ -36,5 +36,4 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
-[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index 962f15e..ddc0d40 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,5 +58,3 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
-# BMI
-blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
deleted file mode 100644
index 180e40f..0000000
--- a/gas/testsuite/gas/i386/x86-64-bmi.d
+++ /dev/null
@@ -1,265 +0,0 @@
-#objdump: -dw
-#name: x86-64 BMI
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-0+ <_start>:
-[ 	]*[a-f0-9]+:	c4 c2 00 f2 c0       	andn   %r8d,%r15d,%eax
-[ 	]*[a-f0-9]+:	c4 62 78 f2 14 0e    	andn   \(%rsi,%rcx,1\),%eax,%r10d
-[ 	]*[a-f0-9]+:	67 c4 c2 48 f2 2e    	andn   \(%r14d\),%esi,%ebp
-[ 	]*[a-f0-9]+:	c4 42 40 f2 7d 00    	andn   0x0\(%r13\),%edi,%r15d
-[ 	]*[a-f0-9]+:	c4 42 18 f2 fe       	andn   %r14d,%r12d,%r15d
-[ 	]*[a-f0-9]+:	67 c4 82 08 f2 3c 50 	andn   \(%r8d,%r10d,2\),%r14d,%edi
-[ 	]*[a-f0-9]+:	67 c4 42 28 f2 29    	andn   \(%r9d\),%r10d,%r13d
-[ 	]*[a-f0-9]+:	67 c4 22 70 f2 0c bd 00 00 00 00 	andn   0x0\(,%r15d,4\),%ecx,%r9d
-[ 	]*[a-f0-9]+:	c4 a2 38 f2 24 85 00 00 00 00 	andn   0x0\(,%r8,4\),%r8d,%esp
-[ 	]*[a-f0-9]+:	c4 62 38 f2 24 07    	andn   \(%rdi,%rax,1\),%r8d,%r12d
-[ 	]*[a-f0-9]+:	67 c4 c2 20 f2 44 1d 00 	andn   0x0\(%r13d,%ebx,1\),%r11d,%eax
-[ 	]*[a-f0-9]+:	c4 e2 60 f2 f2       	andn   %edx,%ebx,%esi
-[ 	]*[a-f0-9]+:	c4 c2 58 f2 11       	andn   \(%r9\),%esp,%edx
-[ 	]*[a-f0-9]+:	c4 e2 00 f2 0f       	andn   \(%rdi\),%r15d,%ecx
-[ 	]*[a-f0-9]+:	67 c4 62 50 f2 37    	andn   \(%edi\),%ebp,%r14d
-[ 	]*[a-f0-9]+:	c4 a2 28 f2 84 83 fa b5 bb c6 	andn   -0x39444a06\(%rbx,%r8,4\),%r10d,%eax
-[ 	]*[a-f0-9]+:	67 c4 c2 f8 f2 02    	andn   \(%r10d\),%rax,%rax
-[ 	]*[a-f0-9]+:	67 c4 c2 80 f2 16    	andn   \(%r14d\),%r15,%rdx
-[ 	]*[a-f0-9]+:	c4 02 d8 f2 bc 0f 93 5b 00 00 	andn   0x5b93\(%r15,%r9,1\),%rsp,%r15
-[ 	]*[a-f0-9]+:	c4 42 a0 f2 09       	andn   \(%r9\),%r11,%r9
-[ 	]*[a-f0-9]+:	67 c4 e2 80 f2 3c 45 00 00 00 00 	andn   0x0\(,%eax,2\),%r15,%rdi
-[ 	]*[a-f0-9]+:	c4 62 c8 f2 dd       	andn   %rbp,%rsi,%r11
-[ 	]*[a-f0-9]+:	c4 42 e0 f2 45 00    	andn   0x0\(%r13\),%rbx,%r8
-[ 	]*[a-f0-9]+:	c4 62 c0 f2 d0       	andn   %rax,%rdi,%r10
-[ 	]*[a-f0-9]+:	c4 c2 98 f2 e4       	andn   %r12,%r12,%rsp
-[ 	]*[a-f0-9]+:	67 c4 62 a8 f2 3e    	andn   \(%esi\),%r10,%r15
-[ 	]*[a-f0-9]+:	67 c4 62 f8 f2 3a    	andn   \(%edx\),%rax,%r15
-[ 	]*[a-f0-9]+:	67 c4 c2 b8 f2 37    	andn   \(%r15d\),%r8,%rsi
-[ 	]*[a-f0-9]+:	67 c4 42 80 f2 20    	andn   \(%r8d\),%r15,%r12
-[ 	]*[a-f0-9]+:	c4 c2 80 f2 ef       	andn   %r15,%r15,%rbp
-[ 	]*[a-f0-9]+:	c4 a2 d0 f2 0c e5 00 00 00 00 	andn   0x0\(,%r12,8\),%rbp,%rcx
-[ 	]*[a-f0-9]+:	c4 62 f0 f2 2a       	andn   \(%rdx\),%rcx,%r13
-[ 	]*[a-f0-9]+:	c4 e2 00 f7 c0       	bextr  %r15d,%eax,%eax
-[ 	]*[a-f0-9]+:	c4 42 78 f7 fa       	bextr  %eax,%r10d,%r15d
-[ 	]*[a-f0-9]+:	67 c4 82 68 f7 0c cf 	bextr  %edx,\(%r15d,%r9d,8\),%ecx
-[ 	]*[a-f0-9]+:	c4 02 50 f7 54 3d 00 	bextr  %ebp,0x0\(%r13,%r15,1\),%r10d
-[ 	]*[a-f0-9]+:	c4 c2 20 f7 ef       	bextr  %r11d,%r15d,%ebp
-[ 	]*[a-f0-9]+:	c4 82 00 f7 64 35 00 	bextr  %r15d,0x0\(%r13,%r14,1\),%esp
-[ 	]*[a-f0-9]+:	67 c4 02 30 f7 84 c3 ad de 00 00 	bextr  %r9d,0xdead\(%r11d,%r8d,8\),%r8d
-[ 	]*[a-f0-9]+:	67 c4 c2 20 f7 44 04 01 	bextr  %r11d,0x1\(%r12d,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	67 c4 42 28 f7 76 f4 	bextr  %r10d,-0xc\(%r14d\),%r14d
-[ 	]*[a-f0-9]+:	c4 62 78 f7 18       	bextr  %eax,\(%rax\),%r11d
-[ 	]*[a-f0-9]+:	67 c4 c2 60 f7 14 24 	bextr  %ebx,\(%r12d\),%edx
-[ 	]*[a-f0-9]+:	67 c4 62 48 f7 28    	bextr  %esi,\(%eax\),%r13d
-[ 	]*[a-f0-9]+:	c4 e2 78 f7 dd       	bextr  %eax,%ebp,%ebx
-[ 	]*[a-f0-9]+:	c4 c2 78 f7 04 24    	bextr  %eax,\(%r12\),%eax
-[ 	]*[a-f0-9]+:	67 c4 c2 50 f7 04 02 	bextr  %ebp,\(%r10d,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	67 c4 e2 10 f7 44 03 99 	bextr  %r13d,-0x67\(%ebx,%eax,1\),%eax
-[ 	]*[a-f0-9]+:	c4 82 a8 f7 84 7b fe ca 00 00 	bextr  %r10,0xcafe\(%r11,%r15,2\),%rax
-[ 	]*[a-f0-9]+:	c4 42 a8 f7 b1 fe ca 00 00 	bextr  %r10,0xcafe\(%r9\),%r14
-[ 	]*[a-f0-9]+:	c4 62 f8 f7 ff       	bextr  %rax,%rdi,%r15
-[ 	]*[a-f0-9]+:	67 c4 62 f8 f7 2a    	bextr  %rax,\(%edx\),%r13
-[ 	]*[a-f0-9]+:	c4 42 f8 f7 17       	bextr  %rax,\(%r15\),%r10
-[ 	]*[a-f0-9]+:	c4 c2 80 f7 ea       	bextr  %r15,%r10,%rbp
-[ 	]*[a-f0-9]+:	67 c4 e2 f8 f7 3e    	bextr  %rax,\(%esi\),%rdi
-[ 	]*[a-f0-9]+:	c4 42 98 f7 e1       	bextr  %r12,%r9,%r12
-[ 	]*[a-f0-9]+:	c4 c2 b8 f7 dd       	bextr  %r8,%r13,%rbx
-[ 	]*[a-f0-9]+:	c4 c2 f8 f7 24 24    	bextr  %rax,\(%r12\),%rsp
-[ 	]*[a-f0-9]+:	c4 42 f8 f7 5d 00    	bextr  %rax,0x0\(%r13\),%r11
-[ 	]*[a-f0-9]+:	c4 c2 f8 f7 30       	bextr  %rax,\(%r8\),%rsi
-[ 	]*[a-f0-9]+:	c4 e2 f0 f7 d6       	bextr  %rcx,%rsi,%rdx
-[ 	]*[a-f0-9]+:	67 c4 02 b8 f7 7c 0a 03 	bextr  %r8,0x3\(%r10d,%r9d,1\),%r15
-[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 07    	bextr  %rax,\(%r15d\),%rax
-[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 08    	bextr  %rax,\(%r8d\),%rcx
-[ 	]*[a-f0-9]+:	67 c4 a2 48 f3 1c 7d f3 ff ff ff 	blsi   -0xd\(,%r15d,2\),%esi
-[ 	]*[a-f0-9]+:	c4 c2 00 f3 df       	blsi   %r15d,%r15d
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 d8       	blsi   %eax,%eax
-[ 	]*[a-f0-9]+:	c4 c2 28 f3 19       	blsi   \(%r9\),%r10d
-[ 	]*[a-f0-9]+:	c4 e2 30 f3 dd       	blsi   %ebp,%r9d
-[ 	]*[a-f0-9]+:	c4 a2 68 f3 1c 4d 05 00 00 00 	blsi   0x5\(,%r9,2\),%edx
-[ 	]*[a-f0-9]+:	c4 a2 70 f3 1c 5d 96 ff ff ff 	blsi   -0x6a\(,%r11,2\),%ecx
-[ 	]*[a-f0-9]+:	67 c4 e2 50 f3 19    	blsi   \(%ecx\),%ebp
-[ 	]*[a-f0-9]+:	67 c4 e2 20 f3 1f    	blsi   \(%edi\),%r11d
-[ 	]*[a-f0-9]+:	c4 e2 38 f3 5f f9    	blsi   -0x7\(%rdi\),%r8d
-[ 	]*[a-f0-9]+:	67 c4 c2 10 f3 18    	blsi   \(%r8d\),%r13d
-[ 	]*[a-f0-9]+:	c4 c2 60 f3 1a       	blsi   \(%r10\),%ebx
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 05 fe ca 00 00 	blsi   0xcafe\(,%rax,1\),%edi
-[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 1e    	blsi   \(%esi\),%eax
-[ 	]*[a-f0-9]+:	c4 c2 78 f3 d9       	blsi   %r9d,%eax
-[ 	]*[a-f0-9]+:	67 c4 c2 78 f3 5c 3a 99 	blsi   -0x67\(%r10d,%edi,1\),%eax
-[ 	]*[a-f0-9]+:	c4 c2 80 f3 5a 0f    	blsi   0xf\(%r10\),%r15
-[ 	]*[a-f0-9]+:	c4 c2 f8 f3 df       	blsi   %r15,%rax
-[ 	]*[a-f0-9]+:	c4 e2 d8 f3 d8       	blsi   %rax,%rsp
-[ 	]*[a-f0-9]+:	67 c4 e2 a8 f3 18    	blsi   \(%eax\),%r10
-[ 	]*[a-f0-9]+:	67 c4 c2 90 f3 18    	blsi   \(%r8d\),%r13
-[ 	]*[a-f0-9]+:	67 c4 a2 88 f3 9c cf 85 00 00 00 	blsi   0x85\(%edi,%r9d,8\),%r14
-[ 	]*[a-f0-9]+:	c4 c2 98 f3 da       	blsi   %r10,%r12
-[ 	]*[a-f0-9]+:	c4 c2 b8 f3 1b       	blsi   \(%r11\),%r8
-[ 	]*[a-f0-9]+:	c4 c2 b0 f3 9f 20 d6 db b8 	blsi   -0x472429e0\(%r15\),%r9
-[ 	]*[a-f0-9]+:	67 c4 e2 e8 f3 1f    	blsi   \(%edi\),%rdx
-[ 	]*[a-f0-9]+:	67 c4 e2 e0 f3 1c 95 00 00 00 00 	blsi   0x0\(,%edx,4\),%rbx
-[ 	]*[a-f0-9]+:	67 c4 e2 c0 f3 1b    	blsi   \(%ebx\),%rdi
-[ 	]*[a-f0-9]+:	c4 c2 f0 f3 9a ad de 00 00 	blsi   0xdead\(%r10\),%rcx
-[ 	]*[a-f0-9]+:	c4 82 c0 f3 5c f7 1b 	blsi   0x1b\(%r15,%r14,8\),%rdi
-[ 	]*[a-f0-9]+:	c4 e2 a0 f3 1b       	blsi   \(%rbx\),%r11
-[ 	]*[a-f0-9]+:	c4 82 f8 f3 5c 08 0a 	blsi   0xa\(%r8,%r9,1\),%rax
-[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
-[ 	]*[a-f0-9]+:	c4 a2 48 f3 14 8d 00 00 00 00 	blsmsk 0x0\(,%r9,4\),%esi
-[ 	]*[a-f0-9]+:	67 c4 e2 00 f3 14 7d 00 00 00 00 	blsmsk 0x0\(,%edi,2\),%r15d
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 17       	blsmsk \(%rdi\),%esp
-[ 	]*[a-f0-9]+:	67 c4 c2 70 f3 55 00 	blsmsk 0x0\(%r13d\),%ecx
-[ 	]*[a-f0-9]+:	c4 c2 08 f3 d1       	blsmsk %r9d,%r14d
-[ 	]*[a-f0-9]+:	c4 e2 38 f3 12       	blsmsk \(%rdx\),%r8d
-[ 	]*[a-f0-9]+:	67 c4 e2 18 f3 16    	blsmsk \(%esi\),%r12d
-[ 	]*[a-f0-9]+:	c4 c2 20 f3 94 15 c5 22 f8 65 	blsmsk 0x65f822c5\(%r13,%rdx,1\),%r11d
-[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 54 0b fd 	blsmsk -0x3\(%ebx,%ecx,1\),%r10d
-[ 	]*[a-f0-9]+:	c4 c2 50 f3 d7       	blsmsk %r15d,%ebp
-[ 	]*[a-f0-9]+:	c4 e2 10 f3 d6       	blsmsk %esi,%r13d
-[ 	]*[a-f0-9]+:	c4 c2 68 f3 17       	blsmsk \(%r15\),%edx
-[ 	]*[a-f0-9]+:	c4 c2 28 f3 16       	blsmsk \(%r14\),%r10d
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 d5       	blsmsk %ebp,%edi
-[ 	]*[a-f0-9]+:	c4 a2 60 f3 14 21    	blsmsk \(%rcx,%r12,1\),%ebx
-[ 	]*[a-f0-9]+:	c4 c2 e8 f3 d7       	blsmsk %r15,%rdx
-[ 	]*[a-f0-9]+:	c4 e2 f8 f3 14 c8    	blsmsk \(%rax,%rcx,8\),%rax
-[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
-[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 17    	blsmsk \(%r15d\),%r8
-[ 	]*[a-f0-9]+:	c4 e2 80 f3 d0       	blsmsk %rax,%r15
-[ 	]*[a-f0-9]+:	c4 e2 98 f3 56 fd    	blsmsk -0x3\(%rsi\),%r12
-[ 	]*[a-f0-9]+:	c4 e2 c8 f3 14 12    	blsmsk \(%rdx,%rdx,1\),%rsi
-[ 	]*[a-f0-9]+:	c4 c2 e0 f3 16       	blsmsk \(%r14\),%rbx
-[ 	]*[a-f0-9]+:	c4 c2 c0 f3 17       	blsmsk \(%r15\),%rdi
-[ 	]*[a-f0-9]+:	c4 a2 d0 f3 14 25 24 ff ff ff 	blsmsk -0xdc\(,%r12,1\),%rbp
-[ 	]*[a-f0-9]+:	67 c4 e2 a0 f3 13    	blsmsk \(%ebx\),%r11
-[ 	]*[a-f0-9]+:	67 c4 a2 f8 f3 14 35 b8 43 00 00 	blsmsk 0x43b8\(,%r14d,1\),%rax
-[ 	]*[a-f0-9]+:	c4 e2 90 f3 d2       	blsmsk %rdx,%r13
-[ 	]*[a-f0-9]+:	c4 e2 b0 f3 d5       	blsmsk %rbp,%r9
-[ 	]*[a-f0-9]+:	67 c4 e2 d8 f3 10    	blsmsk \(%eax\),%rsp
-[ 	]*[a-f0-9]+:	67 c4 c2 80 f3 16    	blsmsk \(%r14d\),%r15
-[ 	]*[a-f0-9]+:	c4 c2 00 f3 cf       	blsr   %r15d,%r15d
-[ 	]*[a-f0-9]+:	c4 e2 30 f3 c8       	blsr   %eax,%r9d
-[ 	]*[a-f0-9]+:	67 c4 e2 08 f3 0c 15 01 00 00 00 	blsr   0x1\(,%edx,1\),%r14d
-[ 	]*[a-f0-9]+:	c4 e2 70 f3 ca       	blsr   %edx,%ecx
-[ 	]*[a-f0-9]+:	c4 a2 60 f3 0c 71    	blsr   \(%rcx,%r14,2\),%ebx
-[ 	]*[a-f0-9]+:	67 c4 a2 78 f3 0c 8d 4a 46 00 00 	blsr   0x464a\(,%r9d,4\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 58 f3 0e       	blsr   \(%rsi\),%esp
-[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 09    	blsr   \(%ecx\),%esi
-[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 0f    	blsr   \(%edi\),%esi
-[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 0c 7d 00 00 00 00 	blsr   0x0\(,%edi,2\),%r10d
-[ 	]*[a-f0-9]+:	c4 e2 20 f3 0a       	blsr   \(%rdx\),%r11d
-[ 	]*[a-f0-9]+:	c4 c2 10 f3 0b       	blsr   \(%r11\),%r13d
-[ 	]*[a-f0-9]+:	c4 c2 38 f3 c9       	blsr   %r9d,%r8d
-[ 	]*[a-f0-9]+:	c4 e2 68 f3 cf       	blsr   %edi,%edx
-[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 0b    	blsr   \(%ebx\),%eax
-[ 	]*[a-f0-9]+:	c4 e2 40 f3 08       	blsr   \(%rax\),%edi
-[ 	]*[a-f0-9]+:	c4 c2 80 f3 0b       	blsr   \(%r11\),%r15
-[ 	]*[a-f0-9]+:	67 c4 e2 b0 f3 0c 0d 03 00 00 00 	blsr   0x3\(,%ecx,1\),%r9
-[ 	]*[a-f0-9]+:	c4 e2 d8 f3 0e       	blsr   \(%rsi\),%rsp
-[ 	]*[a-f0-9]+:	c4 c2 f8 f3 4d 00    	blsr   0x0\(%r13\),%rax
-[ 	]*[a-f0-9]+:	c4 c2 e8 f3 cf       	blsr   %r15,%rdx
-[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 0e    	blsr   \(%r14d\),%r8
-[ 	]*[a-f0-9]+:	c4 c2 f8 f3 0e       	blsr   \(%r14\),%rax
-[ 	]*[a-f0-9]+:	c4 c2 d0 f3 08       	blsr   \(%r8\),%rbp
-[ 	]*[a-f0-9]+:	c4 e2 a0 f3 ca       	blsr   %rdx,%r11
-[ 	]*[a-f0-9]+:	67 c4 e2 80 f3 0a    	blsr   \(%edx\),%r15
-[ 	]*[a-f0-9]+:	67 c4 a2 e0 f3 0c 25 7e 33 00 00 	blsr   0x337e\(,%r12d,1\),%rbx
-[ 	]*[a-f0-9]+:	c4 e2 f0 f3 08       	blsr   \(%rax\),%rcx
-[ 	]*[a-f0-9]+:	c4 e2 d8 f3 cd       	blsr   %rbp,%rsp
-[ 	]*[a-f0-9]+:	c4 e2 a8 f3 c8       	blsr   %rax,%r10
-[ 	]*[a-f0-9]+:	c4 82 98 f3 4c a5 67 	blsr   0x67\(%r13,%r12,4\),%r12
-[ 	]*[a-f0-9]+:	67 c4 a2 c0 f3 0c 2d 00 00 00 00 	blsr   0x0\(,%r13d,1\),%rdi
-[ 	]*[a-f0-9]+:	67 66 f3 46 0f bd 2c 05 5a 1f 00 00 	lzcnt  0x1f5a\(,%r8d,1\),%r13w
-[ 	]*[a-f0-9]+:	66 f3 44 0f bd e0    	lzcnt  %ax,%r12w
-[ 	]*[a-f0-9]+:	66 f3 45 0f bd 11    	lzcnt  \(%r9\),%r10w
-[ 	]*[a-f0-9]+:	66 f3 41 0f bd c5    	lzcnt  %r13w,%ax
-[ 	]*[a-f0-9]+:	66 f3 44 0f bd 3c c5 99 ff ff ff 	lzcnt  -0x67\(,%rax,8\),%r15w
-[ 	]*[a-f0-9]+:	66 f3 41 0f bd 7c 15 00 	lzcnt  0x0\(%r13,%rdx,1\),%di
-[ 	]*[a-f0-9]+:	66 f3 0f bd 2f       	lzcnt  \(%rdi\),%bp
-[ 	]*[a-f0-9]+:	66 f3 45 0f bd 03    	lzcnt  \(%r11\),%r8w
-[ 	]*[a-f0-9]+:	66 f3 41 0f bd f7    	lzcnt  %r15w,%si
-[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 26 	lzcnt  \(%r14d\),%sp
-[ 	]*[a-f0-9]+:	66 f3 44 0f bd 09    	lzcnt  \(%rcx\),%r9w
-[ 	]*[a-f0-9]+:	66 f3 45 0f bd 8c db e7 9a 00 00 	lzcnt  0x9ae7\(%r11,%rbx,8\),%r9w
-[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
-[ 	]*[a-f0-9]+:	67 66 f3 0f bd 0b    	lzcnt  \(%ebx\),%cx
-[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 1a 	lzcnt  \(%r10d\),%bx
-[ 	]*[a-f0-9]+:	66 f3 45 0f bd f1    	lzcnt  %r9w,%r14w
-[ 	]*[a-f0-9]+:	67 f3 45 0f bd 7d 00 	lzcnt  0x0\(%r13d\),%r15d
-[ 	]*[a-f0-9]+:	f3 0f bd e7          	lzcnt  %edi,%esp
-[ 	]*[a-f0-9]+:	67 f3 45 0f bd 2e    	lzcnt  \(%r14d\),%r13d
-[ 	]*[a-f0-9]+:	f3 41 0f bd 16       	lzcnt  \(%r14\),%edx
-[ 	]*[a-f0-9]+:	f3 45 0f bd df       	lzcnt  %r15d,%r11d
-[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
-[ 	]*[a-f0-9]+:	f3 41 0f bd 30       	lzcnt  \(%r8\),%esi
-[ 	]*[a-f0-9]+:	f3 45 0f bd f9       	lzcnt  %r9d,%r15d
-[ 	]*[a-f0-9]+:	f3 45 0f bd 04 24    	lzcnt  \(%r12\),%r8d
-[ 	]*[a-f0-9]+:	f3 41 0f bd e8       	lzcnt  %r8d,%ebp
-[ 	]*[a-f0-9]+:	67 f3 41 0f bd 1a    	lzcnt  \(%r10d\),%ebx
-[ 	]*[a-f0-9]+:	f3 41 0f bd 3c 0c    	lzcnt  \(%r12,%rcx,1\),%edi
-[ 	]*[a-f0-9]+:	f3 44 0f bd 3f       	lzcnt  \(%rdi\),%r15d
-[ 	]*[a-f0-9]+:	67 f3 44 0f bd 3f    	lzcnt  \(%edi\),%r15d
-[ 	]*[a-f0-9]+:	f3 45 0f bd d4       	lzcnt  %r12d,%r10d
-[ 	]*[a-f0-9]+:	f3 42 0f bd 04 2d 00 00 00 00 	lzcnt  0x0\(,%r13,1\),%eax
-[ 	]*[a-f0-9]+:	67 f3 49 0f bd 6d 00 	lzcnt  0x0\(%r13d\),%rbp
-[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 02    	lzcnt  \(%r10d\),%r8
-[ 	]*[a-f0-9]+:	67 f3 48 0f bd 06    	lzcnt  \(%esi\),%rax
-[ 	]*[a-f0-9]+:	f3 4c 0f bd eb       	lzcnt  %rbx,%r13
-[ 	]*[a-f0-9]+:	f3 4d 0f bd 39       	lzcnt  \(%r9\),%r15
-[ 	]*[a-f0-9]+:	f3 48 0f bd ca       	lzcnt  %rdx,%rcx
-[ 	]*[a-f0-9]+:	f3 4a 0f bd 04 6d 00 00 00 00 	lzcnt  0x0\(,%r13,2\),%rax
-[ 	]*[a-f0-9]+:	67 f3 48 0f bd 30    	lzcnt  \(%eax\),%rsi
-[ 	]*[a-f0-9]+:	67 f3 49 0f bd 27    	lzcnt  \(%r15d\),%rsp
-[ 	]*[a-f0-9]+:	67 f3 4e 0f bd 1c bd 00 00 00 00 	lzcnt  0x0\(,%r15d,4\),%r11
-[ 	]*[a-f0-9]+:	f3 4d 0f bd e7       	lzcnt  %r15,%r12
-[ 	]*[a-f0-9]+:	f3 48 0f bd 17       	lzcnt  \(%rdi\),%rdx
-[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 0c 24 	lzcnt  \(%r12d\),%r9
-[ 	]*[a-f0-9]+:	f3 4d 0f bd d3       	lzcnt  %r11,%r10
-[ 	]*[a-f0-9]+:	67 f3 4c 0f bd 2c dd fe ca 00 00 	lzcnt  0xcafe\(,%ebx,8\),%r13
-[ 	]*[a-f0-9]+:	f3 48 0f bd c0       	lzcnt  %rax,%rax
-[ 	]*[a-f0-9]+:	66 f3 45 0f bc f2    	tzcnt  %r10w,%r14w
-[ 	]*[a-f0-9]+:	66 f3 41 0f bc 86 7a 73 00 00 	tzcnt  0x737a\(%r14\),%ax
-[ 	]*[a-f0-9]+:	66 f3 44 0f bc d0    	tzcnt  %ax,%r10w
-[ 	]*[a-f0-9]+:	66 f3 41 0f bc f7    	tzcnt  %r15w,%si
-[ 	]*[a-f0-9]+:	66 f3 45 0f bc 3c 24 	tzcnt  \(%r12\),%r15w
-[ 	]*[a-f0-9]+:	67 66 f3 0f bc 22    	tzcnt  \(%edx\),%sp
-[ 	]*[a-f0-9]+:	66 f3 44 0f bc 28    	tzcnt  \(%rax\),%r13w
-[ 	]*[a-f0-9]+:	66 f3 41 0f bc ec    	tzcnt  %r12w,%bp
-[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 81 ad 3c 00 00 	tzcnt  0x3cad\(%r9d\),%ax
-[ 	]*[a-f0-9]+:	66 f3 41 0f bc 44 12 06 	tzcnt  0x6\(%r10,%rdx,1\),%ax
-[ 	]*[a-f0-9]+:	66 f3 45 0f bc dd    	tzcnt  %r13w,%r11w
-[ 	]*[a-f0-9]+:	67 66 f3 43 0f bc 0c 32 	tzcnt  \(%r10d,%r14d,1\),%cx
-[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc a4 9a 44 ae d0 4c 	tzcnt  0x4cd0ae44\(%r10d,%ebx,4\),%r12w
-[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc 3f 	tzcnt  \(%r15d\),%r15w
-[ 	]*[a-f0-9]+:	66 f3 45 0f bc 08    	tzcnt  \(%r8\),%r9w
-[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 01 	tzcnt  \(%r9d\),%ax
-[ 	]*[a-f0-9]+:	f3 41 0f bc 10       	tzcnt  \(%r8\),%edx
-[ 	]*[a-f0-9]+:	67 f3 44 0f bc 1e    	tzcnt  \(%esi\),%r11d
-[ 	]*[a-f0-9]+:	f3 41 0f bc 02       	tzcnt  \(%r10\),%eax
-[ 	]*[a-f0-9]+:	f3 45 0f bc 7c 16 c3 	tzcnt  -0x3d\(%r14,%rdx,1\),%r15d
-[ 	]*[a-f0-9]+:	f3 41 0f bc 75 00    	tzcnt  0x0\(%r13\),%esi
-[ 	]*[a-f0-9]+:	f3 44 0f bc 27       	tzcnt  \(%rdi\),%r12d
-[ 	]*[a-f0-9]+:	67 f3 0f bc 01       	tzcnt  \(%ecx\),%eax
-[ 	]*[a-f0-9]+:	f3 47 0f bc ac e9 bc 9a ff ff 	tzcnt  -0x6544\(%r9,%r13,8\),%r13d
-[ 	]*[a-f0-9]+:	f3 0f bc e0          	tzcnt  %eax,%esp
-[ 	]*[a-f0-9]+:	f3 45 0f bc c7       	tzcnt  %r15d,%r8d
-[ 	]*[a-f0-9]+:	67 f3 0f bc 3c 0d f1 ff ff ff 	tzcnt  -0xf\(,%ecx,1\),%edi
-[ 	]*[a-f0-9]+:	f3 45 0f bc 09       	tzcnt  \(%r9\),%r9d
-[ 	]*[a-f0-9]+:	f3 0f bc 21          	tzcnt  \(%rcx\),%esp
-[ 	]*[a-f0-9]+:	f3 43 0f bc 2c 10    	tzcnt  \(%r8,%r10,1\),%ebp
-[ 	]*[a-f0-9]+:	f3 46 0f bc 34 17    	tzcnt  \(%rdi,%r10,1\),%r14d
-[ 	]*[a-f0-9]+:	67 f3 0f bc 30       	tzcnt  \(%eax\),%esi
-[ 	]*[a-f0-9]+:	67 f3 4c 0f bc 0f    	tzcnt  \(%edi\),%r9
-[ 	]*[a-f0-9]+:	f3 49 0f bc 29       	tzcnt  \(%r9\),%rbp
-[ 	]*[a-f0-9]+:	67 f3 4d 0f bc 3c 9f 	tzcnt  \(%r15d,%ebx,4\),%r15
-[ 	]*[a-f0-9]+:	f3 4d 0f bc 26       	tzcnt  \(%r14\),%r12
-[ 	]*[a-f0-9]+:	f3 4e 0f bc 14 05 0e 8a f2 62 	tzcnt  0x62f28a0e\(,%r8,1\),%r10
-[ 	]*[a-f0-9]+:	f3 4d 0f bc 34 30    	tzcnt  \(%r8,%rsi,1\),%r14
-[ 	]*[a-f0-9]+:	67 f3 48 0f bc 06    	tzcnt  \(%esi\),%rax
-[ 	]*[a-f0-9]+:	f3 49 0f bc c5       	tzcnt  %r13,%rax
-[ 	]*[a-f0-9]+:	f3 4d 0f bc 81 6c 3d 00 00 	tzcnt  0x3d6c\(%r9\),%r8
-[ 	]*[a-f0-9]+:	f3 4c 0f bc f8       	tzcnt  %rax,%r15
-[ 	]*[a-f0-9]+:	f3 4a 0f bc 24 4d 00 00 00 00 	tzcnt  0x0\(,%r9,2\),%rsp
-[ 	]*[a-f0-9]+:	67 f3 4a 0f bc 1c e5 00 00 00 00 	tzcnt  0x0\(,%r12d,8\),%rbx
-[ 	]*[a-f0-9]+:	f3 4c 0f bc 1c 16    	tzcnt  \(%rsi,%rdx,1\),%r11
-[ 	]*[a-f0-9]+:	f3 4a 0f bc 3c a9    	tzcnt  \(%rcx,%r13,4\),%rdi
-[ 	]*[a-f0-9]+:	f3 49 0f bc 44 c3 f1 	tzcnt  -0xf\(%r11,%rax,8\),%rax
-[ 	]*[a-f0-9]+:	f3 49 0f bc 00       	tzcnt  \(%r8\),%rax
-
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
deleted file mode 100644
index e4059ec..0000000
--- a/gas/testsuite/gas/i386/x86-64-bmi.s
+++ /dev/null
@@ -1,263 +0,0 @@
-
-	.allow_index_reg
-	.text
-	
-_start:
-
-    ANDN     %eax,%r15d,%eax
-    ANDN     (%rsi,%rcx),%eax,%r10d
-    ANDN     (%r14d),%esi,%ebp
-    ANDN     (%r13),%edi,%r15d
-    ANDN     %esi,%r12d,%r15d
-    ANDN     (%r8d,%r10d,2),%r14d,%edi
-    ANDN     (%r9d),%r10d,%r13d
-    ANDN     (,%r15d,4),%ecx,%r9d
-    ANDN     (,%r8,4),%r8d,%esp
-    ANDN     (%rdi,%rax),%r8d,%r12d
-    ANDN     (%r13d,%ebx),%r11d,%eax
-    ANDN     %edx,%ebx,%esi
-    ANDN     (%r9),%esp,%edx
-    ANDN     (%rdi),%r15d,%ecx
-    ANDN     (%edi),%ebp,%r14d
-    ANDN     -0x39444A06(%rbx,%r8,4),%r10d,%eax
-    ANDN     (%r10d),%rax,%rax
-    ANDN     (%r14d),%r15,%rdx
-    ANDN     0x5B93(%r15,%r9),%rsp,%r15
-    ANDN     (%r9),%r11,%r9
-    ANDN     (,%eax,2),%r15,%rdi
-    ANDN     %rbp,%rsi,%r11
-    ANDN     (%r13),%rbx,%r8
-    ANDN     %rax,%rdi,%r10
-    ANDN     %rsp,%r12,%rsp
-    ANDN     (%esi),%r10,%r15
-    ANDN     (%edx),%rax,%r15
-    ANDN     (%r15d),%r8,%rsi
-    ANDN     (%r8d),%r15,%r12
-    ANDN     %rdi,%r15,%rbp
-    ANDN     (,%r12,8),%rbp,%rcx
-    ANDN     (%rdx),%rcx,%r13
-    BEXTR    %r15d,%eax,%eax
-    BEXTR    %eax,%r10d,%r15d
-    BEXTR    %edx,(%r15d,%r9d,8),%ecx
-    BEXTR    %ebp,(%r13,%r15),%r10d
-    BEXTR    %r11d,%r15d,%ebp
-    BEXTR    %r15d,(%r13,%r14),%esp
-    BEXTR    %r9d,0xDEAD(%r11d,%r8d,8),%r8d
-    BEXTR    %r11d,0x1(%r12d,%eax),%eax
-    BEXTR    %r10d,-0xC(%r14d),%r14d
-    BEXTR    %eax,(%rax),%r11d
-    BEXTR    %ebx,(%r12d),%edx
-    BEXTR    %esi,(%eax),%r13d
-    BEXTR    %eax,%ebp,%ebx
-    BEXTR    %eax,(%r12),%eax
-    BEXTR    %ebp,(%r10d,%eax),%eax
-    BEXTR    %r13d,-0x67(%ebx,%eax),%eax
-    BEXTR    %r15,0xCAFE(%r11,%r15,2),%rax
-    BEXTR    %r14,0xCAFE(%r9),%r14
-    BEXTR    %rdi,%rax,%r15
-    BEXTR    %rax,(%edx),%r13
-    BEXTR    %rdx,(%r15),%r10
-    BEXTR    %r10,%r15,%rbp
-    BEXTR    %r12,(%esi),%rdi
-    BEXTR    %rcx,%r12,%r12
-    BEXTR    %rbp,%r8,%rbx
-    BEXTR    %rbx,(%r12),%rsp
-    BEXTR    %r9,(%r13),%r11
-    BEXTR    %r11,(%r8),%rsi
-    BEXTR    %rsi,%rcx,%rdx
-    BEXTR    %r13,0x3(%r10d,%r9d,1),%r15
-    BEXTR    %rax,(%r15d),%rax
-    BEXTR    %r15,(%r8d),%rcx
-    BLSI     -0xD(,%r15d,2),%esi
-    BLSI     %r15d,%r15d
-    BLSI     %eax,%eax
-    BLSI     (%r9),%r10d
-    BLSI     %ebp,%r9d
-    BLSI     0x5(,%r9,2),%edx
-    BLSI     -0x6A(,%r11,2),%ecx
-    BLSI     (%ecx),%ebp
-    BLSI     (%edi),%r11d
-    BLSI     -0x7(%rdi),%r8d
-    BLSI     (%r8d),%r13d
-    BLSI     (%r10),%ebx
-    BLSI     0xCAFE(,%rax),%edi
-    BLSI     (%esi),%eax
-    BLSI     %r9d,%eax
-    BLSI     -0x67(%r10d,%edi,1),%eax
-    BLSI     0xF(%r10),%r15
-    BLSI     %r15,%rax
-    BLSI     %rax,%rsp
-    BLSI     (%eax),%r10
-    BLSI     (%r8d),%r13
-    BLSI     0x85(%edi,%r9d,8),%r14
-    BLSI     %r10,%r12
-    BLSI     (%r11),%r8
-    BLSI     -0x472429E0(%r15),%r9
-    BLSI     (%edi),%rdx
-    BLSI     (,%edx,4),%rbx
-    BLSI     (%ebx),%rdi
-    BLSI     0xDEAD(%r10),%rcx
-    BLSI     0x1B(%r15,%r14,8),%rdi
-    BLSI     (%rbx),%r11
-    BLSI     0xA(%r8,%r9),%rax
-    BLSMSK   %eax,%eax
-    BLSMSK   (,%r9,4),%esi
-    BLSMSK   (,%edi,2),%r15d
-    BLSMSK   (%rdi),%esp
-    BLSMSK   (%r13d),%ecx
-    BLSMSK   %r9d,%r14d
-    BLSMSK   (%rdx),%r8d
-    BLSMSK   (%esi),%r12d
-    BLSMSK   0x65F822C5(%r13,%rdx),%r11d
-    BLSMSK   -0x3(%ebx,%ecx,1),%r10d
-    BLSMSK   %r15d,%ebp
-    BLSMSK   %esi,%r13d
-    BLSMSK   (%r15),%edx
-    BLSMSK   (%r14),%r10d
-    BLSMSK   %ebp,%edi
-    BLSMSK   (%rcx,%r12),%ebx
-    BLSMSK   %r15,%rdx
-    BLSMSK   (%rax,%rcx,8),%rax
-    BLSMSK   %r9,%r15
-    BLSMSK   (%r15d),%r8
-    BLSMSK   %rax,%r15
-    BLSMSK   -0x3(%rsi),%r12
-    BLSMSK   -0x0(%rdx,%rdx),%rsi
-    BLSMSK   (%r14),%rbx
-    BLSMSK   (%r15),%rdi
-    BLSMSK   -0xDC(,%r12),%rbp
-    BLSMSK   (%ebx),%r11
-    BLSMSK   0x43B8(,%r14d),%rax
-    BLSMSK   %rdx,%r13
-    BLSMSK   %rbp,%r9
-    BLSMSK   (%eax),%rsp
-    BLSMSK   (%r14d),%r15
-    BLSR     %r15d,%r15d
-    BLSR     %eax,%r9d
-    BLSR     0x1(,%edx),%r14d
-    BLSR     %edx,%ecx
-    BLSR     (%rcx,%r14,2),%ebx
-    BLSR     0x464A(,%r9d,4),%eax
-    BLSR     (%rsi),%esp
-    BLSR     (%ecx),%esi
-    BLSR     (%edi),%esi
-    BLSR     (,%edi,2),%r10d
-    BLSR     (%rdx),%r11d
-    BLSR     (%r11),%r13d
-    BLSR     %r9d,%r8d
-    BLSR     %edi,%edx
-    BLSR     (%ebx),%eax
-    BLSR     (%rax),%edi
-    BLSR     (%r11),%r15
-    BLSR     0x3(,%ecx),%r9
-    BLSR     (%rsi),%rsp
-    BLSR     (%r13),%rax
-    BLSR     %r15,%rdx
-    BLSR     (%r14d),%r8
-    BLSR     (%r14),%rax
-    BLSR     (%r8),%rbp
-    BLSR     %rdx,%r11
-    BLSR     (%edx),%r15
-    BLSR     0x337E(,%r12d),%rbx
-    BLSR     (%rax),%rcx
-    BLSR     %rbp,%rsp
-    BLSR     %rax,%r10
-    BLSR     0x67(%r13,%r12,4),%r12
-    BLSR     (,%r13d,1),%rdi
-    LZCNT    0x1F5A(,%r8d),%r13w
-    LZCNT    %ax,%r12w
-    LZCNT    (%r9),%r10w
-    LZCNT    %r13w,%ax
-    LZCNT    -0x67(,%rax,8),%r15w
-    LZCNT    (%r13,%rdx),%di
-    LZCNT    (%rdi),%bp
-    LZCNT    (%r11),%r8w
-    LZCNT    %r15w,%si
-    LZCNT    (%r14d),%sp
-    LZCNT    (%rcx),%r9w
-    LZCNT    0x9AE7(%r11,%rbx,8),%r9w
-    LZCNT    %si,%si
-    LZCNT    (%ebx),%cx
-    LZCNT    (%r10d),%bx
-    LZCNT    %r9w,%r14w
-    LZCNT    (%r13d),%r15d
-    LZCNT    %edi,%esp
-    LZCNT    (%r14d),%r13d
-    LZCNT    (%r14),%edx
-    LZCNT    %r15d,%r11d
-    LZCNT    %eax,%eax
-    LZCNT    (%r8),%esi
-    LZCNT    %r9d,%r15d
-    LZCNT    (%r12),%r8d
-    LZCNT    %r8d,%ebp
-    LZCNT    (%r10d),%ebx
-    LZCNT    (%r12,%rcx),%edi
-    LZCNT    (%rdi),%r15d
-    LZCNT    (%edi),%r15d
-    LZCNT    %r12d,%r10d
-    LZCNT    (,%r13,1),%eax
-    LZCNT    (%r13d),%rbp
-    LZCNT    (%r10d),%r8
-    LZCNT    (%esi),%rax
-    LZCNT    %rbx,%r13
-    LZCNT    (%r9),%r15
-    LZCNT    %rdx,%rcx
-    LZCNT    (,%r13,2),%rax
-    LZCNT    (%eax),%rsi
-    LZCNT    (%r15d),%rsp
-    LZCNT    (,%r15d,4),%r11
-    LZCNT    %r15,%r12
-    LZCNT    (%rdi),%rdx
-    LZCNT    (%r12d),%r9
-    LZCNT    %r11,%r10
-    LZCNT    0xCAFE(,%ebx,8),%r13
-    LZCNT    %rax,%rax
-    TZCNT    %r10w,%r14w
-    TZCNT    0x737A(%r14),%ax
-    TZCNT    %ax,%r10w
-    TZCNT    %r15w,%si
-    TZCNT    (%r12),%r15w
-    TZCNT    (%edx),%sp
-    TZCNT    (%rax),%r13w
-    TZCNT    %r12w,%bp
-    TZCNT    0x3CAD(%r9d),%ax
-    TZCNT    0x6(%r10,%rdx),%ax
-    TZCNT    %r13w,%r11w
-    TZCNT    (%r10d,%r14d),%cx
-    TZCNT    0x4CD0AE44(%r10d,%ebx,4),%r12w
-    TZCNT    (%r15d),%r15w
-    TZCNT    (%r8),%r9w
-    TZCNT    (%r9d),%ax
-    TZCNT    (%r8),%edx
-    TZCNT    (%esi),%r11d
-    TZCNT    (%r10),%eax
-    TZCNT    -0x3D(%r14,%rdx),%r15d
-    TZCNT    (%r13),%esi
-    TZCNT    (%rdi),%r12d
-    TZCNT    (%ecx),%eax
-    TZCNT    -0x6544(%r9,%r13,8),%r13d
-    TZCNT    %eax,%esp
-    TZCNT    %r15d,%r8d
-    TZCNT    -0xF(,%ecx),%edi
-    TZCNT    (%r9),%r9d
-    TZCNT    (%rcx),%esp
-    TZCNT    (%r8,%r10),%ebp
-    TZCNT    (%rdi,%r10),%r14d
-    TZCNT    (%eax),%esi
-    TZCNT    (%edi),%r9
-    TZCNT    (%r9),%rbp
-    TZCNT    (%r15d,%ebx,4),%r15
-    TZCNT    (%r14),%r12
-    TZCNT    0x62F28A0E(,%r8),%r10
-    TZCNT    (%r8,%rsi),%r14
-    TZCNT    (%esi),%rax
-    TZCNT    %r13,%rax
-    TZCNT    0x3D6C(%r9),%r8
-    TZCNT    %rax,%r15
-    TZCNT    (,%r9,2),%rsp
-    TZCNT    (,%r12d,8),%rbx
-    TZCNT    (%rsi,%rdx),%r11
-    TZCNT    (%rcx,%r13,4),%rdi
-    TZCNT    -0xF(%r11,%rax,8),%rax
-    TZCNT    (%r8),%rax
-
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8f1b4bd..b18b6b9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,42 +1,3 @@
-2010-12-20  Quentin Neill  <quentin.neill@amd.com>
-
-	* i386-dis.c (REG_XOP_BMI_F3): New.
-	(PREFIX_BMI_F30F): New.
-	(dis386_twobyte): Redirect to PREFIX_BMI_F30F entry.
-	(reg_table): Add REG_XOP_BMI_F3 table.
-	(prefix_table): Add PREFIX_BMI_F30F table.
-	(x86_64_table): Add andn, bextr, and redirect to
-	REG_XOP_BMI_F3 entry.
-
-	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS, CpuBMI.
-	(cpu_flags): Add CpuBMI.
-	(opcode_modifiers): Define bitfield ModrmRegExt.
-
-	* i386-opc.h (CpuBMI) New.
-	(i386_cpu_flags): Add bit cpubmi.
-	(enum): New ModrmRegExt enum, rename VexVVVV
-	encoding from VEX.LWP to VEX.VRM, add VexOpcode
-	encoding XOP02, and add VexSources enoding
-	XOP2REVSOURCES.
-	(i386_opcode_modifier): Add modrmregext bit, increase
-	vexvvvv bit width to 3.
-
-	* i386-opc.tbl (andn): Added.
-	(andn): Added.
-	(bextr): Added.
-	(bextr): Added.
-	(blsi): Added.
-	(blsi): Added.
-	(blsmsk): Added.
-	(blsmsk): Added.
-	(blsr): Added.
-	(blsr): Added.
-	(tzcnt): Added.
-
-	* i386-init.h: Regenerated.
-
-	* i386-tbl.h: Regenerated
-
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 30ea470..f2def13 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -599,8 +599,7 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_XOP_LWPCB,
-  REG_XOP_LWP,
-  REG_XOP_BMI_F3
+  REG_XOP_LWP
 };
 
 enum
@@ -1069,8 +1068,7 @@ enum
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,
-  PREFIX_VEX_0F3ADF,
-  PREFIX_BMI_F30F
+  PREFIX_VEX_0F3ADF
 };
 
 enum
@@ -2160,7 +2158,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "ud1",		{ XX } },
   { REG_TABLE (REG_0FBA) },
   { "btcS",		{ Ev, Gv } },
-  { PREFIX_TABLE (PREFIX_BMI_F30F) },
+  { "bsfS",		{ Gv, Ev } },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",	{ Gv, Eb } },
   { "movs{wR|x}",	{ Gv, Ew } }, /* yes, there really is movsww ! */
@@ -2761,13 +2759,6 @@ static const struct dis386 reg_table[][8] = {
     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
     { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq } },
   },
-  /* REG_XOP_BMI_F3 */
-  {
-    { Bad_Opcode },
-    { "blsr",	{ { OP_LWP_E, 0 }, Ev } },
-    { "blsmsk",	{ { OP_LWP_E, 0 }, Ev } },
-    { "blsi",	{ { OP_LWP_E, 0 }, Ev } },
-  },
 };
 
 static const struct dis386 prefix_table[][4] = {
@@ -5363,14 +5354,6 @@ static const struct dis386 prefix_table[][4] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },
-
-  /* PREFIX_BMI_F30F */
-  {
-    { "bsfS",		{ Gv, Ev } },
-    { "tzcntS",		{ Gv, Ev } },
-    { "bsfS",		{ Gv, Ev } },
-    { "tzcntS",		{ Gv, Ev } },
-  },
 };
 
 static const struct dis386 x86_64_table[][2] = {
@@ -7845,12 +7828,12 @@ static const struct dis386 vex_table[][256] = {
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
-    { "andn",	{ Gv, { OP_LWP_E, 0 }, Ev } },
-    { REG_TABLE (REG_XOP_BMI_F3) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "bextr",	{ Gv, Ev, { OP_LWP_E, 0 } } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index c4ed21f..ee06338 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,8 +140,6 @@ static initializer cpu_flag_init[] =
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
   { "CPU_LWP_FLAGS",
     "CpuLWP" },
-  { "CPU_BMI_FLAGS",
-    "CpuBMI" },
   { "CPU_MOVBE_FLAGS",
     "CpuMovbe" },
   { "CPU_RDTSCP_FLAGS",
@@ -322,7 +320,6 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuFMA4),
   BITFIELD (CpuXOP),
   BITFIELD (CpuLWP),
-  BITFIELD (CpuBMI),
   BITFIELD (CpuLM),
   BITFIELD (CpuMovbe),
   BITFIELD (CpuEPT),
@@ -343,7 +340,6 @@ static bitfield opcode_modifiers[] =
   BITFIELD (W),
   BITFIELD (S),
   BITFIELD (Modrm),
-  BITFIELD (ModrmRegExt),
   BITFIELD (ShortForm),
   BITFIELD (Jump),
   BITFIELD (JumpDword),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index d5697de..fe546b6 100644
Binary files a/opcodes/i386-init.h and b/opcodes/i386-init.h differ
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 43c0d14..fe4fe97 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,8 +110,6 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
-  /* BMI support required */
-  CpuBMI,
   /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -188,7 +186,6 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
-      unsigned int cpubmi:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -218,8 +215,6 @@ enum
   S,
   /* insn has a modrm byte. */
   Modrm,
-  /* instruction has opcode extension in ModRM reg.  */
-  ModrmRegExt,
   /* register is in low 3 bits of opcode */
   ShortForm,
   /* special case for jump insns.  */
@@ -309,12 +304,12 @@ enum
 	For assembler, there are no difference between VEX.NDS and
 	VEX.DDS.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
-     3. VEX.VRM.  Register destination is encoded in VEX.vvvv and one
+     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 	of the operands can access a memory location.
    */
 #define VEXXDS	1
 #define VEXNDD	2
-#define VEXVRM	3
+#define VEXLWP	3
   VexVVVV,
   /* How the VEX.W bit is used:
      0: Set by the REX.W bit.
@@ -338,17 +333,14 @@ enum
 #define XOP08		3
 #define XOP09		4
 #define XOP0A		5
-#define XOP02		6
   VexOpcode,
   /* number of VEX source operands:
      0: <= 2 source operands.
      1: 2 XOP source operands.
      2: 3 source operands.
-     3: 2 XOP source operands but order reversed.
    */
 #define XOP2SOURCES	1
 #define VEX3SOURCES	2
-#define XOP2REVSOURCES	3
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
@@ -374,7 +366,6 @@ typedef struct i386_opcode_modifier
   unsigned int w:1;
   unsigned int s:1;
   unsigned int modrm:1;
-  unsigned int modrmregext:1;
   unsigned int shortform:1;
   unsigned int jump:1;
   unsigned int jumpdword:1;
@@ -410,7 +401,7 @@ typedef struct i386_opcode_modifier
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
-  unsigned int vexvvvv:3;
+  unsigned int vexvvvv:2;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 23eb2f2..f63919e 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,19 +2733,6 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
 
-// BMI instructions
-andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32, Reg32 }
-andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64, Reg64 }
-bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
-bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
-blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
-blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
-blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
-blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
-blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
-blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
-tzcnt,   2, 0xf30fbc, None, 2, CpuBMI, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
-
 // AMD 3DNow! instructions.
 
 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 72e1173..5c4e7e8 100644
Binary files a/opcodes/i386-tbl.h and b/opcodes/i386-tbl.h differ

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-20 22:33 [PATCH] AMD bdver2 processors 1/2 - BMI Quentin Neill
@ 2010-12-20 22:56 ` Sebastian Pop
  2010-12-20 23:25   ` Quentin Neill
  0 siblings, 1 reply; 23+ messages in thread
From: Sebastian Pop @ 2010-12-20 22:56 UTC (permalink / raw)
  To: Quentin Neill; +Cc: binutils

On Mon, Dec 20, 2010 at 16:32, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> These two patches add support for BMI and TBM ISAs to be introduced in
> AMD bdver2 processors.
>
> The full encoding specification is delayed, however I have posted
> abbreviated specs on the gcc mailing list:
> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>

Looks like your patch is reversed.  Could you please send another one
that you get from git format-patch -1

Thanks,
Sebastian

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-20 22:56 ` Sebastian Pop
@ 2010-12-20 23:25   ` Quentin Neill
  2010-12-21  2:30     ` Sebastian Pop
  2010-12-28 13:56     ` H.J. Lu
  0 siblings, 2 replies; 23+ messages in thread
From: Quentin Neill @ 2010-12-20 23:25 UTC (permalink / raw)
  To: Sebastian Pop; +Cc: binutils

[-- Attachment #1: Type: text/plain, Size: 751 bytes --]

On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> These two patches add support for BMI and TBM ISAs to be introduced in
>> AMD bdver2 processors.
>>
>> The full encoding specification is delayed, however I have posted
>> abbreviated specs on the gcc mailing list:
>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>
>
> Looks like your patch is reversed.  Could you please send another one
> that you get from git format-patch -1
>
> Thanks,
> Sebastian

Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
-- 
Quentin

[-- Attachment #2: 7037_bdver2_bmi.diff.txt --]
[-- Type: text/plain, Size: 59214 bytes --]

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 50216fd..08f908d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2010-12-20  Quentin Neill  <quentin.neill@amd.com>
+
+	* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
+	(build_modrm_byte): Add BMI instruction encoding.
+
+	* doc/c-i386.texi (i386-BMI): New section.
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* config/tc-mips.c (insn_uses_reg): Handle the new flags
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 9c33cf9..4c12e9f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -715,6 +715,8 @@ static const arch_entry cpu_arch[] =
     CPU_SSE4A_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
     CPU_ABM_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
+    CPU_BMI_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF
@@ -5550,7 +5552,8 @@ build_modrm_byte (void)
       else
 	mem = ~0;
 
-      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+      if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+          || (i.tm.opcode_modifier.vexsources == XOP2REVSOURCES))
 	{
 	  if (operand_type_check (i.types[0], imm))
 	    i.vex.register_specifier = NULL;
@@ -5558,7 +5561,8 @@ build_modrm_byte (void)
 	    {
 	      /* VEX.vvvv encodes one of the sources when the first
 		 operand is not an immediate.  */
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+                  && (i.tm.opcode_modifier.vexw == VEXW0))
 		i.vex.register_specifier = i.op[0].regs;
 	      else
 		i.vex.register_specifier = i.op[1].regs;
@@ -5575,7 +5579,8 @@ build_modrm_byte (void)
 	    {
 	      i.rm.mode = 3;
 
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+                  && (i.tm.opcode_modifier.vexw == VEXW0))
 		i.rm.regmem = i.op[1].regs->reg_num;
 	      else
 		i.rm.regmem = i.op[0].regs->reg_num;
@@ -5584,17 +5589,32 @@ build_modrm_byte (void)
 		i.rex |= REX_B;
 	    }
 	}
-      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)
 	{
-	  i.vex.register_specifier = i.op[2].regs;
+	  unsigned int regspec_op = MAX_OPERANDS;
+	  unsigned int regmem_op = MAX_OPERANDS; 
+	  if (i.tm.opcode_modifier.modrmregext)
+	    {
+	      i.rm.reg = i.tm.extension_opcode;
+	      regspec_op = 1;
+	      regmem_op = 0;
+	    }
+	  else
+	    {
+	      regspec_op = 2;
+	      regmem_op = 1;
+	    }
+
+	  i.vex.register_specifier = i.op[regspec_op].regs;
 	  if (!i.mem_operands)
 	    {
 	      i.rm.mode = 3;
-	      i.rm.regmem = i.op[1].regs->reg_num;
-	      if ((i.op[1].regs->reg_flags & RegRex) != 0)
+	      i.rm.regmem = i.op[regmem_op].regs->reg_num;
+	      if ((i.op[regmem_op].regs->reg_flags & RegRex) != 0)
 		i.rex |= REX_B;
 	    }
 	}
+
       /* Fill in i.rm.reg or i.rm.regmem field with register operand
 	 (if any) based on i.tm.extension_opcode.  Again, we must be
 	 careful to make sure that segment/control/debug/test/MMX
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1c6175b..fd315b0 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,6 +35,7 @@ extending the Intel architecture to 64-bits.
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-LWP::                    AMD's Lightweight Profiling Instructions
+* i386-BMI::                    Bit Manipulation Instructions
 * i386-16bit::                  Writing 16-bit Code
 * i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
@@ -842,6 +843,20 @@ For detailed information on the LWP instruction set, see the
 @cite{AMD Lightweight Profiling Specification} available at
 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
 
+@node i386-BMI
+@section Bit Manipulation Instructions
+
+@cindex BMI, i386
+@cindex BMI, x86-64
+
+@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
+
+BMI instructions provide several instructions implementing individual
+bit manipulation operations such as isolation, masking, setting, or
+resetting.  
+
+@c Need to add a specification citation here.
+
 @node i386-16bit
 @section Writing 16-bit Code
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0cf93d6..01faa8d 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2010-12-20  Quentin Neill  <quentin.neill@amd.com>
+
+	* gas/i386/i386.exp: Run bmi and x86-64-bmi.
+	* gas/i386/bmi.d: New.
+	* gas/i386/bmi.s: New.
+	* gas/i386/x86-64-bmi.d: New.
+	* gas/i386/x86-64-bmi.s: New.
+	* gas/i386/arch-10.s: Add a BMI instruction.
+	* gas/i386/x86-64-arch-2.s: Likewise.
+	* gas/i386/arch-10.d: Add bmi flag and BMI instruction pattern.
+	* gas/i386/x86-64-arch-2.d: Likewise.
+	* gas/i386/arch-10-1.l: Add BMI instruction pattern.
+	* gas/i386/arch-10-2.l: Likewise.
+	* gas/i386/arch-10-3.l: Likewise.
+	* gas/i386/arch-10-4.l: Likewise.
+
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 0b78958..95f4425 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -29,6 +29,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -96,5 +97,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index d9e1b51..3e9d68f 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -28,6 +28,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -95,5 +96,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 75c07ec..7183ea0 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -21,6 +21,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -91,5 +92,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 3c40045..7cd68a3 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -19,6 +19,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -89,5 +90,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 3efd52d..6e40abd 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: i386 arch 10
 
@@ -36,5 +36,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
 #pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index d0fb12b..7c669eb 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -58,5 +58,7 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx
 # nop
 nopl (%eax)
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
new file mode 100644
index 0000000..1f89b7c
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.d
@@ -0,0 +1,153 @@
+#objdump: -dw
+#name: i386 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 ff       	andn   %edi,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 70 f2 0c fa    	andn   \(%edx,%edi,8\),%ecx,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c3       	andn   %ebx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 14 9b    	andn   \(%ebx,%ebx,4\),%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 b1 dc 36 00 00 	andn   0x36dc\(%ecx\),%edi,%esi
+[ 	]*[a-f0-9]+:	c4 e2 48 f2 1b       	andn   \(%ebx\),%esi,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f8       	andn   %eax,%ebx,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 c1       	andn   %ecx,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 a4 5e 86 a9 9d ae 	andn   -0x5162567a\(%esi,%ebx,2\),%edx,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 2e       	andn   \(%esi\),%edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c2       	andn   %edx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 d6       	andn   %esi,%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 be 53 21 ff ff 	andn   -0xdead\(%esi\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 74 19 0a 	andn   0xa\(%ecx,%ebx,1\),%esp,%esi
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 00       	andn   \(%eax\),%edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 7c 13 ce 	andn   -0x32\(%ebx,%edx,1\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 3b       	bextr  %eax,\(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 31       	bextr  %edi,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 58 f7 cf       	bextr  %esp,%edi,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 c1       	bextr  %ebp,%ecx,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 f8       	bextr  %ebx,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 d3       	bextr  %esi,%ebx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 68 f7 04 07    	bextr  %edx,\(%edi,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 2f       	bextr  %edi,\(%edi\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f7 e6       	bextr  %ecx,%esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 18       	bextr  %edi,\(%eax\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 05 00 00 00 00 	bextr  %eax,0x0\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 22       	bextr  %ebp,\(%edx\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 2c 85 0f a9 00 00 	bextr  %esi,0xa90f\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 7c 03 03 	bextr  %ebx,0x3\(%ebx,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 b9 ff ff ff 3f 	bextr  %edi,0x3fffffff\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 12    	bextr  %eax,\(%edx,%edx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 df       	blsi   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1b       	blsi   \(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 de       	blsi   %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 da       	blsi   %edx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 1f       	blsi   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 59 08    	blsi   0x8\(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1a       	blsi   \(%edx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 19       	blsi   \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 dd       	blsi   %ebp,%esp
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 1c 19    	blsi   \(%ecx,%ebx,1\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 1c 4d 03 00 00 00 	blsi   0x3\(,%ecx,2\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1c 02    	blsi   \(%edx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 71    	blsi   \(%ecx,%esi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%eax\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 d2       	blsmsk %edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d7       	blsmsk %edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 d5       	blsmsk %ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 d3       	blsmsk %ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 17       	blsmsk \(%edi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 14 85 00 00 00 00 	blsmsk 0x0\(,%eax,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d4       	blsmsk %esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 13       	blsmsk \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 d3    	blsmsk \(%ebx,%edx,8\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 d6       	blsmsk %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 94 7f af e6 3d a1 	blsmsk -0x5ec21951\(%edi,%edi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 48    	blsmsk \(%eax,%ecx,2\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 1b    	blsmsk \(%ebx,%ebx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 14 83    	blsmsk \(%ebx,%eax,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 8c 92 fe ca 00 00 	blsr   0xcafe\(%edx,%edx,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cf       	blsr   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 0c cd 00 00 00 00 	blsr   0x0\(,%ecx,8\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 c8       	blsr   %eax,%edx
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 0e       	blsr   \(%esi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 9d 51 35 b0 66 	blsr   0x66b03551\(,%ebx,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 0c 85 0a ff ff ff 	blsr   -0xf6\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 ce       	blsr   %esi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0b       	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 8c 7b 3a f2 00 00 	blsr   0xf23a\(%ebx,%edi,2\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 09       	blsr   \(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0c 05 05 00 00 00 	blsr   0x5\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cd       	blsr   %ebp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 8c 03 c3 41 00 00 	blsr   0x41c3\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 5d 03 00 00 00 	blsr   0x3\(,%ebx,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 49 5a    	blsr   0x5a\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	66 f3 0f bd 38       	lzcnt  \(%eax\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd e7       	lzcnt  %di,%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bd 06       	lzcnt  \(%esi\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 cd 00 00 00 00 	lzcnt  0x0\(,%ecx,8\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fc       	lzcnt  %sp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 35 09 60 ff ff 	lzcnt  -0x9ff7\(,%esi,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd bc cb 4d 6e 00 00 	lzcnt  0x6e4d\(%ebx,%ecx,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2a       	lzcnt  \(%edx\),%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bd c9       	lzcnt  %cx,%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bd dd       	lzcnt  %bp,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	66 f3 0f bd 04 05 00 00 00 00 	lzcnt  0x0\(,%eax,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd f8       	lzcnt  %ax,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd db       	lzcnt  %bx,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fa       	lzcnt  %dx,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 1f       	lzcnt  \(%edi\),%bx
+[ 	]*[a-f0-9]+:	f3 0f bd db          	lzcnt  %ebx,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd f9          	lzcnt  %ecx,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 14 09       	lzcnt  \(%ecx,%ecx,1\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd cf          	lzcnt  %edi,%ecx
+[ 	]*[a-f0-9]+:	f3 0f bd fc          	lzcnt  %esp,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 34 7d 00 00 00 00 	lzcnt  0x0\(,%edi,2\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bd 03          	lzcnt  \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bd 3c 43       	lzcnt  \(%ebx,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 1f          	lzcnt  \(%edi\),%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd ed          	lzcnt  %ebp,%ebp
+[ 	]*[a-f0-9]+:	f3 0f bd a3 ad de 00 00 	lzcnt  0xdead\(%ebx\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bd c6          	lzcnt  %esi,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd bc 00 05 63 00 00 	lzcnt  0x6305\(%eax,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd bc 07 74 8f ff ff 	lzcnt  -0x708c\(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 06          	lzcnt  \(%esi\),%eax
+[ 	]*[a-f0-9]+:	66 f3 0f bc eb       	tzcnt  %bx,%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bc c7       	tzcnt  %di,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc fd       	tzcnt  %bp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 14 16    	tzcnt  \(%esi,%edx,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0f       	tzcnt  \(%edi\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0a       	tzcnt  \(%edx\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 24 8d 00 00 00 00 	tzcnt  0x0\(,%ecx,4\),%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bc 31       	tzcnt  \(%ecx\),%si
+[ 	]*[a-f0-9]+:	66 f3 0f bc 03       	tzcnt  \(%ebx\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 3c c7    	tzcnt  \(%edi,%eax,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 1c 3b    	tzcnt  \(%ebx,%edi,1\),%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc c1       	tzcnt  %cx,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc b9 63 27 ff ff 	tzcnt  -0xd89d\(%ecx\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	f3 0f bc f8          	tzcnt  %eax,%edi
+[ 	]*[a-f0-9]+:	f3 0f bc f7          	tzcnt  %edi,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 44 3b 61    	tzcnt  0x61\(%ebx,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc de          	tzcnt  %esi,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 2a          	tzcnt  \(%edx\),%ebp
+[ 	]*[a-f0-9]+:	f3 0f bc 16          	tzcnt  \(%esi\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bc 0c 0f       	tzcnt  \(%edi,%ecx,1\),%ecx
+[ 	]*[a-f0-9]+:	f3 0f bc f5          	tzcnt  %ebp,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 07          	tzcnt  \(%edi\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 07       	tzcnt  \(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 00       	tzcnt  \(%eax,%eax,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc 00          	tzcnt  \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 45 bf ff ff ff 	tzcnt  -0x41\(,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 1d 01 00 00 c0 	tzcnt  -0x3fffffff\(,%ebx,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc c3          	tzcnt  %ebx,%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3b          	tzcnt  \(%ebx\),%edi
+
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
new file mode 100644
index 0000000..f3f9c38
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.s
@@ -0,0 +1,151 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %edi,%eax,%edi
+    ANDN     (%edx,%edi,8),%ecx,%ecx
+    ANDN     %ebx,%esp,%eax
+    ANDN     (%ebx,%ebx,4),%ebp,%edx
+    ANDN     0x36DC(%ecx),%edi,%esi
+    ANDN     (%ebx),%esi,%ebx
+    ANDN     %eax,%ebx,%edi
+    ANDN     %ecx,%eax,%eax
+    ANDN     -0x5162567A(%esi,%ebx,2),%edx,%esp
+    ANDN     (%esi),%edx,%ebp
+    ANDN     %edx,%esp,%eax
+    ANDN     %esi,%ebp,%edx
+    ANDN     -0xDEAD(%esi),%edi,%edi
+    ANDN     0xA(%ecx,%ebx),%esp,%esi
+    ANDN     (%eax),%edi,%eax
+    ANDN     -0x32(%ebx,%edx),%edi,%edi
+    BEXTR    %eax,(%ebx),%edi
+    BEXTR    %edi,(%ecx),%esi
+    BEXTR    %esp,%edi,%ecx
+    BEXTR    %ebp,%ecx,%eax
+    BEXTR    %ebx,%eax,%edi
+    BEXTR    %esi,%ebx,%edx
+    BEXTR    %edx,(%edi,%eax),%eax
+    BEXTR    %edi,(%edi),%ebp
+    BEXTR    %ecx,%esi,%esp
+    BEXTR    %edi,0x0(%eax),%ebx
+    BEXTR    %eax,(,%eax,1),%eax
+    BEXTR    %ebp,(%edx),%esp
+    BEXTR    %esi,0xA90F(,%eax,4),%ebp
+    BEXTR    %ebx,0x3(%ebx,%eax),%edi
+    BEXTR    %edi,0x3FFFFFFF(%ecx),%edi
+    BEXTR    %eax,(%edx,%edx),%eax
+    BLSI     %edi,%eax
+    BLSI     %eax,%edi
+    BLSI     (%ebx),%edi
+    BLSI     %esi,%esp
+    BLSI     %edx,%edx
+    BLSI     (%edi),%esi
+    BLSI     0x8(%ecx),%ebx
+    BLSI     (%edx),%eax
+    BLSI     (%ecx),%eax
+    BLSI     %ebp,%esp
+    BLSI     (%ecx,%ebx),%ebp
+    BLSI     0x3(,%ecx,2),%ecx
+    BLSI     (%edx,%eax),%eax
+    BLSI     (%ecx,%esi,2),%edi
+    BLSI     %eax,%edi
+    BLSI     (%eax),%eax
+    BLSMSK   %edx,%ebp
+    BLSMSK   %edi,%edi
+    BLSMSK   %eax,%eax
+    BLSMSK   %ebp,%edx
+    BLSMSK   %ebx,%esi
+    BLSMSK   (%edi),%ecx
+    BLSMSK   (%ecx),%ebx
+    BLSMSK   (,%eax,4),%esp
+    BLSMSK   %esp,%eax
+    BLSMSK   (%ebx),%eax
+    BLSMSK   (%ebx,%edx,8),%eax
+    BLSMSK   %esi,%esp
+    BLSMSK   -0x5EC21951(%edi,%edi,2),%edi
+    BLSMSK   (%eax,%ecx,2),%eax
+    BLSMSK   (%ebx,%ebx),%eax
+    BLSMSK   (%ebx,%eax,4),%edi
+    BLSR     0xCAFE(%edx,%edx,4),%esp
+    BLSR     %edi,%eax
+    BLSR     (,%ecx,8),%esi
+    BLSR     %eax,%edx
+    BLSR     (%esi),%ecx
+    BLSR     0x66B03551(,%ebx,4),%edi
+    BLSR     -0xF6(,%eax,4),%ebp
+    BLSR     %esi,%edi
+    BLSR     (%ebx),%eax
+    BLSR     0xF23A(%ebx,%edi,2),%ebx
+    BLSR     (%ecx),%edi
+    BLSR     0x5(,%eax),%eax
+    BLSR     %ebp,%eax
+    BLSR     0x41C3(%ebx,%eax),%eax
+    BLSR     0x3(,%ebx,2),%edi
+    BLSR     0x5A(%ecx),%edi
+    LZCNT    (%eax),%di
+    LZCNT    %di,%sp
+    LZCNT    (%esi),%ax
+    LZCNT    (,%ecx,8),%dx
+    LZCNT    %sp,%di
+    LZCNT    -0x9FF7(,%esi),%dx
+    LZCNT    0x6E4D(%ebx,%ecx,8),%di
+    LZCNT    (%edx),%bp
+    LZCNT    %cx,%cx
+    LZCNT    %bp,%bx
+    LZCNT    %si,%si
+    LZCNT    (,%eax,1),%ax
+    LZCNT    %ax,%di
+    LZCNT    %bx,%bx
+    LZCNT    %dx,%di
+    LZCNT    (%edi),%bx
+    LZCNT    %ebx,%ebx
+    LZCNT    %ecx,%edi
+    LZCNT    (%ecx,%ecx),%edx
+    LZCNT    %eax,%eax
+    LZCNT    %edi,%ecx
+    LZCNT    %esp,%edi
+    LZCNT    (,%edi,2),%esi
+    LZCNT    (%ebx),%eax
+    LZCNT    (%ebx,%eax,2),%edi
+    LZCNT    (%edi),%ebx
+    LZCNT    %ebp,%ebp
+    LZCNT    0xDEAD(%ebx),%esp
+    LZCNT    %esi,%eax
+    LZCNT    0x6305(%eax,%eax,1),%edi
+    LZCNT    -0x708C(%edi,%eax),%edi
+    LZCNT    (%esi),%eax
+    TZCNT    %bx,%bp
+    TZCNT    %di,%ax
+    TZCNT    %bp,%di
+    TZCNT    (%esi,%edx,1),%dx
+    TZCNT    (%edi),%cx
+    TZCNT    (%edx),%cx
+    TZCNT    %ax,%bx
+    TZCNT    (,%ecx,4),%sp
+    TZCNT    (%ecx),%si
+    TZCNT    (%ebx),%ax
+    TZCNT    (%edi,%eax,8),%di
+    TZCNT    (%ebx,%edi),%bx
+    TZCNT    %cx,%ax
+    TZCNT    -0xD89D(%ecx),%di
+    TZCNT    %bp,%ax
+    TZCNT    %bp,%ax
+    TZCNT    %eax,%edi
+    TZCNT    %edi,%esi
+    TZCNT    0x61(%ebx,%edi),%eax
+    TZCNT    %esi,%ebx
+    TZCNT    (%edx),%ebp
+    TZCNT    (%esi),%edx
+    TZCNT    (%edi,%ecx),%ecx
+    TZCNT    %ebp,%esi
+    TZCNT    (%edi),%eax
+    TZCNT    (%edi,%eax,1),%edi
+    TZCNT    (%eax,%eax),%esp
+    TZCNT    (%eax),%eax
+    TZCNT    -0x41(,%eax,2),%edi
+    TZCNT    -0x3FFFFFFF(,%ebx),%esp
+    TZCNT    %ebx,%eax
+    TZCNT    (%ebx),%edi
+
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a966d7..01a3ecb 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
+    run_dump_test "bmi"
     run_dump_test "f16c"
     run_dump_test "f16c-intel"
     run_dump_test "fsgs"
@@ -372,6 +373,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
+    run_dump_test "x86-64-bmi"
     run_dump_test "x86-64-f16c"
     run_dump_test "x86-64-f16c-intel"
     run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 9cd1306..ac09453 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: x86-64 arch 2
 
@@ -36,4 +36,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index ddc0d40..962f15e 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,3 +58,5 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
new file mode 100644
index 0000000..180e40f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.d
@@ -0,0 +1,265 @@
+#objdump: -dw
+#name: x86-64 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 c2 00 f2 c0       	andn   %r8d,%r15d,%eax
+[ 	]*[a-f0-9]+:	c4 62 78 f2 14 0e    	andn   \(%rsi,%rcx,1\),%eax,%r10d
+[ 	]*[a-f0-9]+:	67 c4 c2 48 f2 2e    	andn   \(%r14d\),%esi,%ebp
+[ 	]*[a-f0-9]+:	c4 42 40 f2 7d 00    	andn   0x0\(%r13\),%edi,%r15d
+[ 	]*[a-f0-9]+:	c4 42 18 f2 fe       	andn   %r14d,%r12d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 08 f2 3c 50 	andn   \(%r8d,%r10d,2\),%r14d,%edi
+[ 	]*[a-f0-9]+:	67 c4 42 28 f2 29    	andn   \(%r9d\),%r10d,%r13d
+[ 	]*[a-f0-9]+:	67 c4 22 70 f2 0c bd 00 00 00 00 	andn   0x0\(,%r15d,4\),%ecx,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 38 f2 24 85 00 00 00 00 	andn   0x0\(,%r8,4\),%r8d,%esp
+[ 	]*[a-f0-9]+:	c4 62 38 f2 24 07    	andn   \(%rdi,%rax,1\),%r8d,%r12d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f2 44 1d 00 	andn   0x0\(%r13d,%ebx,1\),%r11d,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f2       	andn   %edx,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 c2 58 f2 11       	andn   \(%r9\),%esp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 00 f2 0f       	andn   \(%rdi\),%r15d,%ecx
+[ 	]*[a-f0-9]+:	67 c4 62 50 f2 37    	andn   \(%edi\),%ebp,%r14d
+[ 	]*[a-f0-9]+:	c4 a2 28 f2 84 83 fa b5 bb c6 	andn   -0x39444a06\(%rbx,%r8,4\),%r10d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f2 02    	andn   \(%r10d\),%rax,%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f2 16    	andn   \(%r14d\),%r15,%rdx
+[ 	]*[a-f0-9]+:	c4 02 d8 f2 bc 0f 93 5b 00 00 	andn   0x5b93\(%r15,%r9,1\),%rsp,%r15
+[ 	]*[a-f0-9]+:	c4 42 a0 f2 09       	andn   \(%r9\),%r11,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f2 3c 45 00 00 00 00 	andn   0x0\(,%eax,2\),%r15,%rdi
+[ 	]*[a-f0-9]+:	c4 62 c8 f2 dd       	andn   %rbp,%rsi,%r11
+[ 	]*[a-f0-9]+:	c4 42 e0 f2 45 00    	andn   0x0\(%r13\),%rbx,%r8
+[ 	]*[a-f0-9]+:	c4 62 c0 f2 d0       	andn   %rax,%rdi,%r10
+[ 	]*[a-f0-9]+:	c4 c2 98 f2 e4       	andn   %r12,%r12,%rsp
+[ 	]*[a-f0-9]+:	67 c4 62 a8 f2 3e    	andn   \(%esi\),%r10,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f2 3a    	andn   \(%edx\),%rax,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f2 37    	andn   \(%r15d\),%r8,%rsi
+[ 	]*[a-f0-9]+:	67 c4 42 80 f2 20    	andn   \(%r8d\),%r15,%r12
+[ 	]*[a-f0-9]+:	c4 c2 80 f2 ef       	andn   %r15,%r15,%rbp
+[ 	]*[a-f0-9]+:	c4 a2 d0 f2 0c e5 00 00 00 00 	andn   0x0\(,%r12,8\),%rbp,%rcx
+[ 	]*[a-f0-9]+:	c4 62 f0 f2 2a       	andn   \(%rdx\),%rcx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 00 f7 c0       	bextr  %r15d,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 42 78 f7 fa       	bextr  %eax,%r10d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 68 f7 0c cf 	bextr  %edx,\(%r15d,%r9d,8\),%ecx
+[ 	]*[a-f0-9]+:	c4 02 50 f7 54 3d 00 	bextr  %ebp,0x0\(%r13,%r15,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 20 f7 ef       	bextr  %r11d,%r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 82 00 f7 64 35 00 	bextr  %r15d,0x0\(%r13,%r14,1\),%esp
+[ 	]*[a-f0-9]+:	67 c4 02 30 f7 84 c3 ad de 00 00 	bextr  %r9d,0xdead\(%r11d,%r8d,8\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f7 44 04 01 	bextr  %r11d,0x1\(%r12d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 42 28 f7 76 f4 	bextr  %r10d,-0xc\(%r14d\),%r14d
+[ 	]*[a-f0-9]+:	c4 62 78 f7 18       	bextr  %eax,\(%rax\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 c2 60 f7 14 24 	bextr  %ebx,\(%r12d\),%edx
+[ 	]*[a-f0-9]+:	67 c4 62 48 f7 28    	bextr  %esi,\(%eax\),%r13d
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 dd       	bextr  %eax,%ebp,%ebx
+[ 	]*[a-f0-9]+:	c4 c2 78 f7 04 24    	bextr  %eax,\(%r12\),%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 50 f7 04 02 	bextr  %ebp,\(%r10d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 e2 10 f7 44 03 99 	bextr  %r13d,-0x67\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 82 a8 f7 84 7b fe ca 00 00 	bextr  %r10,0xcafe\(%r11,%r15,2\),%rax
+[ 	]*[a-f0-9]+:	c4 42 a8 f7 b1 fe ca 00 00 	bextr  %r10,0xcafe\(%r9\),%r14
+[ 	]*[a-f0-9]+:	c4 62 f8 f7 ff       	bextr  %rax,%rdi,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f7 2a    	bextr  %rax,\(%edx\),%r13
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 17       	bextr  %rax,\(%r15\),%r10
+[ 	]*[a-f0-9]+:	c4 c2 80 f7 ea       	bextr  %r15,%r10,%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 f8 f7 3e    	bextr  %rax,\(%esi\),%rdi
+[ 	]*[a-f0-9]+:	c4 42 98 f7 e1       	bextr  %r12,%r9,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f7 dd       	bextr  %r8,%r13,%rbx
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 24 24    	bextr  %rax,\(%r12\),%rsp
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 5d 00    	bextr  %rax,0x0\(%r13\),%r11
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 30       	bextr  %rax,\(%r8\),%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f0 f7 d6       	bextr  %rcx,%rsi,%rdx
+[ 	]*[a-f0-9]+:	67 c4 02 b8 f7 7c 0a 03 	bextr  %r8,0x3\(%r10d,%r9d,1\),%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 07    	bextr  %rax,\(%r15d\),%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 08    	bextr  %rax,\(%r8d\),%rcx
+[ 	]*[a-f0-9]+:	67 c4 a2 48 f3 1c 7d f3 ff ff ff 	blsi   -0xd\(,%r15d,2\),%esi
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 df       	blsi   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d8       	blsi   %eax,%eax
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 19       	blsi   \(%r9\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 dd       	blsi   %ebp,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 68 f3 1c 4d 05 00 00 00 	blsi   0x5\(,%r9,2\),%edx
+[ 	]*[a-f0-9]+:	c4 a2 70 f3 1c 5d 96 ff ff ff 	blsi   -0x6a\(,%r11,2\),%ecx
+[ 	]*[a-f0-9]+:	67 c4 e2 50 f3 19    	blsi   \(%ecx\),%ebp
+[ 	]*[a-f0-9]+:	67 c4 e2 20 f3 1f    	blsi   \(%edi\),%r11d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 5f f9    	blsi   -0x7\(%rdi\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 10 f3 18    	blsi   \(%r8d\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 60 f3 1a       	blsi   \(%r10\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 05 fe ca 00 00 	blsi   0xcafe\(,%rax,1\),%edi
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 1e    	blsi   \(%esi\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 78 f3 d9       	blsi   %r9d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 78 f3 5c 3a 99 	blsi   -0x67\(%r10d,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 5a 0f    	blsi   0xf\(%r10\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 df       	blsi   %r15,%rax
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 d8       	blsi   %rax,%rsp
+[ 	]*[a-f0-9]+:	67 c4 e2 a8 f3 18    	blsi   \(%eax\),%r10
+[ 	]*[a-f0-9]+:	67 c4 c2 90 f3 18    	blsi   \(%r8d\),%r13
+[ 	]*[a-f0-9]+:	67 c4 a2 88 f3 9c cf 85 00 00 00 	blsi   0x85\(%edi,%r9d,8\),%r14
+[ 	]*[a-f0-9]+:	c4 c2 98 f3 da       	blsi   %r10,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f3 1b       	blsi   \(%r11\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 b0 f3 9f 20 d6 db b8 	blsi   -0x472429e0\(%r15\),%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 e8 f3 1f    	blsi   \(%edi\),%rdx
+[ 	]*[a-f0-9]+:	67 c4 e2 e0 f3 1c 95 00 00 00 00 	blsi   0x0\(,%edx,4\),%rbx
+[ 	]*[a-f0-9]+:	67 c4 e2 c0 f3 1b    	blsi   \(%ebx\),%rdi
+[ 	]*[a-f0-9]+:	c4 c2 f0 f3 9a ad de 00 00 	blsi   0xdead\(%r10\),%rcx
+[ 	]*[a-f0-9]+:	c4 82 c0 f3 5c f7 1b 	blsi   0x1b\(%r15,%r14,8\),%rdi
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 1b       	blsi   \(%rbx\),%r11
+[ 	]*[a-f0-9]+:	c4 82 f8 f3 5c 08 0a 	blsi   0xa\(%r8,%r9,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 a2 48 f3 14 8d 00 00 00 00 	blsmsk 0x0\(,%r9,4\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 00 f3 14 7d 00 00 00 00 	blsmsk 0x0\(,%edi,2\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 17       	blsmsk \(%rdi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 c2 70 f3 55 00 	blsmsk 0x0\(%r13d\),%ecx
+[ 	]*[a-f0-9]+:	c4 c2 08 f3 d1       	blsmsk %r9d,%r14d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 12       	blsmsk \(%rdx\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 e2 18 f3 16    	blsmsk \(%esi\),%r12d
+[ 	]*[a-f0-9]+:	c4 c2 20 f3 94 15 c5 22 f8 65 	blsmsk 0x65f822c5\(%r13,%rdx,1\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 54 0b fd 	blsmsk -0x3\(%ebx,%ecx,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 50 f3 d7       	blsmsk %r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 10 f3 d6       	blsmsk %esi,%r13d
+[ 	]*[a-f0-9]+:	c4 c2 68 f3 17       	blsmsk \(%r15\),%edx
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 16       	blsmsk \(%r14\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d5       	blsmsk %ebp,%edi
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 14 21    	blsmsk \(%rcx,%r12,1\),%ebx
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 d7       	blsmsk %r15,%rdx
+[ 	]*[a-f0-9]+:	c4 e2 f8 f3 14 c8    	blsmsk \(%rax,%rcx,8\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 17    	blsmsk \(%r15d\),%r8
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 d0       	blsmsk %rax,%r15
+[ 	]*[a-f0-9]+:	c4 e2 98 f3 56 fd    	blsmsk -0x3\(%rsi\),%r12
+[ 	]*[a-f0-9]+:	c4 e2 c8 f3 14 12    	blsmsk \(%rdx,%rdx,1\),%rsi
+[ 	]*[a-f0-9]+:	c4 c2 e0 f3 16       	blsmsk \(%r14\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 c0 f3 17       	blsmsk \(%r15\),%rdi
+[ 	]*[a-f0-9]+:	c4 a2 d0 f3 14 25 24 ff ff ff 	blsmsk -0xdc\(,%r12,1\),%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 a0 f3 13    	blsmsk \(%ebx\),%r11
+[ 	]*[a-f0-9]+:	67 c4 a2 f8 f3 14 35 b8 43 00 00 	blsmsk 0x43b8\(,%r14d,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 90 f3 d2       	blsmsk %rdx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 b0 f3 d5       	blsmsk %rbp,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 d8 f3 10    	blsmsk \(%eax\),%rsp
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f3 16    	blsmsk \(%r14d\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 cf       	blsr   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 c8       	blsr   %eax,%r9d
+[ 	]*[a-f0-9]+:	67 c4 e2 08 f3 0c 15 01 00 00 00 	blsr   0x1\(,%edx,1\),%r14d
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 ca       	blsr   %edx,%ecx
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 0c 71    	blsr   \(%rcx,%r14,2\),%ebx
+[ 	]*[a-f0-9]+:	67 c4 a2 78 f3 0c 8d 4a 46 00 00 	blsr   0x464a\(,%r9d,4\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 0e       	blsr   \(%rsi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 09    	blsr   \(%ecx\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 0f    	blsr   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 0c 7d 00 00 00 00 	blsr   0x0\(,%edi,2\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 20 f3 0a       	blsr   \(%rdx\),%r11d
+[ 	]*[a-f0-9]+:	c4 c2 10 f3 0b       	blsr   \(%r11\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 38 f3 c9       	blsr   %r9d,%r8d
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 cf       	blsr   %edi,%edx
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 0b    	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 08       	blsr   \(%rax\),%edi
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 0b       	blsr   \(%r11\),%r15
+[ 	]*[a-f0-9]+:	67 c4 e2 b0 f3 0c 0d 03 00 00 00 	blsr   0x3\(,%ecx,1\),%r9
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 0e       	blsr   \(%rsi\),%rsp
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 4d 00    	blsr   0x0\(%r13\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 cf       	blsr   %r15,%rdx
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 0e    	blsr   \(%r14d\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 0e       	blsr   \(%r14\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 d0 f3 08       	blsr   \(%r8\),%rbp
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 ca       	blsr   %rdx,%r11
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f3 0a    	blsr   \(%edx\),%r15
+[ 	]*[a-f0-9]+:	67 c4 a2 e0 f3 0c 25 7e 33 00 00 	blsr   0x337e\(,%r12d,1\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 f0 f3 08       	blsr   \(%rax\),%rcx
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 cd       	blsr   %rbp,%rsp
+[ 	]*[a-f0-9]+:	c4 e2 a8 f3 c8       	blsr   %rax,%r10
+[ 	]*[a-f0-9]+:	c4 82 98 f3 4c a5 67 	blsr   0x67\(%r13,%r12,4\),%r12
+[ 	]*[a-f0-9]+:	67 c4 a2 c0 f3 0c 2d 00 00 00 00 	blsr   0x0\(,%r13d,1\),%rdi
+[ 	]*[a-f0-9]+:	67 66 f3 46 0f bd 2c 05 5a 1f 00 00 	lzcnt  0x1f5a\(,%r8d,1\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd e0    	lzcnt  %ax,%r12w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 11    	lzcnt  \(%r9\),%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd c5    	lzcnt  %r13w,%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 3c c5 99 ff ff ff 	lzcnt  -0x67\(,%rax,8\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd 7c 15 00 	lzcnt  0x0\(%r13,%rdx,1\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2f       	lzcnt  \(%rdi\),%bp
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 03    	lzcnt  \(%r11\),%r8w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd f7    	lzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 26 	lzcnt  \(%r14d\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 09    	lzcnt  \(%rcx\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 8c db e7 9a 00 00 	lzcnt  0x9ae7\(%r11,%rbx,8\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	67 66 f3 0f bd 0b    	lzcnt  \(%ebx\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 1a 	lzcnt  \(%r10d\),%bx
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd f1    	lzcnt  %r9w,%r14w
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 7d 00 	lzcnt  0x0\(%r13d\),%r15d
+[ 	]*[a-f0-9]+:	f3 0f bd e7          	lzcnt  %edi,%esp
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 2e    	lzcnt  \(%r14d\),%r13d
+[ 	]*[a-f0-9]+:	f3 41 0f bd 16       	lzcnt  \(%r14\),%edx
+[ 	]*[a-f0-9]+:	f3 45 0f bd df       	lzcnt  %r15d,%r11d
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 41 0f bd 30       	lzcnt  \(%r8\),%esi
+[ 	]*[a-f0-9]+:	f3 45 0f bd f9       	lzcnt  %r9d,%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd 04 24    	lzcnt  \(%r12\),%r8d
+[ 	]*[a-f0-9]+:	f3 41 0f bd e8       	lzcnt  %r8d,%ebp
+[ 	]*[a-f0-9]+:	67 f3 41 0f bd 1a    	lzcnt  \(%r10d\),%ebx
+[ 	]*[a-f0-9]+:	f3 41 0f bd 3c 0c    	lzcnt  \(%r12,%rcx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 44 0f bd 3f       	lzcnt  \(%rdi\),%r15d
+[ 	]*[a-f0-9]+:	67 f3 44 0f bd 3f    	lzcnt  \(%edi\),%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd d4       	lzcnt  %r12d,%r10d
+[ 	]*[a-f0-9]+:	f3 42 0f bd 04 2d 00 00 00 00 	lzcnt  0x0\(,%r13,1\),%eax
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 6d 00 	lzcnt  0x0\(%r13d\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 02    	lzcnt  \(%r10d\),%r8
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 06    	lzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 4c 0f bd eb       	lzcnt  %rbx,%r13
+[ 	]*[a-f0-9]+:	f3 4d 0f bd 39       	lzcnt  \(%r9\),%r15
+[ 	]*[a-f0-9]+:	f3 48 0f bd ca       	lzcnt  %rdx,%rcx
+[ 	]*[a-f0-9]+:	f3 4a 0f bd 04 6d 00 00 00 00 	lzcnt  0x0\(,%r13,2\),%rax
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 30    	lzcnt  \(%eax\),%rsi
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 27    	lzcnt  \(%r15d\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4e 0f bd 1c bd 00 00 00 00 	lzcnt  0x0\(,%r15d,4\),%r11
+[ 	]*[a-f0-9]+:	f3 4d 0f bd e7       	lzcnt  %r15,%r12
+[ 	]*[a-f0-9]+:	f3 48 0f bd 17       	lzcnt  \(%rdi\),%rdx
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 0c 24 	lzcnt  \(%r12d\),%r9
+[ 	]*[a-f0-9]+:	f3 4d 0f bd d3       	lzcnt  %r11,%r10
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bd 2c dd fe ca 00 00 	lzcnt  0xcafe\(,%ebx,8\),%r13
+[ 	]*[a-f0-9]+:	f3 48 0f bd c0       	lzcnt  %rax,%rax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc f2    	tzcnt  %r10w,%r14w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 86 7a 73 00 00 	tzcnt  0x737a\(%r14\),%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc d0    	tzcnt  %ax,%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc f7    	tzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 3c 24 	tzcnt  \(%r12\),%r15w
+[ 	]*[a-f0-9]+:	67 66 f3 0f bc 22    	tzcnt  \(%edx\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 28    	tzcnt  \(%rax\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc ec    	tzcnt  %r12w,%bp
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 81 ad 3c 00 00 	tzcnt  0x3cad\(%r9d\),%ax
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 44 12 06 	tzcnt  0x6\(%r10,%rdx,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc dd    	tzcnt  %r13w,%r11w
+[ 	]*[a-f0-9]+:	67 66 f3 43 0f bc 0c 32 	tzcnt  \(%r10d,%r14d,1\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc a4 9a 44 ae d0 4c 	tzcnt  0x4cd0ae44\(%r10d,%ebx,4\),%r12w
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc 3f 	tzcnt  \(%r15d\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 08    	tzcnt  \(%r8\),%r9w
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 01 	tzcnt  \(%r9d\),%ax
+[ 	]*[a-f0-9]+:	f3 41 0f bc 10       	tzcnt  \(%r8\),%edx
+[ 	]*[a-f0-9]+:	67 f3 44 0f bc 1e    	tzcnt  \(%esi\),%r11d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 02       	tzcnt  \(%r10\),%eax
+[ 	]*[a-f0-9]+:	f3 45 0f bc 7c 16 c3 	tzcnt  -0x3d\(%r14,%rdx,1\),%r15d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 75 00    	tzcnt  0x0\(%r13\),%esi
+[ 	]*[a-f0-9]+:	f3 44 0f bc 27       	tzcnt  \(%rdi\),%r12d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 01       	tzcnt  \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	f3 47 0f bc ac e9 bc 9a ff ff 	tzcnt  -0x6544\(%r9,%r13,8\),%r13d
+[ 	]*[a-f0-9]+:	f3 0f bc e0          	tzcnt  %eax,%esp
+[ 	]*[a-f0-9]+:	f3 45 0f bc c7       	tzcnt  %r15d,%r8d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 3c 0d f1 ff ff ff 	tzcnt  -0xf\(,%ecx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 45 0f bc 09       	tzcnt  \(%r9\),%r9d
+[ 	]*[a-f0-9]+:	f3 0f bc 21          	tzcnt  \(%rcx\),%esp
+[ 	]*[a-f0-9]+:	f3 43 0f bc 2c 10    	tzcnt  \(%r8,%r10,1\),%ebp
+[ 	]*[a-f0-9]+:	f3 46 0f bc 34 17    	tzcnt  \(%rdi,%r10,1\),%r14d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 30       	tzcnt  \(%eax\),%esi
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bc 0f    	tzcnt  \(%edi\),%r9
+[ 	]*[a-f0-9]+:	f3 49 0f bc 29       	tzcnt  \(%r9\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bc 3c 9f 	tzcnt  \(%r15d,%ebx,4\),%r15
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 26       	tzcnt  \(%r14\),%r12
+[ 	]*[a-f0-9]+:	f3 4e 0f bc 14 05 0e 8a f2 62 	tzcnt  0x62f28a0e\(,%r8,1\),%r10
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 34 30    	tzcnt  \(%r8,%rsi,1\),%r14
+[ 	]*[a-f0-9]+:	67 f3 48 0f bc 06    	tzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc c5       	tzcnt  %r13,%rax
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 81 6c 3d 00 00 	tzcnt  0x3d6c\(%r9\),%r8
+[ 	]*[a-f0-9]+:	f3 4c 0f bc f8       	tzcnt  %rax,%r15
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 24 4d 00 00 00 00 	tzcnt  0x0\(,%r9,2\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4a 0f bc 1c e5 00 00 00 00 	tzcnt  0x0\(,%r12d,8\),%rbx
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 1c 16    	tzcnt  \(%rsi,%rdx,1\),%r11
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 3c a9    	tzcnt  \(%rcx,%r13,4\),%rdi
+[ 	]*[a-f0-9]+:	f3 49 0f bc 44 c3 f1 	tzcnt  -0xf\(%r11,%rax,8\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc 00       	tzcnt  \(%r8\),%rax
+
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
new file mode 100644
index 0000000..e4059ec
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.s
@@ -0,0 +1,263 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %eax,%r15d,%eax
+    ANDN     (%rsi,%rcx),%eax,%r10d
+    ANDN     (%r14d),%esi,%ebp
+    ANDN     (%r13),%edi,%r15d
+    ANDN     %esi,%r12d,%r15d
+    ANDN     (%r8d,%r10d,2),%r14d,%edi
+    ANDN     (%r9d),%r10d,%r13d
+    ANDN     (,%r15d,4),%ecx,%r9d
+    ANDN     (,%r8,4),%r8d,%esp
+    ANDN     (%rdi,%rax),%r8d,%r12d
+    ANDN     (%r13d,%ebx),%r11d,%eax
+    ANDN     %edx,%ebx,%esi
+    ANDN     (%r9),%esp,%edx
+    ANDN     (%rdi),%r15d,%ecx
+    ANDN     (%edi),%ebp,%r14d
+    ANDN     -0x39444A06(%rbx,%r8,4),%r10d,%eax
+    ANDN     (%r10d),%rax,%rax
+    ANDN     (%r14d),%r15,%rdx
+    ANDN     0x5B93(%r15,%r9),%rsp,%r15
+    ANDN     (%r9),%r11,%r9
+    ANDN     (,%eax,2),%r15,%rdi
+    ANDN     %rbp,%rsi,%r11
+    ANDN     (%r13),%rbx,%r8
+    ANDN     %rax,%rdi,%r10
+    ANDN     %rsp,%r12,%rsp
+    ANDN     (%esi),%r10,%r15
+    ANDN     (%edx),%rax,%r15
+    ANDN     (%r15d),%r8,%rsi
+    ANDN     (%r8d),%r15,%r12
+    ANDN     %rdi,%r15,%rbp
+    ANDN     (,%r12,8),%rbp,%rcx
+    ANDN     (%rdx),%rcx,%r13
+    BEXTR    %r15d,%eax,%eax
+    BEXTR    %eax,%r10d,%r15d
+    BEXTR    %edx,(%r15d,%r9d,8),%ecx
+    BEXTR    %ebp,(%r13,%r15),%r10d
+    BEXTR    %r11d,%r15d,%ebp
+    BEXTR    %r15d,(%r13,%r14),%esp
+    BEXTR    %r9d,0xDEAD(%r11d,%r8d,8),%r8d
+    BEXTR    %r11d,0x1(%r12d,%eax),%eax
+    BEXTR    %r10d,-0xC(%r14d),%r14d
+    BEXTR    %eax,(%rax),%r11d
+    BEXTR    %ebx,(%r12d),%edx
+    BEXTR    %esi,(%eax),%r13d
+    BEXTR    %eax,%ebp,%ebx
+    BEXTR    %eax,(%r12),%eax
+    BEXTR    %ebp,(%r10d,%eax),%eax
+    BEXTR    %r13d,-0x67(%ebx,%eax),%eax
+    BEXTR    %r15,0xCAFE(%r11,%r15,2),%rax
+    BEXTR    %r14,0xCAFE(%r9),%r14
+    BEXTR    %rdi,%rax,%r15
+    BEXTR    %rax,(%edx),%r13
+    BEXTR    %rdx,(%r15),%r10
+    BEXTR    %r10,%r15,%rbp
+    BEXTR    %r12,(%esi),%rdi
+    BEXTR    %rcx,%r12,%r12
+    BEXTR    %rbp,%r8,%rbx
+    BEXTR    %rbx,(%r12),%rsp
+    BEXTR    %r9,(%r13),%r11
+    BEXTR    %r11,(%r8),%rsi
+    BEXTR    %rsi,%rcx,%rdx
+    BEXTR    %r13,0x3(%r10d,%r9d,1),%r15
+    BEXTR    %rax,(%r15d),%rax
+    BEXTR    %r15,(%r8d),%rcx
+    BLSI     -0xD(,%r15d,2),%esi
+    BLSI     %r15d,%r15d
+    BLSI     %eax,%eax
+    BLSI     (%r9),%r10d
+    BLSI     %ebp,%r9d
+    BLSI     0x5(,%r9,2),%edx
+    BLSI     -0x6A(,%r11,2),%ecx
+    BLSI     (%ecx),%ebp
+    BLSI     (%edi),%r11d
+    BLSI     -0x7(%rdi),%r8d
+    BLSI     (%r8d),%r13d
+    BLSI     (%r10),%ebx
+    BLSI     0xCAFE(,%rax),%edi
+    BLSI     (%esi),%eax
+    BLSI     %r9d,%eax
+    BLSI     -0x67(%r10d,%edi,1),%eax
+    BLSI     0xF(%r10),%r15
+    BLSI     %r15,%rax
+    BLSI     %rax,%rsp
+    BLSI     (%eax),%r10
+    BLSI     (%r8d),%r13
+    BLSI     0x85(%edi,%r9d,8),%r14
+    BLSI     %r10,%r12
+    BLSI     (%r11),%r8
+    BLSI     -0x472429E0(%r15),%r9
+    BLSI     (%edi),%rdx
+    BLSI     (,%edx,4),%rbx
+    BLSI     (%ebx),%rdi
+    BLSI     0xDEAD(%r10),%rcx
+    BLSI     0x1B(%r15,%r14,8),%rdi
+    BLSI     (%rbx),%r11
+    BLSI     0xA(%r8,%r9),%rax
+    BLSMSK   %eax,%eax
+    BLSMSK   (,%r9,4),%esi
+    BLSMSK   (,%edi,2),%r15d
+    BLSMSK   (%rdi),%esp
+    BLSMSK   (%r13d),%ecx
+    BLSMSK   %r9d,%r14d
+    BLSMSK   (%rdx),%r8d
+    BLSMSK   (%esi),%r12d
+    BLSMSK   0x65F822C5(%r13,%rdx),%r11d
+    BLSMSK   -0x3(%ebx,%ecx,1),%r10d
+    BLSMSK   %r15d,%ebp
+    BLSMSK   %esi,%r13d
+    BLSMSK   (%r15),%edx
+    BLSMSK   (%r14),%r10d
+    BLSMSK   %ebp,%edi
+    BLSMSK   (%rcx,%r12),%ebx
+    BLSMSK   %r15,%rdx
+    BLSMSK   (%rax,%rcx,8),%rax
+    BLSMSK   %r9,%r15
+    BLSMSK   (%r15d),%r8
+    BLSMSK   %rax,%r15
+    BLSMSK   -0x3(%rsi),%r12
+    BLSMSK   -0x0(%rdx,%rdx),%rsi
+    BLSMSK   (%r14),%rbx
+    BLSMSK   (%r15),%rdi
+    BLSMSK   -0xDC(,%r12),%rbp
+    BLSMSK   (%ebx),%r11
+    BLSMSK   0x43B8(,%r14d),%rax
+    BLSMSK   %rdx,%r13
+    BLSMSK   %rbp,%r9
+    BLSMSK   (%eax),%rsp
+    BLSMSK   (%r14d),%r15
+    BLSR     %r15d,%r15d
+    BLSR     %eax,%r9d
+    BLSR     0x1(,%edx),%r14d
+    BLSR     %edx,%ecx
+    BLSR     (%rcx,%r14,2),%ebx
+    BLSR     0x464A(,%r9d,4),%eax
+    BLSR     (%rsi),%esp
+    BLSR     (%ecx),%esi
+    BLSR     (%edi),%esi
+    BLSR     (,%edi,2),%r10d
+    BLSR     (%rdx),%r11d
+    BLSR     (%r11),%r13d
+    BLSR     %r9d,%r8d
+    BLSR     %edi,%edx
+    BLSR     (%ebx),%eax
+    BLSR     (%rax),%edi
+    BLSR     (%r11),%r15
+    BLSR     0x3(,%ecx),%r9
+    BLSR     (%rsi),%rsp
+    BLSR     (%r13),%rax
+    BLSR     %r15,%rdx
+    BLSR     (%r14d),%r8
+    BLSR     (%r14),%rax
+    BLSR     (%r8),%rbp
+    BLSR     %rdx,%r11
+    BLSR     (%edx),%r15
+    BLSR     0x337E(,%r12d),%rbx
+    BLSR     (%rax),%rcx
+    BLSR     %rbp,%rsp
+    BLSR     %rax,%r10
+    BLSR     0x67(%r13,%r12,4),%r12
+    BLSR     (,%r13d,1),%rdi
+    LZCNT    0x1F5A(,%r8d),%r13w
+    LZCNT    %ax,%r12w
+    LZCNT    (%r9),%r10w
+    LZCNT    %r13w,%ax
+    LZCNT    -0x67(,%rax,8),%r15w
+    LZCNT    (%r13,%rdx),%di
+    LZCNT    (%rdi),%bp
+    LZCNT    (%r11),%r8w
+    LZCNT    %r15w,%si
+    LZCNT    (%r14d),%sp
+    LZCNT    (%rcx),%r9w
+    LZCNT    0x9AE7(%r11,%rbx,8),%r9w
+    LZCNT    %si,%si
+    LZCNT    (%ebx),%cx
+    LZCNT    (%r10d),%bx
+    LZCNT    %r9w,%r14w
+    LZCNT    (%r13d),%r15d
+    LZCNT    %edi,%esp
+    LZCNT    (%r14d),%r13d
+    LZCNT    (%r14),%edx
+    LZCNT    %r15d,%r11d
+    LZCNT    %eax,%eax
+    LZCNT    (%r8),%esi
+    LZCNT    %r9d,%r15d
+    LZCNT    (%r12),%r8d
+    LZCNT    %r8d,%ebp
+    LZCNT    (%r10d),%ebx
+    LZCNT    (%r12,%rcx),%edi
+    LZCNT    (%rdi),%r15d
+    LZCNT    (%edi),%r15d
+    LZCNT    %r12d,%r10d
+    LZCNT    (,%r13,1),%eax
+    LZCNT    (%r13d),%rbp
+    LZCNT    (%r10d),%r8
+    LZCNT    (%esi),%rax
+    LZCNT    %rbx,%r13
+    LZCNT    (%r9),%r15
+    LZCNT    %rdx,%rcx
+    LZCNT    (,%r13,2),%rax
+    LZCNT    (%eax),%rsi
+    LZCNT    (%r15d),%rsp
+    LZCNT    (,%r15d,4),%r11
+    LZCNT    %r15,%r12
+    LZCNT    (%rdi),%rdx
+    LZCNT    (%r12d),%r9
+    LZCNT    %r11,%r10
+    LZCNT    0xCAFE(,%ebx,8),%r13
+    LZCNT    %rax,%rax
+    TZCNT    %r10w,%r14w
+    TZCNT    0x737A(%r14),%ax
+    TZCNT    %ax,%r10w
+    TZCNT    %r15w,%si
+    TZCNT    (%r12),%r15w
+    TZCNT    (%edx),%sp
+    TZCNT    (%rax),%r13w
+    TZCNT    %r12w,%bp
+    TZCNT    0x3CAD(%r9d),%ax
+    TZCNT    0x6(%r10,%rdx),%ax
+    TZCNT    %r13w,%r11w
+    TZCNT    (%r10d,%r14d),%cx
+    TZCNT    0x4CD0AE44(%r10d,%ebx,4),%r12w
+    TZCNT    (%r15d),%r15w
+    TZCNT    (%r8),%r9w
+    TZCNT    (%r9d),%ax
+    TZCNT    (%r8),%edx
+    TZCNT    (%esi),%r11d
+    TZCNT    (%r10),%eax
+    TZCNT    -0x3D(%r14,%rdx),%r15d
+    TZCNT    (%r13),%esi
+    TZCNT    (%rdi),%r12d
+    TZCNT    (%ecx),%eax
+    TZCNT    -0x6544(%r9,%r13,8),%r13d
+    TZCNT    %eax,%esp
+    TZCNT    %r15d,%r8d
+    TZCNT    -0xF(,%ecx),%edi
+    TZCNT    (%r9),%r9d
+    TZCNT    (%rcx),%esp
+    TZCNT    (%r8,%r10),%ebp
+    TZCNT    (%rdi,%r10),%r14d
+    TZCNT    (%eax),%esi
+    TZCNT    (%edi),%r9
+    TZCNT    (%r9),%rbp
+    TZCNT    (%r15d,%ebx,4),%r15
+    TZCNT    (%r14),%r12
+    TZCNT    0x62F28A0E(,%r8),%r10
+    TZCNT    (%r8,%rsi),%r14
+    TZCNT    (%esi),%rax
+    TZCNT    %r13,%rax
+    TZCNT    0x3D6C(%r9),%r8
+    TZCNT    %rax,%r15
+    TZCNT    (,%r9,2),%rsp
+    TZCNT    (,%r12d,8),%rbx
+    TZCNT    (%rsi,%rdx),%r11
+    TZCNT    (%rcx,%r13,4),%rdi
+    TZCNT    -0xF(%r11,%rax,8),%rax
+    TZCNT    (%r8),%rax
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b18b6b9..8f1b4bd 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,42 @@
+2010-12-20  Quentin Neill  <quentin.neill@amd.com>
+
+	* i386-dis.c (REG_XOP_BMI_F3): New.
+	(PREFIX_BMI_F30F): New.
+	(dis386_twobyte): Redirect to PREFIX_BMI_F30F entry.
+	(reg_table): Add REG_XOP_BMI_F3 table.
+	(prefix_table): Add PREFIX_BMI_F30F table.
+	(x86_64_table): Add andn, bextr, and redirect to
+	REG_XOP_BMI_F3 entry.
+
+	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS, CpuBMI.
+	(cpu_flags): Add CpuBMI.
+	(opcode_modifiers): Define bitfield ModrmRegExt.
+
+	* i386-opc.h (CpuBMI) New.
+	(i386_cpu_flags): Add bit cpubmi.
+	(enum): New ModrmRegExt enum, rename VexVVVV
+	encoding from VEX.LWP to VEX.VRM, add VexOpcode
+	encoding XOP02, and add VexSources enoding
+	XOP2REVSOURCES.
+	(i386_opcode_modifier): Add modrmregext bit, increase
+	vexvvvv bit width to 3.
+
+	* i386-opc.tbl (andn): Added.
+	(andn): Added.
+	(bextr): Added.
+	(bextr): Added.
+	(blsi): Added.
+	(blsi): Added.
+	(blsmsk): Added.
+	(blsmsk): Added.
+	(blsr): Added.
+	(blsr): Added.
+	(tzcnt): Added.
+
+	* i386-init.h: Regenerated.
+
+	* i386-tbl.h: Regenerated
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f2def13..30ea470 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -599,7 +599,8 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_XOP_LWPCB,
-  REG_XOP_LWP
+  REG_XOP_LWP,
+  REG_XOP_BMI_F3
 };
 
 enum
@@ -1068,7 +1069,8 @@ enum
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,
-  PREFIX_VEX_0F3ADF
+  PREFIX_VEX_0F3ADF,
+  PREFIX_BMI_F30F
 };
 
 enum
@@ -2158,7 +2160,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "ud1",		{ XX } },
   { REG_TABLE (REG_0FBA) },
   { "btcS",		{ Ev, Gv } },
-  { "bsfS",		{ Gv, Ev } },
+  { PREFIX_TABLE (PREFIX_BMI_F30F) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",	{ Gv, Eb } },
   { "movs{wR|x}",	{ Gv, Ew } }, /* yes, there really is movsww ! */
@@ -2759,6 +2761,13 @@ static const struct dis386 reg_table[][8] = {
     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
     { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq } },
   },
+  /* REG_XOP_BMI_F3 */
+  {
+    { Bad_Opcode },
+    { "blsr",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsmsk",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsi",	{ { OP_LWP_E, 0 }, Ev } },
+  },
 };
 
 static const struct dis386 prefix_table[][4] = {
@@ -5354,6 +5363,14 @@ static const struct dis386 prefix_table[][4] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },
+
+  /* PREFIX_BMI_F30F */
+  {
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+  },
 };
 
 static const struct dis386 x86_64_table[][2] = {
@@ -7828,12 +7845,12 @@ static const struct dis386 vex_table[][256] = {
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
+    { "andn",	{ Gv, { OP_LWP_E, 0 }, Ev } },
+    { REG_TABLE (REG_XOP_BMI_F3) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "bextr",	{ Gv, Ev, { OP_LWP_E, 0 } } },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index ee06338..c4ed21f 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,6 +140,8 @@ static initializer cpu_flag_init[] =
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
   { "CPU_LWP_FLAGS",
     "CpuLWP" },
+  { "CPU_BMI_FLAGS",
+    "CpuBMI" },
   { "CPU_MOVBE_FLAGS",
     "CpuMovbe" },
   { "CPU_RDTSCP_FLAGS",
@@ -320,6 +322,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuFMA4),
   BITFIELD (CpuXOP),
   BITFIELD (CpuLWP),
+  BITFIELD (CpuBMI),
   BITFIELD (CpuLM),
   BITFIELD (CpuMovbe),
   BITFIELD (CpuEPT),
@@ -340,6 +343,7 @@ static bitfield opcode_modifiers[] =
   BITFIELD (W),
   BITFIELD (S),
   BITFIELD (Modrm),
+  BITFIELD (ModrmRegExt),
   BITFIELD (ShortForm),
   BITFIELD (Jump),
   BITFIELD (JumpDword),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index fe546b6..d5697de 100644
Binary files a/opcodes/i386-init.h and b/opcodes/i386-init.h differ
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index fe4fe97..43c0d14 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,6 +110,8 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
+  /* BMI support required */
+  CpuBMI,
   /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -186,6 +188,7 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
+      unsigned int cpubmi:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -215,6 +218,8 @@ enum
   S,
   /* insn has a modrm byte. */
   Modrm,
+  /* instruction has opcode extension in ModRM reg.  */
+  ModrmRegExt,
   /* register is in low 3 bits of opcode */
   ShortForm,
   /* special case for jump insns.  */
@@ -304,12 +309,12 @@ enum
 	For assembler, there are no difference between VEX.NDS and
 	VEX.DDS.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
-     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
+     3. VEX.VRM.  Register destination is encoded in VEX.vvvv and one
 	of the operands can access a memory location.
    */
 #define VEXXDS	1
 #define VEXNDD	2
-#define VEXLWP	3
+#define VEXVRM	3
   VexVVVV,
   /* How the VEX.W bit is used:
      0: Set by the REX.W bit.
@@ -333,14 +338,17 @@ enum
 #define XOP08		3
 #define XOP09		4
 #define XOP0A		5
+#define XOP02		6
   VexOpcode,
   /* number of VEX source operands:
      0: <= 2 source operands.
      1: 2 XOP source operands.
      2: 3 source operands.
+     3: 2 XOP source operands but order reversed.
    */
 #define XOP2SOURCES	1
 #define VEX3SOURCES	2
+#define XOP2REVSOURCES	3
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
@@ -366,6 +374,7 @@ typedef struct i386_opcode_modifier
   unsigned int w:1;
   unsigned int s:1;
   unsigned int modrm:1;
+  unsigned int modrmregext:1;
   unsigned int shortform:1;
   unsigned int jump:1;
   unsigned int jumpdword:1;
@@ -401,7 +410,7 @@ typedef struct i386_opcode_modifier
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
-  unsigned int vexvvvv:2;
+  unsigned int vexvvvv:3;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f63919e..23eb2f2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,6 +2733,19 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
 
+// BMI instructions
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32, Reg32 }
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64, Reg64 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+tzcnt,   2, 0xf30fbc, None, 2, CpuBMI, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+
 // AMD 3DNow! instructions.
 
 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5c4e7e8..72e1173 100644
Binary files a/opcodes/i386-tbl.h and b/opcodes/i386-tbl.h differ

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-20 23:25   ` Quentin Neill
@ 2010-12-21  2:30     ` Sebastian Pop
  2010-12-22  0:57       ` Quentin Neill
  2010-12-28 13:56     ` H.J. Lu
  1 sibling, 1 reply; 23+ messages in thread
From: Sebastian Pop @ 2010-12-21  2:30 UTC (permalink / raw)
  To: Quentin Neill; +Cc: binutils

Hi Quentin,
There is no need for the extra parentheses in:

+      if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+          || (i.tm.opcode_modifier.vexsources == XOP2REVSOURCES))

+              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+                  && (i.tm.opcode_modifier.vexw == VEXW0))

+              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+                  && (i.tm.opcode_modifier.vexw == VEXW0))

Then there is this change that does not appear in the ChangeLog:

-      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)

Please add something like "(VEXLWP): Renamed VEXVRM." both in the
gas/ChangeLog and in opcodes/ChangeLog.

Otherwise the patch looks good to me, but I cannot approve it.

Thanks,
Sebastian

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-21  2:30     ` Sebastian Pop
@ 2010-12-22  0:57       ` Quentin Neill
  0 siblings, 0 replies; 23+ messages in thread
From: Quentin Neill @ 2010-12-22  0:57 UTC (permalink / raw)
  To: Sebastian Pop; +Cc: binutils

[-- Attachment #1: Type: text/plain, Size: 1057 bytes --]

On Mon, Dec 20, 2010 at 5:24 PM, Sebastian Pop <sebpop@gmail.com> wrote:
> Hi Quentin,
> There is no need for the extra parentheses in:
>
> +      if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
> +          || (i.tm.opcode_modifier.vexsources == XOP2REVSOURCES))
>
> +              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
> +                  && (i.tm.opcode_modifier.vexw == VEXW0))
>
> +              if ((i.tm.opcode_modifier.vexsources == XOP2SOURCES)
> +                  && (i.tm.opcode_modifier.vexw == VEXW0))
>
> Then there is this change that does not appear in the ChangeLog:
>
> -      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
> +      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)
>
> Please add something like "(VEXLWP): Renamed VEXVRM." both in the
> gas/ChangeLog and in opcodes/ChangeLog.
>
> Otherwise the patch looks good to me, but I cannot approve it.
>
> Thanks,
> Sebastian

Fixed as recommended.  Passes "make -k check RUNTESTFLAGS=i386.exp".

Okay to commit?
-- 
Quentin

[-- Attachment #2: 7039_bdver2_bmi.diff.txt --]
[-- Type: text/plain, Size: 59198 bytes --]

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 50216fd..4d1e926 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2010-12-21  Quentin Neill  <quentin.neill@amd.com>
+
+	* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
+	(build_modrm_byte): Add BMI instruction encoding.
+	VEXLWP renamed VEXVRM.
+
+	* doc/c-i386.texi (i386-BMI): New section.
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* config/tc-mips.c (insn_uses_reg): Handle the new flags
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 9c33cf9..7371f8f 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -715,6 +715,8 @@ static const arch_entry cpu_arch[] =
     CPU_SSE4A_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
     CPU_ABM_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
+    CPU_BMI_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF
@@ -5550,7 +5552,8 @@ build_modrm_byte (void)
       else
 	mem = ~0;
 
-      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES
+          || i.tm.opcode_modifier.vexsources == XOP2REVSOURCES)
 	{
 	  if (operand_type_check (i.types[0], imm))
 	    i.vex.register_specifier = NULL;
@@ -5558,7 +5561,8 @@ build_modrm_byte (void)
 	    {
 	      /* VEX.vvvv encodes one of the sources when the first
 		 operand is not an immediate.  */
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if (i.tm.opcode_modifier.vexsources == XOP2SOURCES
+                  && i.tm.opcode_modifier.vexw == VEXW0)
 		i.vex.register_specifier = i.op[0].regs;
 	      else
 		i.vex.register_specifier = i.op[1].regs;
@@ -5575,7 +5579,8 @@ build_modrm_byte (void)
 	    {
 	      i.rm.mode = 3;
 
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if (i.tm.opcode_modifier.vexsources == XOP2SOURCES
+                  && i.tm.opcode_modifier.vexw == VEXW0)
 		i.rm.regmem = i.op[1].regs->reg_num;
 	      else
 		i.rm.regmem = i.op[0].regs->reg_num;
@@ -5584,17 +5589,32 @@ build_modrm_byte (void)
 		i.rex |= REX_B;
 	    }
 	}
-      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)
 	{
-	  i.vex.register_specifier = i.op[2].regs;
+	  unsigned int regspec_op = MAX_OPERANDS;
+	  unsigned int regmem_op = MAX_OPERANDS; 
+	  if (i.tm.opcode_modifier.modrmregext)
+	    {
+	      i.rm.reg = i.tm.extension_opcode;
+	      regspec_op = 1;
+	      regmem_op = 0;
+	    }
+	  else
+	    {
+	      regspec_op = 2;
+	      regmem_op = 1;
+	    }
+
+	  i.vex.register_specifier = i.op[regspec_op].regs;
 	  if (!i.mem_operands)
 	    {
 	      i.rm.mode = 3;
-	      i.rm.regmem = i.op[1].regs->reg_num;
-	      if ((i.op[1].regs->reg_flags & RegRex) != 0)
+	      i.rm.regmem = i.op[regmem_op].regs->reg_num;
+	      if ((i.op[regmem_op].regs->reg_flags & RegRex) != 0)
 		i.rex |= REX_B;
 	    }
 	}
+
       /* Fill in i.rm.reg or i.rm.regmem field with register operand
 	 (if any) based on i.tm.extension_opcode.  Again, we must be
 	 careful to make sure that segment/control/debug/test/MMX
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1c6175b..fd315b0 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,6 +35,7 @@ extending the Intel architecture to 64-bits.
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-LWP::                    AMD's Lightweight Profiling Instructions
+* i386-BMI::                    Bit Manipulation Instructions
 * i386-16bit::                  Writing 16-bit Code
 * i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
@@ -842,6 +843,20 @@ For detailed information on the LWP instruction set, see the
 @cite{AMD Lightweight Profiling Specification} available at
 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
 
+@node i386-BMI
+@section Bit Manipulation Instructions
+
+@cindex BMI, i386
+@cindex BMI, x86-64
+
+@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
+
+BMI instructions provide several instructions implementing individual
+bit manipulation operations such as isolation, masking, setting, or
+resetting.  
+
+@c Need to add a specification citation here.
+
 @node i386-16bit
 @section Writing 16-bit Code
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0cf93d6..99e8ee8 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,19 @@
+2010-12-21  Quentin Neill  <quentin.neill@amd.com>
+
+	* gas/i386/i386.exp: Run bmi and x86-64-bmi.
+	* gas/i386/bmi.d: New.
+	* gas/i386/bmi.s: New.
+	* gas/i386/x86-64-bmi.d: New.
+	* gas/i386/x86-64-bmi.s: New.
+	* gas/i386/arch-10.s: Add a BMI instruction.
+	* gas/i386/x86-64-arch-2.s: Likewise.
+	* gas/i386/arch-10.d: Add bmi flag and BMI instruction pattern.
+	* gas/i386/x86-64-arch-2.d: Likewise.
+	* gas/i386/arch-10-1.l: Add BMI instruction pattern.
+	* gas/i386/arch-10-2.l: Likewise.
+	* gas/i386/arch-10-3.l: Likewise.
+	* gas/i386/arch-10-4.l: Likewise.
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d,
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 0b78958..95f4425 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -29,6 +29,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -96,5 +97,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index d9e1b51..3e9d68f 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -28,6 +28,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -95,5 +96,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 75c07ec..7183ea0 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -21,6 +21,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -91,5 +92,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 3c40045..7cd68a3 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -19,6 +19,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -89,5 +90,7 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# BMI
+[ 	]*62[ 	]+blsr %ecx,%ebx
+[ 	]*63[ 	]+\# nop
+[ 	]*64[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 3efd52d..6e40abd 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: i386 arch 10
 
@@ -36,5 +36,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
 #pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index d0fb12b..7c669eb 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -58,5 +58,7 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx
 # nop
 nopl (%eax)
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
new file mode 100644
index 0000000..1f89b7c
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.d
@@ -0,0 +1,153 @@
+#objdump: -dw
+#name: i386 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 ff       	andn   %edi,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 70 f2 0c fa    	andn   \(%edx,%edi,8\),%ecx,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c3       	andn   %ebx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 14 9b    	andn   \(%ebx,%ebx,4\),%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 b1 dc 36 00 00 	andn   0x36dc\(%ecx\),%edi,%esi
+[ 	]*[a-f0-9]+:	c4 e2 48 f2 1b       	andn   \(%ebx\),%esi,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f8       	andn   %eax,%ebx,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 c1       	andn   %ecx,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 a4 5e 86 a9 9d ae 	andn   -0x5162567a\(%esi,%ebx,2\),%edx,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 2e       	andn   \(%esi\),%edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c2       	andn   %edx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 d6       	andn   %esi,%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 be 53 21 ff ff 	andn   -0xdead\(%esi\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 74 19 0a 	andn   0xa\(%ecx,%ebx,1\),%esp,%esi
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 00       	andn   \(%eax\),%edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 7c 13 ce 	andn   -0x32\(%ebx,%edx,1\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 3b       	bextr  %eax,\(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 31       	bextr  %edi,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 58 f7 cf       	bextr  %esp,%edi,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 c1       	bextr  %ebp,%ecx,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 f8       	bextr  %ebx,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 d3       	bextr  %esi,%ebx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 68 f7 04 07    	bextr  %edx,\(%edi,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 2f       	bextr  %edi,\(%edi\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f7 e6       	bextr  %ecx,%esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 18       	bextr  %edi,\(%eax\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 05 00 00 00 00 	bextr  %eax,0x0\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 22       	bextr  %ebp,\(%edx\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 2c 85 0f a9 00 00 	bextr  %esi,0xa90f\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 7c 03 03 	bextr  %ebx,0x3\(%ebx,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 b9 ff ff ff 3f 	bextr  %edi,0x3fffffff\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 12    	bextr  %eax,\(%edx,%edx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 df       	blsi   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1b       	blsi   \(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 de       	blsi   %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 da       	blsi   %edx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 1f       	blsi   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 59 08    	blsi   0x8\(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1a       	blsi   \(%edx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 19       	blsi   \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 dd       	blsi   %ebp,%esp
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 1c 19    	blsi   \(%ecx,%ebx,1\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 1c 4d 03 00 00 00 	blsi   0x3\(,%ecx,2\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1c 02    	blsi   \(%edx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 71    	blsi   \(%ecx,%esi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%eax\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 d2       	blsmsk %edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d7       	blsmsk %edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 d5       	blsmsk %ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 d3       	blsmsk %ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 17       	blsmsk \(%edi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 14 85 00 00 00 00 	blsmsk 0x0\(,%eax,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d4       	blsmsk %esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 13       	blsmsk \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 d3    	blsmsk \(%ebx,%edx,8\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 d6       	blsmsk %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 94 7f af e6 3d a1 	blsmsk -0x5ec21951\(%edi,%edi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 48    	blsmsk \(%eax,%ecx,2\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 1b    	blsmsk \(%ebx,%ebx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 14 83    	blsmsk \(%ebx,%eax,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 8c 92 fe ca 00 00 	blsr   0xcafe\(%edx,%edx,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cf       	blsr   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 0c cd 00 00 00 00 	blsr   0x0\(,%ecx,8\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 c8       	blsr   %eax,%edx
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 0e       	blsr   \(%esi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 9d 51 35 b0 66 	blsr   0x66b03551\(,%ebx,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 0c 85 0a ff ff ff 	blsr   -0xf6\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 ce       	blsr   %esi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0b       	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 8c 7b 3a f2 00 00 	blsr   0xf23a\(%ebx,%edi,2\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 09       	blsr   \(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0c 05 05 00 00 00 	blsr   0x5\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cd       	blsr   %ebp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 8c 03 c3 41 00 00 	blsr   0x41c3\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 5d 03 00 00 00 	blsr   0x3\(,%ebx,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 49 5a    	blsr   0x5a\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	66 f3 0f bd 38       	lzcnt  \(%eax\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd e7       	lzcnt  %di,%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bd 06       	lzcnt  \(%esi\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 cd 00 00 00 00 	lzcnt  0x0\(,%ecx,8\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fc       	lzcnt  %sp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 35 09 60 ff ff 	lzcnt  -0x9ff7\(,%esi,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd bc cb 4d 6e 00 00 	lzcnt  0x6e4d\(%ebx,%ecx,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2a       	lzcnt  \(%edx\),%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bd c9       	lzcnt  %cx,%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bd dd       	lzcnt  %bp,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	66 f3 0f bd 04 05 00 00 00 00 	lzcnt  0x0\(,%eax,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd f8       	lzcnt  %ax,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd db       	lzcnt  %bx,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fa       	lzcnt  %dx,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 1f       	lzcnt  \(%edi\),%bx
+[ 	]*[a-f0-9]+:	f3 0f bd db          	lzcnt  %ebx,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd f9          	lzcnt  %ecx,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 14 09       	lzcnt  \(%ecx,%ecx,1\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd cf          	lzcnt  %edi,%ecx
+[ 	]*[a-f0-9]+:	f3 0f bd fc          	lzcnt  %esp,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 34 7d 00 00 00 00 	lzcnt  0x0\(,%edi,2\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bd 03          	lzcnt  \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bd 3c 43       	lzcnt  \(%ebx,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 1f          	lzcnt  \(%edi\),%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd ed          	lzcnt  %ebp,%ebp
+[ 	]*[a-f0-9]+:	f3 0f bd a3 ad de 00 00 	lzcnt  0xdead\(%ebx\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bd c6          	lzcnt  %esi,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd bc 00 05 63 00 00 	lzcnt  0x6305\(%eax,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd bc 07 74 8f ff ff 	lzcnt  -0x708c\(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 06          	lzcnt  \(%esi\),%eax
+[ 	]*[a-f0-9]+:	66 f3 0f bc eb       	tzcnt  %bx,%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bc c7       	tzcnt  %di,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc fd       	tzcnt  %bp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 14 16    	tzcnt  \(%esi,%edx,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0f       	tzcnt  \(%edi\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0a       	tzcnt  \(%edx\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 24 8d 00 00 00 00 	tzcnt  0x0\(,%ecx,4\),%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bc 31       	tzcnt  \(%ecx\),%si
+[ 	]*[a-f0-9]+:	66 f3 0f bc 03       	tzcnt  \(%ebx\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 3c c7    	tzcnt  \(%edi,%eax,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 1c 3b    	tzcnt  \(%ebx,%edi,1\),%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc c1       	tzcnt  %cx,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc b9 63 27 ff ff 	tzcnt  -0xd89d\(%ecx\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	f3 0f bc f8          	tzcnt  %eax,%edi
+[ 	]*[a-f0-9]+:	f3 0f bc f7          	tzcnt  %edi,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 44 3b 61    	tzcnt  0x61\(%ebx,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc de          	tzcnt  %esi,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 2a          	tzcnt  \(%edx\),%ebp
+[ 	]*[a-f0-9]+:	f3 0f bc 16          	tzcnt  \(%esi\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bc 0c 0f       	tzcnt  \(%edi,%ecx,1\),%ecx
+[ 	]*[a-f0-9]+:	f3 0f bc f5          	tzcnt  %ebp,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 07          	tzcnt  \(%edi\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 07       	tzcnt  \(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 00       	tzcnt  \(%eax,%eax,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc 00          	tzcnt  \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 45 bf ff ff ff 	tzcnt  -0x41\(,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 1d 01 00 00 c0 	tzcnt  -0x3fffffff\(,%ebx,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc c3          	tzcnt  %ebx,%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3b          	tzcnt  \(%ebx\),%edi
+
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
new file mode 100644
index 0000000..f3f9c38
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.s
@@ -0,0 +1,151 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %edi,%eax,%edi
+    ANDN     (%edx,%edi,8),%ecx,%ecx
+    ANDN     %ebx,%esp,%eax
+    ANDN     (%ebx,%ebx,4),%ebp,%edx
+    ANDN     0x36DC(%ecx),%edi,%esi
+    ANDN     (%ebx),%esi,%ebx
+    ANDN     %eax,%ebx,%edi
+    ANDN     %ecx,%eax,%eax
+    ANDN     -0x5162567A(%esi,%ebx,2),%edx,%esp
+    ANDN     (%esi),%edx,%ebp
+    ANDN     %edx,%esp,%eax
+    ANDN     %esi,%ebp,%edx
+    ANDN     -0xDEAD(%esi),%edi,%edi
+    ANDN     0xA(%ecx,%ebx),%esp,%esi
+    ANDN     (%eax),%edi,%eax
+    ANDN     -0x32(%ebx,%edx),%edi,%edi
+    BEXTR    %eax,(%ebx),%edi
+    BEXTR    %edi,(%ecx),%esi
+    BEXTR    %esp,%edi,%ecx
+    BEXTR    %ebp,%ecx,%eax
+    BEXTR    %ebx,%eax,%edi
+    BEXTR    %esi,%ebx,%edx
+    BEXTR    %edx,(%edi,%eax),%eax
+    BEXTR    %edi,(%edi),%ebp
+    BEXTR    %ecx,%esi,%esp
+    BEXTR    %edi,0x0(%eax),%ebx
+    BEXTR    %eax,(,%eax,1),%eax
+    BEXTR    %ebp,(%edx),%esp
+    BEXTR    %esi,0xA90F(,%eax,4),%ebp
+    BEXTR    %ebx,0x3(%ebx,%eax),%edi
+    BEXTR    %edi,0x3FFFFFFF(%ecx),%edi
+    BEXTR    %eax,(%edx,%edx),%eax
+    BLSI     %edi,%eax
+    BLSI     %eax,%edi
+    BLSI     (%ebx),%edi
+    BLSI     %esi,%esp
+    BLSI     %edx,%edx
+    BLSI     (%edi),%esi
+    BLSI     0x8(%ecx),%ebx
+    BLSI     (%edx),%eax
+    BLSI     (%ecx),%eax
+    BLSI     %ebp,%esp
+    BLSI     (%ecx,%ebx),%ebp
+    BLSI     0x3(,%ecx,2),%ecx
+    BLSI     (%edx,%eax),%eax
+    BLSI     (%ecx,%esi,2),%edi
+    BLSI     %eax,%edi
+    BLSI     (%eax),%eax
+    BLSMSK   %edx,%ebp
+    BLSMSK   %edi,%edi
+    BLSMSK   %eax,%eax
+    BLSMSK   %ebp,%edx
+    BLSMSK   %ebx,%esi
+    BLSMSK   (%edi),%ecx
+    BLSMSK   (%ecx),%ebx
+    BLSMSK   (,%eax,4),%esp
+    BLSMSK   %esp,%eax
+    BLSMSK   (%ebx),%eax
+    BLSMSK   (%ebx,%edx,8),%eax
+    BLSMSK   %esi,%esp
+    BLSMSK   -0x5EC21951(%edi,%edi,2),%edi
+    BLSMSK   (%eax,%ecx,2),%eax
+    BLSMSK   (%ebx,%ebx),%eax
+    BLSMSK   (%ebx,%eax,4),%edi
+    BLSR     0xCAFE(%edx,%edx,4),%esp
+    BLSR     %edi,%eax
+    BLSR     (,%ecx,8),%esi
+    BLSR     %eax,%edx
+    BLSR     (%esi),%ecx
+    BLSR     0x66B03551(,%ebx,4),%edi
+    BLSR     -0xF6(,%eax,4),%ebp
+    BLSR     %esi,%edi
+    BLSR     (%ebx),%eax
+    BLSR     0xF23A(%ebx,%edi,2),%ebx
+    BLSR     (%ecx),%edi
+    BLSR     0x5(,%eax),%eax
+    BLSR     %ebp,%eax
+    BLSR     0x41C3(%ebx,%eax),%eax
+    BLSR     0x3(,%ebx,2),%edi
+    BLSR     0x5A(%ecx),%edi
+    LZCNT    (%eax),%di
+    LZCNT    %di,%sp
+    LZCNT    (%esi),%ax
+    LZCNT    (,%ecx,8),%dx
+    LZCNT    %sp,%di
+    LZCNT    -0x9FF7(,%esi),%dx
+    LZCNT    0x6E4D(%ebx,%ecx,8),%di
+    LZCNT    (%edx),%bp
+    LZCNT    %cx,%cx
+    LZCNT    %bp,%bx
+    LZCNT    %si,%si
+    LZCNT    (,%eax,1),%ax
+    LZCNT    %ax,%di
+    LZCNT    %bx,%bx
+    LZCNT    %dx,%di
+    LZCNT    (%edi),%bx
+    LZCNT    %ebx,%ebx
+    LZCNT    %ecx,%edi
+    LZCNT    (%ecx,%ecx),%edx
+    LZCNT    %eax,%eax
+    LZCNT    %edi,%ecx
+    LZCNT    %esp,%edi
+    LZCNT    (,%edi,2),%esi
+    LZCNT    (%ebx),%eax
+    LZCNT    (%ebx,%eax,2),%edi
+    LZCNT    (%edi),%ebx
+    LZCNT    %ebp,%ebp
+    LZCNT    0xDEAD(%ebx),%esp
+    LZCNT    %esi,%eax
+    LZCNT    0x6305(%eax,%eax,1),%edi
+    LZCNT    -0x708C(%edi,%eax),%edi
+    LZCNT    (%esi),%eax
+    TZCNT    %bx,%bp
+    TZCNT    %di,%ax
+    TZCNT    %bp,%di
+    TZCNT    (%esi,%edx,1),%dx
+    TZCNT    (%edi),%cx
+    TZCNT    (%edx),%cx
+    TZCNT    %ax,%bx
+    TZCNT    (,%ecx,4),%sp
+    TZCNT    (%ecx),%si
+    TZCNT    (%ebx),%ax
+    TZCNT    (%edi,%eax,8),%di
+    TZCNT    (%ebx,%edi),%bx
+    TZCNT    %cx,%ax
+    TZCNT    -0xD89D(%ecx),%di
+    TZCNT    %bp,%ax
+    TZCNT    %bp,%ax
+    TZCNT    %eax,%edi
+    TZCNT    %edi,%esi
+    TZCNT    0x61(%ebx,%edi),%eax
+    TZCNT    %esi,%ebx
+    TZCNT    (%edx),%ebp
+    TZCNT    (%esi),%edx
+    TZCNT    (%edi,%ecx),%ecx
+    TZCNT    %ebp,%esi
+    TZCNT    (%edi),%eax
+    TZCNT    (%edi,%eax,1),%edi
+    TZCNT    (%eax,%eax),%esp
+    TZCNT    (%eax),%eax
+    TZCNT    -0x41(,%eax,2),%edi
+    TZCNT    -0x3FFFFFFF(,%ebx),%esp
+    TZCNT    %ebx,%eax
+    TZCNT    (%ebx),%edi
+
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a966d7..01a3ecb 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
+    run_dump_test "bmi"
     run_dump_test "f16c"
     run_dump_test "f16c-intel"
     run_dump_test "fsgs"
@@ -372,6 +373,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
+    run_dump_test "x86-64-bmi"
     run_dump_test "x86-64-f16c"
     run_dump_test "x86-64-f16c-intel"
     run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 9cd1306..ac09453 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: x86-64 arch 2
 
@@ -36,4 +36,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index ddc0d40..962f15e 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,3 +58,5 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
new file mode 100644
index 0000000..180e40f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.d
@@ -0,0 +1,265 @@
+#objdump: -dw
+#name: x86-64 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 c2 00 f2 c0       	andn   %r8d,%r15d,%eax
+[ 	]*[a-f0-9]+:	c4 62 78 f2 14 0e    	andn   \(%rsi,%rcx,1\),%eax,%r10d
+[ 	]*[a-f0-9]+:	67 c4 c2 48 f2 2e    	andn   \(%r14d\),%esi,%ebp
+[ 	]*[a-f0-9]+:	c4 42 40 f2 7d 00    	andn   0x0\(%r13\),%edi,%r15d
+[ 	]*[a-f0-9]+:	c4 42 18 f2 fe       	andn   %r14d,%r12d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 08 f2 3c 50 	andn   \(%r8d,%r10d,2\),%r14d,%edi
+[ 	]*[a-f0-9]+:	67 c4 42 28 f2 29    	andn   \(%r9d\),%r10d,%r13d
+[ 	]*[a-f0-9]+:	67 c4 22 70 f2 0c bd 00 00 00 00 	andn   0x0\(,%r15d,4\),%ecx,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 38 f2 24 85 00 00 00 00 	andn   0x0\(,%r8,4\),%r8d,%esp
+[ 	]*[a-f0-9]+:	c4 62 38 f2 24 07    	andn   \(%rdi,%rax,1\),%r8d,%r12d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f2 44 1d 00 	andn   0x0\(%r13d,%ebx,1\),%r11d,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f2       	andn   %edx,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 c2 58 f2 11       	andn   \(%r9\),%esp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 00 f2 0f       	andn   \(%rdi\),%r15d,%ecx
+[ 	]*[a-f0-9]+:	67 c4 62 50 f2 37    	andn   \(%edi\),%ebp,%r14d
+[ 	]*[a-f0-9]+:	c4 a2 28 f2 84 83 fa b5 bb c6 	andn   -0x39444a06\(%rbx,%r8,4\),%r10d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f2 02    	andn   \(%r10d\),%rax,%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f2 16    	andn   \(%r14d\),%r15,%rdx
+[ 	]*[a-f0-9]+:	c4 02 d8 f2 bc 0f 93 5b 00 00 	andn   0x5b93\(%r15,%r9,1\),%rsp,%r15
+[ 	]*[a-f0-9]+:	c4 42 a0 f2 09       	andn   \(%r9\),%r11,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f2 3c 45 00 00 00 00 	andn   0x0\(,%eax,2\),%r15,%rdi
+[ 	]*[a-f0-9]+:	c4 62 c8 f2 dd       	andn   %rbp,%rsi,%r11
+[ 	]*[a-f0-9]+:	c4 42 e0 f2 45 00    	andn   0x0\(%r13\),%rbx,%r8
+[ 	]*[a-f0-9]+:	c4 62 c0 f2 d0       	andn   %rax,%rdi,%r10
+[ 	]*[a-f0-9]+:	c4 c2 98 f2 e4       	andn   %r12,%r12,%rsp
+[ 	]*[a-f0-9]+:	67 c4 62 a8 f2 3e    	andn   \(%esi\),%r10,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f2 3a    	andn   \(%edx\),%rax,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f2 37    	andn   \(%r15d\),%r8,%rsi
+[ 	]*[a-f0-9]+:	67 c4 42 80 f2 20    	andn   \(%r8d\),%r15,%r12
+[ 	]*[a-f0-9]+:	c4 c2 80 f2 ef       	andn   %r15,%r15,%rbp
+[ 	]*[a-f0-9]+:	c4 a2 d0 f2 0c e5 00 00 00 00 	andn   0x0\(,%r12,8\),%rbp,%rcx
+[ 	]*[a-f0-9]+:	c4 62 f0 f2 2a       	andn   \(%rdx\),%rcx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 00 f7 c0       	bextr  %r15d,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 42 78 f7 fa       	bextr  %eax,%r10d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 68 f7 0c cf 	bextr  %edx,\(%r15d,%r9d,8\),%ecx
+[ 	]*[a-f0-9]+:	c4 02 50 f7 54 3d 00 	bextr  %ebp,0x0\(%r13,%r15,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 20 f7 ef       	bextr  %r11d,%r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 82 00 f7 64 35 00 	bextr  %r15d,0x0\(%r13,%r14,1\),%esp
+[ 	]*[a-f0-9]+:	67 c4 02 30 f7 84 c3 ad de 00 00 	bextr  %r9d,0xdead\(%r11d,%r8d,8\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f7 44 04 01 	bextr  %r11d,0x1\(%r12d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 42 28 f7 76 f4 	bextr  %r10d,-0xc\(%r14d\),%r14d
+[ 	]*[a-f0-9]+:	c4 62 78 f7 18       	bextr  %eax,\(%rax\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 c2 60 f7 14 24 	bextr  %ebx,\(%r12d\),%edx
+[ 	]*[a-f0-9]+:	67 c4 62 48 f7 28    	bextr  %esi,\(%eax\),%r13d
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 dd       	bextr  %eax,%ebp,%ebx
+[ 	]*[a-f0-9]+:	c4 c2 78 f7 04 24    	bextr  %eax,\(%r12\),%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 50 f7 04 02 	bextr  %ebp,\(%r10d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 e2 10 f7 44 03 99 	bextr  %r13d,-0x67\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 82 a8 f7 84 7b fe ca 00 00 	bextr  %r10,0xcafe\(%r11,%r15,2\),%rax
+[ 	]*[a-f0-9]+:	c4 42 a8 f7 b1 fe ca 00 00 	bextr  %r10,0xcafe\(%r9\),%r14
+[ 	]*[a-f0-9]+:	c4 62 f8 f7 ff       	bextr  %rax,%rdi,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f7 2a    	bextr  %rax,\(%edx\),%r13
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 17       	bextr  %rax,\(%r15\),%r10
+[ 	]*[a-f0-9]+:	c4 c2 80 f7 ea       	bextr  %r15,%r10,%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 f8 f7 3e    	bextr  %rax,\(%esi\),%rdi
+[ 	]*[a-f0-9]+:	c4 42 98 f7 e1       	bextr  %r12,%r9,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f7 dd       	bextr  %r8,%r13,%rbx
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 24 24    	bextr  %rax,\(%r12\),%rsp
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 5d 00    	bextr  %rax,0x0\(%r13\),%r11
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 30       	bextr  %rax,\(%r8\),%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f0 f7 d6       	bextr  %rcx,%rsi,%rdx
+[ 	]*[a-f0-9]+:	67 c4 02 b8 f7 7c 0a 03 	bextr  %r8,0x3\(%r10d,%r9d,1\),%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 07    	bextr  %rax,\(%r15d\),%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 08    	bextr  %rax,\(%r8d\),%rcx
+[ 	]*[a-f0-9]+:	67 c4 a2 48 f3 1c 7d f3 ff ff ff 	blsi   -0xd\(,%r15d,2\),%esi
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 df       	blsi   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d8       	blsi   %eax,%eax
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 19       	blsi   \(%r9\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 dd       	blsi   %ebp,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 68 f3 1c 4d 05 00 00 00 	blsi   0x5\(,%r9,2\),%edx
+[ 	]*[a-f0-9]+:	c4 a2 70 f3 1c 5d 96 ff ff ff 	blsi   -0x6a\(,%r11,2\),%ecx
+[ 	]*[a-f0-9]+:	67 c4 e2 50 f3 19    	blsi   \(%ecx\),%ebp
+[ 	]*[a-f0-9]+:	67 c4 e2 20 f3 1f    	blsi   \(%edi\),%r11d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 5f f9    	blsi   -0x7\(%rdi\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 10 f3 18    	blsi   \(%r8d\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 60 f3 1a       	blsi   \(%r10\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 05 fe ca 00 00 	blsi   0xcafe\(,%rax,1\),%edi
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 1e    	blsi   \(%esi\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 78 f3 d9       	blsi   %r9d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 78 f3 5c 3a 99 	blsi   -0x67\(%r10d,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 5a 0f    	blsi   0xf\(%r10\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 df       	blsi   %r15,%rax
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 d8       	blsi   %rax,%rsp
+[ 	]*[a-f0-9]+:	67 c4 e2 a8 f3 18    	blsi   \(%eax\),%r10
+[ 	]*[a-f0-9]+:	67 c4 c2 90 f3 18    	blsi   \(%r8d\),%r13
+[ 	]*[a-f0-9]+:	67 c4 a2 88 f3 9c cf 85 00 00 00 	blsi   0x85\(%edi,%r9d,8\),%r14
+[ 	]*[a-f0-9]+:	c4 c2 98 f3 da       	blsi   %r10,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f3 1b       	blsi   \(%r11\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 b0 f3 9f 20 d6 db b8 	blsi   -0x472429e0\(%r15\),%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 e8 f3 1f    	blsi   \(%edi\),%rdx
+[ 	]*[a-f0-9]+:	67 c4 e2 e0 f3 1c 95 00 00 00 00 	blsi   0x0\(,%edx,4\),%rbx
+[ 	]*[a-f0-9]+:	67 c4 e2 c0 f3 1b    	blsi   \(%ebx\),%rdi
+[ 	]*[a-f0-9]+:	c4 c2 f0 f3 9a ad de 00 00 	blsi   0xdead\(%r10\),%rcx
+[ 	]*[a-f0-9]+:	c4 82 c0 f3 5c f7 1b 	blsi   0x1b\(%r15,%r14,8\),%rdi
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 1b       	blsi   \(%rbx\),%r11
+[ 	]*[a-f0-9]+:	c4 82 f8 f3 5c 08 0a 	blsi   0xa\(%r8,%r9,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 a2 48 f3 14 8d 00 00 00 00 	blsmsk 0x0\(,%r9,4\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 00 f3 14 7d 00 00 00 00 	blsmsk 0x0\(,%edi,2\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 17       	blsmsk \(%rdi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 c2 70 f3 55 00 	blsmsk 0x0\(%r13d\),%ecx
+[ 	]*[a-f0-9]+:	c4 c2 08 f3 d1       	blsmsk %r9d,%r14d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 12       	blsmsk \(%rdx\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 e2 18 f3 16    	blsmsk \(%esi\),%r12d
+[ 	]*[a-f0-9]+:	c4 c2 20 f3 94 15 c5 22 f8 65 	blsmsk 0x65f822c5\(%r13,%rdx,1\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 54 0b fd 	blsmsk -0x3\(%ebx,%ecx,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 50 f3 d7       	blsmsk %r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 10 f3 d6       	blsmsk %esi,%r13d
+[ 	]*[a-f0-9]+:	c4 c2 68 f3 17       	blsmsk \(%r15\),%edx
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 16       	blsmsk \(%r14\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d5       	blsmsk %ebp,%edi
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 14 21    	blsmsk \(%rcx,%r12,1\),%ebx
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 d7       	blsmsk %r15,%rdx
+[ 	]*[a-f0-9]+:	c4 e2 f8 f3 14 c8    	blsmsk \(%rax,%rcx,8\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 17    	blsmsk \(%r15d\),%r8
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 d0       	blsmsk %rax,%r15
+[ 	]*[a-f0-9]+:	c4 e2 98 f3 56 fd    	blsmsk -0x3\(%rsi\),%r12
+[ 	]*[a-f0-9]+:	c4 e2 c8 f3 14 12    	blsmsk \(%rdx,%rdx,1\),%rsi
+[ 	]*[a-f0-9]+:	c4 c2 e0 f3 16       	blsmsk \(%r14\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 c0 f3 17       	blsmsk \(%r15\),%rdi
+[ 	]*[a-f0-9]+:	c4 a2 d0 f3 14 25 24 ff ff ff 	blsmsk -0xdc\(,%r12,1\),%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 a0 f3 13    	blsmsk \(%ebx\),%r11
+[ 	]*[a-f0-9]+:	67 c4 a2 f8 f3 14 35 b8 43 00 00 	blsmsk 0x43b8\(,%r14d,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 90 f3 d2       	blsmsk %rdx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 b0 f3 d5       	blsmsk %rbp,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 d8 f3 10    	blsmsk \(%eax\),%rsp
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f3 16    	blsmsk \(%r14d\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 cf       	blsr   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 c8       	blsr   %eax,%r9d
+[ 	]*[a-f0-9]+:	67 c4 e2 08 f3 0c 15 01 00 00 00 	blsr   0x1\(,%edx,1\),%r14d
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 ca       	blsr   %edx,%ecx
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 0c 71    	blsr   \(%rcx,%r14,2\),%ebx
+[ 	]*[a-f0-9]+:	67 c4 a2 78 f3 0c 8d 4a 46 00 00 	blsr   0x464a\(,%r9d,4\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 0e       	blsr   \(%rsi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 09    	blsr   \(%ecx\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 0f    	blsr   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 0c 7d 00 00 00 00 	blsr   0x0\(,%edi,2\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 20 f3 0a       	blsr   \(%rdx\),%r11d
+[ 	]*[a-f0-9]+:	c4 c2 10 f3 0b       	blsr   \(%r11\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 38 f3 c9       	blsr   %r9d,%r8d
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 cf       	blsr   %edi,%edx
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 0b    	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 08       	blsr   \(%rax\),%edi
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 0b       	blsr   \(%r11\),%r15
+[ 	]*[a-f0-9]+:	67 c4 e2 b0 f3 0c 0d 03 00 00 00 	blsr   0x3\(,%ecx,1\),%r9
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 0e       	blsr   \(%rsi\),%rsp
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 4d 00    	blsr   0x0\(%r13\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 cf       	blsr   %r15,%rdx
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 0e    	blsr   \(%r14d\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 0e       	blsr   \(%r14\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 d0 f3 08       	blsr   \(%r8\),%rbp
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 ca       	blsr   %rdx,%r11
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f3 0a    	blsr   \(%edx\),%r15
+[ 	]*[a-f0-9]+:	67 c4 a2 e0 f3 0c 25 7e 33 00 00 	blsr   0x337e\(,%r12d,1\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 f0 f3 08       	blsr   \(%rax\),%rcx
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 cd       	blsr   %rbp,%rsp
+[ 	]*[a-f0-9]+:	c4 e2 a8 f3 c8       	blsr   %rax,%r10
+[ 	]*[a-f0-9]+:	c4 82 98 f3 4c a5 67 	blsr   0x67\(%r13,%r12,4\),%r12
+[ 	]*[a-f0-9]+:	67 c4 a2 c0 f3 0c 2d 00 00 00 00 	blsr   0x0\(,%r13d,1\),%rdi
+[ 	]*[a-f0-9]+:	67 66 f3 46 0f bd 2c 05 5a 1f 00 00 	lzcnt  0x1f5a\(,%r8d,1\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd e0    	lzcnt  %ax,%r12w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 11    	lzcnt  \(%r9\),%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd c5    	lzcnt  %r13w,%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 3c c5 99 ff ff ff 	lzcnt  -0x67\(,%rax,8\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd 7c 15 00 	lzcnt  0x0\(%r13,%rdx,1\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2f       	lzcnt  \(%rdi\),%bp
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 03    	lzcnt  \(%r11\),%r8w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd f7    	lzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 26 	lzcnt  \(%r14d\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 09    	lzcnt  \(%rcx\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 8c db e7 9a 00 00 	lzcnt  0x9ae7\(%r11,%rbx,8\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	67 66 f3 0f bd 0b    	lzcnt  \(%ebx\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 1a 	lzcnt  \(%r10d\),%bx
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd f1    	lzcnt  %r9w,%r14w
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 7d 00 	lzcnt  0x0\(%r13d\),%r15d
+[ 	]*[a-f0-9]+:	f3 0f bd e7          	lzcnt  %edi,%esp
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 2e    	lzcnt  \(%r14d\),%r13d
+[ 	]*[a-f0-9]+:	f3 41 0f bd 16       	lzcnt  \(%r14\),%edx
+[ 	]*[a-f0-9]+:	f3 45 0f bd df       	lzcnt  %r15d,%r11d
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 41 0f bd 30       	lzcnt  \(%r8\),%esi
+[ 	]*[a-f0-9]+:	f3 45 0f bd f9       	lzcnt  %r9d,%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd 04 24    	lzcnt  \(%r12\),%r8d
+[ 	]*[a-f0-9]+:	f3 41 0f bd e8       	lzcnt  %r8d,%ebp
+[ 	]*[a-f0-9]+:	67 f3 41 0f bd 1a    	lzcnt  \(%r10d\),%ebx
+[ 	]*[a-f0-9]+:	f3 41 0f bd 3c 0c    	lzcnt  \(%r12,%rcx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 44 0f bd 3f       	lzcnt  \(%rdi\),%r15d
+[ 	]*[a-f0-9]+:	67 f3 44 0f bd 3f    	lzcnt  \(%edi\),%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd d4       	lzcnt  %r12d,%r10d
+[ 	]*[a-f0-9]+:	f3 42 0f bd 04 2d 00 00 00 00 	lzcnt  0x0\(,%r13,1\),%eax
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 6d 00 	lzcnt  0x0\(%r13d\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 02    	lzcnt  \(%r10d\),%r8
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 06    	lzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 4c 0f bd eb       	lzcnt  %rbx,%r13
+[ 	]*[a-f0-9]+:	f3 4d 0f bd 39       	lzcnt  \(%r9\),%r15
+[ 	]*[a-f0-9]+:	f3 48 0f bd ca       	lzcnt  %rdx,%rcx
+[ 	]*[a-f0-9]+:	f3 4a 0f bd 04 6d 00 00 00 00 	lzcnt  0x0\(,%r13,2\),%rax
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 30    	lzcnt  \(%eax\),%rsi
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 27    	lzcnt  \(%r15d\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4e 0f bd 1c bd 00 00 00 00 	lzcnt  0x0\(,%r15d,4\),%r11
+[ 	]*[a-f0-9]+:	f3 4d 0f bd e7       	lzcnt  %r15,%r12
+[ 	]*[a-f0-9]+:	f3 48 0f bd 17       	lzcnt  \(%rdi\),%rdx
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 0c 24 	lzcnt  \(%r12d\),%r9
+[ 	]*[a-f0-9]+:	f3 4d 0f bd d3       	lzcnt  %r11,%r10
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bd 2c dd fe ca 00 00 	lzcnt  0xcafe\(,%ebx,8\),%r13
+[ 	]*[a-f0-9]+:	f3 48 0f bd c0       	lzcnt  %rax,%rax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc f2    	tzcnt  %r10w,%r14w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 86 7a 73 00 00 	tzcnt  0x737a\(%r14\),%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc d0    	tzcnt  %ax,%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc f7    	tzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 3c 24 	tzcnt  \(%r12\),%r15w
+[ 	]*[a-f0-9]+:	67 66 f3 0f bc 22    	tzcnt  \(%edx\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 28    	tzcnt  \(%rax\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc ec    	tzcnt  %r12w,%bp
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 81 ad 3c 00 00 	tzcnt  0x3cad\(%r9d\),%ax
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 44 12 06 	tzcnt  0x6\(%r10,%rdx,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc dd    	tzcnt  %r13w,%r11w
+[ 	]*[a-f0-9]+:	67 66 f3 43 0f bc 0c 32 	tzcnt  \(%r10d,%r14d,1\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc a4 9a 44 ae d0 4c 	tzcnt  0x4cd0ae44\(%r10d,%ebx,4\),%r12w
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc 3f 	tzcnt  \(%r15d\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 08    	tzcnt  \(%r8\),%r9w
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 01 	tzcnt  \(%r9d\),%ax
+[ 	]*[a-f0-9]+:	f3 41 0f bc 10       	tzcnt  \(%r8\),%edx
+[ 	]*[a-f0-9]+:	67 f3 44 0f bc 1e    	tzcnt  \(%esi\),%r11d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 02       	tzcnt  \(%r10\),%eax
+[ 	]*[a-f0-9]+:	f3 45 0f bc 7c 16 c3 	tzcnt  -0x3d\(%r14,%rdx,1\),%r15d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 75 00    	tzcnt  0x0\(%r13\),%esi
+[ 	]*[a-f0-9]+:	f3 44 0f bc 27       	tzcnt  \(%rdi\),%r12d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 01       	tzcnt  \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	f3 47 0f bc ac e9 bc 9a ff ff 	tzcnt  -0x6544\(%r9,%r13,8\),%r13d
+[ 	]*[a-f0-9]+:	f3 0f bc e0          	tzcnt  %eax,%esp
+[ 	]*[a-f0-9]+:	f3 45 0f bc c7       	tzcnt  %r15d,%r8d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 3c 0d f1 ff ff ff 	tzcnt  -0xf\(,%ecx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 45 0f bc 09       	tzcnt  \(%r9\),%r9d
+[ 	]*[a-f0-9]+:	f3 0f bc 21          	tzcnt  \(%rcx\),%esp
+[ 	]*[a-f0-9]+:	f3 43 0f bc 2c 10    	tzcnt  \(%r8,%r10,1\),%ebp
+[ 	]*[a-f0-9]+:	f3 46 0f bc 34 17    	tzcnt  \(%rdi,%r10,1\),%r14d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 30       	tzcnt  \(%eax\),%esi
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bc 0f    	tzcnt  \(%edi\),%r9
+[ 	]*[a-f0-9]+:	f3 49 0f bc 29       	tzcnt  \(%r9\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bc 3c 9f 	tzcnt  \(%r15d,%ebx,4\),%r15
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 26       	tzcnt  \(%r14\),%r12
+[ 	]*[a-f0-9]+:	f3 4e 0f bc 14 05 0e 8a f2 62 	tzcnt  0x62f28a0e\(,%r8,1\),%r10
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 34 30    	tzcnt  \(%r8,%rsi,1\),%r14
+[ 	]*[a-f0-9]+:	67 f3 48 0f bc 06    	tzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc c5       	tzcnt  %r13,%rax
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 81 6c 3d 00 00 	tzcnt  0x3d6c\(%r9\),%r8
+[ 	]*[a-f0-9]+:	f3 4c 0f bc f8       	tzcnt  %rax,%r15
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 24 4d 00 00 00 00 	tzcnt  0x0\(,%r9,2\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4a 0f bc 1c e5 00 00 00 00 	tzcnt  0x0\(,%r12d,8\),%rbx
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 1c 16    	tzcnt  \(%rsi,%rdx,1\),%r11
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 3c a9    	tzcnt  \(%rcx,%r13,4\),%rdi
+[ 	]*[a-f0-9]+:	f3 49 0f bc 44 c3 f1 	tzcnt  -0xf\(%r11,%rax,8\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc 00       	tzcnt  \(%r8\),%rax
+
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
new file mode 100644
index 0000000..e4059ec
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.s
@@ -0,0 +1,263 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %eax,%r15d,%eax
+    ANDN     (%rsi,%rcx),%eax,%r10d
+    ANDN     (%r14d),%esi,%ebp
+    ANDN     (%r13),%edi,%r15d
+    ANDN     %esi,%r12d,%r15d
+    ANDN     (%r8d,%r10d,2),%r14d,%edi
+    ANDN     (%r9d),%r10d,%r13d
+    ANDN     (,%r15d,4),%ecx,%r9d
+    ANDN     (,%r8,4),%r8d,%esp
+    ANDN     (%rdi,%rax),%r8d,%r12d
+    ANDN     (%r13d,%ebx),%r11d,%eax
+    ANDN     %edx,%ebx,%esi
+    ANDN     (%r9),%esp,%edx
+    ANDN     (%rdi),%r15d,%ecx
+    ANDN     (%edi),%ebp,%r14d
+    ANDN     -0x39444A06(%rbx,%r8,4),%r10d,%eax
+    ANDN     (%r10d),%rax,%rax
+    ANDN     (%r14d),%r15,%rdx
+    ANDN     0x5B93(%r15,%r9),%rsp,%r15
+    ANDN     (%r9),%r11,%r9
+    ANDN     (,%eax,2),%r15,%rdi
+    ANDN     %rbp,%rsi,%r11
+    ANDN     (%r13),%rbx,%r8
+    ANDN     %rax,%rdi,%r10
+    ANDN     %rsp,%r12,%rsp
+    ANDN     (%esi),%r10,%r15
+    ANDN     (%edx),%rax,%r15
+    ANDN     (%r15d),%r8,%rsi
+    ANDN     (%r8d),%r15,%r12
+    ANDN     %rdi,%r15,%rbp
+    ANDN     (,%r12,8),%rbp,%rcx
+    ANDN     (%rdx),%rcx,%r13
+    BEXTR    %r15d,%eax,%eax
+    BEXTR    %eax,%r10d,%r15d
+    BEXTR    %edx,(%r15d,%r9d,8),%ecx
+    BEXTR    %ebp,(%r13,%r15),%r10d
+    BEXTR    %r11d,%r15d,%ebp
+    BEXTR    %r15d,(%r13,%r14),%esp
+    BEXTR    %r9d,0xDEAD(%r11d,%r8d,8),%r8d
+    BEXTR    %r11d,0x1(%r12d,%eax),%eax
+    BEXTR    %r10d,-0xC(%r14d),%r14d
+    BEXTR    %eax,(%rax),%r11d
+    BEXTR    %ebx,(%r12d),%edx
+    BEXTR    %esi,(%eax),%r13d
+    BEXTR    %eax,%ebp,%ebx
+    BEXTR    %eax,(%r12),%eax
+    BEXTR    %ebp,(%r10d,%eax),%eax
+    BEXTR    %r13d,-0x67(%ebx,%eax),%eax
+    BEXTR    %r15,0xCAFE(%r11,%r15,2),%rax
+    BEXTR    %r14,0xCAFE(%r9),%r14
+    BEXTR    %rdi,%rax,%r15
+    BEXTR    %rax,(%edx),%r13
+    BEXTR    %rdx,(%r15),%r10
+    BEXTR    %r10,%r15,%rbp
+    BEXTR    %r12,(%esi),%rdi
+    BEXTR    %rcx,%r12,%r12
+    BEXTR    %rbp,%r8,%rbx
+    BEXTR    %rbx,(%r12),%rsp
+    BEXTR    %r9,(%r13),%r11
+    BEXTR    %r11,(%r8),%rsi
+    BEXTR    %rsi,%rcx,%rdx
+    BEXTR    %r13,0x3(%r10d,%r9d,1),%r15
+    BEXTR    %rax,(%r15d),%rax
+    BEXTR    %r15,(%r8d),%rcx
+    BLSI     -0xD(,%r15d,2),%esi
+    BLSI     %r15d,%r15d
+    BLSI     %eax,%eax
+    BLSI     (%r9),%r10d
+    BLSI     %ebp,%r9d
+    BLSI     0x5(,%r9,2),%edx
+    BLSI     -0x6A(,%r11,2),%ecx
+    BLSI     (%ecx),%ebp
+    BLSI     (%edi),%r11d
+    BLSI     -0x7(%rdi),%r8d
+    BLSI     (%r8d),%r13d
+    BLSI     (%r10),%ebx
+    BLSI     0xCAFE(,%rax),%edi
+    BLSI     (%esi),%eax
+    BLSI     %r9d,%eax
+    BLSI     -0x67(%r10d,%edi,1),%eax
+    BLSI     0xF(%r10),%r15
+    BLSI     %r15,%rax
+    BLSI     %rax,%rsp
+    BLSI     (%eax),%r10
+    BLSI     (%r8d),%r13
+    BLSI     0x85(%edi,%r9d,8),%r14
+    BLSI     %r10,%r12
+    BLSI     (%r11),%r8
+    BLSI     -0x472429E0(%r15),%r9
+    BLSI     (%edi),%rdx
+    BLSI     (,%edx,4),%rbx
+    BLSI     (%ebx),%rdi
+    BLSI     0xDEAD(%r10),%rcx
+    BLSI     0x1B(%r15,%r14,8),%rdi
+    BLSI     (%rbx),%r11
+    BLSI     0xA(%r8,%r9),%rax
+    BLSMSK   %eax,%eax
+    BLSMSK   (,%r9,4),%esi
+    BLSMSK   (,%edi,2),%r15d
+    BLSMSK   (%rdi),%esp
+    BLSMSK   (%r13d),%ecx
+    BLSMSK   %r9d,%r14d
+    BLSMSK   (%rdx),%r8d
+    BLSMSK   (%esi),%r12d
+    BLSMSK   0x65F822C5(%r13,%rdx),%r11d
+    BLSMSK   -0x3(%ebx,%ecx,1),%r10d
+    BLSMSK   %r15d,%ebp
+    BLSMSK   %esi,%r13d
+    BLSMSK   (%r15),%edx
+    BLSMSK   (%r14),%r10d
+    BLSMSK   %ebp,%edi
+    BLSMSK   (%rcx,%r12),%ebx
+    BLSMSK   %r15,%rdx
+    BLSMSK   (%rax,%rcx,8),%rax
+    BLSMSK   %r9,%r15
+    BLSMSK   (%r15d),%r8
+    BLSMSK   %rax,%r15
+    BLSMSK   -0x3(%rsi),%r12
+    BLSMSK   -0x0(%rdx,%rdx),%rsi
+    BLSMSK   (%r14),%rbx
+    BLSMSK   (%r15),%rdi
+    BLSMSK   -0xDC(,%r12),%rbp
+    BLSMSK   (%ebx),%r11
+    BLSMSK   0x43B8(,%r14d),%rax
+    BLSMSK   %rdx,%r13
+    BLSMSK   %rbp,%r9
+    BLSMSK   (%eax),%rsp
+    BLSMSK   (%r14d),%r15
+    BLSR     %r15d,%r15d
+    BLSR     %eax,%r9d
+    BLSR     0x1(,%edx),%r14d
+    BLSR     %edx,%ecx
+    BLSR     (%rcx,%r14,2),%ebx
+    BLSR     0x464A(,%r9d,4),%eax
+    BLSR     (%rsi),%esp
+    BLSR     (%ecx),%esi
+    BLSR     (%edi),%esi
+    BLSR     (,%edi,2),%r10d
+    BLSR     (%rdx),%r11d
+    BLSR     (%r11),%r13d
+    BLSR     %r9d,%r8d
+    BLSR     %edi,%edx
+    BLSR     (%ebx),%eax
+    BLSR     (%rax),%edi
+    BLSR     (%r11),%r15
+    BLSR     0x3(,%ecx),%r9
+    BLSR     (%rsi),%rsp
+    BLSR     (%r13),%rax
+    BLSR     %r15,%rdx
+    BLSR     (%r14d),%r8
+    BLSR     (%r14),%rax
+    BLSR     (%r8),%rbp
+    BLSR     %rdx,%r11
+    BLSR     (%edx),%r15
+    BLSR     0x337E(,%r12d),%rbx
+    BLSR     (%rax),%rcx
+    BLSR     %rbp,%rsp
+    BLSR     %rax,%r10
+    BLSR     0x67(%r13,%r12,4),%r12
+    BLSR     (,%r13d,1),%rdi
+    LZCNT    0x1F5A(,%r8d),%r13w
+    LZCNT    %ax,%r12w
+    LZCNT    (%r9),%r10w
+    LZCNT    %r13w,%ax
+    LZCNT    -0x67(,%rax,8),%r15w
+    LZCNT    (%r13,%rdx),%di
+    LZCNT    (%rdi),%bp
+    LZCNT    (%r11),%r8w
+    LZCNT    %r15w,%si
+    LZCNT    (%r14d),%sp
+    LZCNT    (%rcx),%r9w
+    LZCNT    0x9AE7(%r11,%rbx,8),%r9w
+    LZCNT    %si,%si
+    LZCNT    (%ebx),%cx
+    LZCNT    (%r10d),%bx
+    LZCNT    %r9w,%r14w
+    LZCNT    (%r13d),%r15d
+    LZCNT    %edi,%esp
+    LZCNT    (%r14d),%r13d
+    LZCNT    (%r14),%edx
+    LZCNT    %r15d,%r11d
+    LZCNT    %eax,%eax
+    LZCNT    (%r8),%esi
+    LZCNT    %r9d,%r15d
+    LZCNT    (%r12),%r8d
+    LZCNT    %r8d,%ebp
+    LZCNT    (%r10d),%ebx
+    LZCNT    (%r12,%rcx),%edi
+    LZCNT    (%rdi),%r15d
+    LZCNT    (%edi),%r15d
+    LZCNT    %r12d,%r10d
+    LZCNT    (,%r13,1),%eax
+    LZCNT    (%r13d),%rbp
+    LZCNT    (%r10d),%r8
+    LZCNT    (%esi),%rax
+    LZCNT    %rbx,%r13
+    LZCNT    (%r9),%r15
+    LZCNT    %rdx,%rcx
+    LZCNT    (,%r13,2),%rax
+    LZCNT    (%eax),%rsi
+    LZCNT    (%r15d),%rsp
+    LZCNT    (,%r15d,4),%r11
+    LZCNT    %r15,%r12
+    LZCNT    (%rdi),%rdx
+    LZCNT    (%r12d),%r9
+    LZCNT    %r11,%r10
+    LZCNT    0xCAFE(,%ebx,8),%r13
+    LZCNT    %rax,%rax
+    TZCNT    %r10w,%r14w
+    TZCNT    0x737A(%r14),%ax
+    TZCNT    %ax,%r10w
+    TZCNT    %r15w,%si
+    TZCNT    (%r12),%r15w
+    TZCNT    (%edx),%sp
+    TZCNT    (%rax),%r13w
+    TZCNT    %r12w,%bp
+    TZCNT    0x3CAD(%r9d),%ax
+    TZCNT    0x6(%r10,%rdx),%ax
+    TZCNT    %r13w,%r11w
+    TZCNT    (%r10d,%r14d),%cx
+    TZCNT    0x4CD0AE44(%r10d,%ebx,4),%r12w
+    TZCNT    (%r15d),%r15w
+    TZCNT    (%r8),%r9w
+    TZCNT    (%r9d),%ax
+    TZCNT    (%r8),%edx
+    TZCNT    (%esi),%r11d
+    TZCNT    (%r10),%eax
+    TZCNT    -0x3D(%r14,%rdx),%r15d
+    TZCNT    (%r13),%esi
+    TZCNT    (%rdi),%r12d
+    TZCNT    (%ecx),%eax
+    TZCNT    -0x6544(%r9,%r13,8),%r13d
+    TZCNT    %eax,%esp
+    TZCNT    %r15d,%r8d
+    TZCNT    -0xF(,%ecx),%edi
+    TZCNT    (%r9),%r9d
+    TZCNT    (%rcx),%esp
+    TZCNT    (%r8,%r10),%ebp
+    TZCNT    (%rdi,%r10),%r14d
+    TZCNT    (%eax),%esi
+    TZCNT    (%edi),%r9
+    TZCNT    (%r9),%rbp
+    TZCNT    (%r15d,%ebx,4),%r15
+    TZCNT    (%r14),%r12
+    TZCNT    0x62F28A0E(,%r8),%r10
+    TZCNT    (%r8,%rsi),%r14
+    TZCNT    (%esi),%rax
+    TZCNT    %r13,%rax
+    TZCNT    0x3D6C(%r9),%r8
+    TZCNT    %rax,%r15
+    TZCNT    (,%r9,2),%rsp
+    TZCNT    (,%r12d,8),%rbx
+    TZCNT    (%rsi,%rdx),%r11
+    TZCNT    (%rcx,%r13,4),%rdi
+    TZCNT    -0xF(%r11,%rax,8),%rax
+    TZCNT    (%r8),%rax
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b18b6b9..adb94b4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,42 @@
+2010-12-21  Quentin Neill  <quentin.neill@amd.com>
+
+	* i386-dis.c (REG_XOP_BMI_F3): New.
+	(PREFIX_BMI_F30F): New.
+	(dis386_twobyte): Redirect to PREFIX_BMI_F30F entry.
+	(reg_table): Add REG_XOP_BMI_F3 table.
+	(prefix_table): Add PREFIX_BMI_F30F table.
+	(x86_64_table): Add andn, bextr, and redirect to
+	REG_XOP_BMI_F3 entry.
+
+	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS, CpuBMI.
+	(cpu_flags): Add CpuBMI.
+	(opcode_modifiers): Define bitfield ModrmRegExt.
+
+	* i386-opc.h (CpuBMI) New.
+	(i386_cpu_flags): Add bit cpubmi.
+	(ModrmRegExt): New.
+	(VEXLWP): Rename to VEXVRM.
+	(XOP02): New VexOpcode encoding.
+	(XOP2REVSOURCESS): New VexSources encoding.
+	(i386_opcode_modifier): Add modrmregext bit, increase
+	vexvvvv bit width to 3.
+
+	* i386-opc.tbl (andn): Added.
+	(andn): Added.
+	(bextr): Added.
+	(bextr): Added.
+	(blsi): Added.
+	(blsi): Added.
+	(blsmsk): Added.
+	(blsmsk): Added.
+	(blsr): Added.
+	(blsr): Added.
+	(tzcnt): Added.
+
+	* i386-init.h: Regenerated.
+
+	* i386-tbl.h: Regenerated
+
 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
 
 	* mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index f2def13..30ea470 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -599,7 +599,8 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_XOP_LWPCB,
-  REG_XOP_LWP
+  REG_XOP_LWP,
+  REG_XOP_BMI_F3
 };
 
 enum
@@ -1068,7 +1069,8 @@ enum
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,
-  PREFIX_VEX_0F3ADF
+  PREFIX_VEX_0F3ADF,
+  PREFIX_BMI_F30F
 };
 
 enum
@@ -2158,7 +2160,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "ud1",		{ XX } },
   { REG_TABLE (REG_0FBA) },
   { "btcS",		{ Ev, Gv } },
-  { "bsfS",		{ Gv, Ev } },
+  { PREFIX_TABLE (PREFIX_BMI_F30F) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",	{ Gv, Eb } },
   { "movs{wR|x}",	{ Gv, Ew } }, /* yes, there really is movsww ! */
@@ -2759,6 +2761,13 @@ static const struct dis386 reg_table[][8] = {
     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
     { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq } },
   },
+  /* REG_XOP_BMI_F3 */
+  {
+    { Bad_Opcode },
+    { "blsr",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsmsk",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsi",	{ { OP_LWP_E, 0 }, Ev } },
+  },
 };
 
 static const struct dis386 prefix_table[][4] = {
@@ -5354,6 +5363,14 @@ static const struct dis386 prefix_table[][4] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },
+
+  /* PREFIX_BMI_F30F */
+  {
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+  },
 };
 
 static const struct dis386 x86_64_table[][2] = {
@@ -7828,12 +7845,12 @@ static const struct dis386 vex_table[][256] = {
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
+    { "andn",	{ Gv, { OP_LWP_E, 0 }, Ev } },
+    { REG_TABLE (REG_XOP_BMI_F3) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "bextr",	{ Gv, Ev, { OP_LWP_E, 0 } } },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index ee06338..c4ed21f 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,6 +140,8 @@ static initializer cpu_flag_init[] =
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
   { "CPU_LWP_FLAGS",
     "CpuLWP" },
+  { "CPU_BMI_FLAGS",
+    "CpuBMI" },
   { "CPU_MOVBE_FLAGS",
     "CpuMovbe" },
   { "CPU_RDTSCP_FLAGS",
@@ -320,6 +322,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuFMA4),
   BITFIELD (CpuXOP),
   BITFIELD (CpuLWP),
+  BITFIELD (CpuBMI),
   BITFIELD (CpuLM),
   BITFIELD (CpuMovbe),
   BITFIELD (CpuEPT),
@@ -340,6 +343,7 @@ static bitfield opcode_modifiers[] =
   BITFIELD (W),
   BITFIELD (S),
   BITFIELD (Modrm),
+  BITFIELD (ModrmRegExt),
   BITFIELD (ShortForm),
   BITFIELD (Jump),
   BITFIELD (JumpDword),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index fe546b6..d5697de 100644
Binary files a/opcodes/i386-init.h and b/opcodes/i386-init.h differ
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index fe4fe97..43c0d14 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,6 +110,8 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
+  /* BMI support required */
+  CpuBMI,
   /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -186,6 +188,7 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
+      unsigned int cpubmi:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -215,6 +218,8 @@ enum
   S,
   /* insn has a modrm byte. */
   Modrm,
+  /* instruction has opcode extension in ModRM reg.  */
+  ModrmRegExt,
   /* register is in low 3 bits of opcode */
   ShortForm,
   /* special case for jump insns.  */
@@ -304,12 +309,12 @@ enum
 	For assembler, there are no difference between VEX.NDS and
 	VEX.DDS.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
-     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
+     3. VEX.VRM.  Register destination is encoded in VEX.vvvv and one
 	of the operands can access a memory location.
    */
 #define VEXXDS	1
 #define VEXNDD	2
-#define VEXLWP	3
+#define VEXVRM	3
   VexVVVV,
   /* How the VEX.W bit is used:
      0: Set by the REX.W bit.
@@ -333,14 +338,17 @@ enum
 #define XOP08		3
 #define XOP09		4
 #define XOP0A		5
+#define XOP02		6
   VexOpcode,
   /* number of VEX source operands:
      0: <= 2 source operands.
      1: 2 XOP source operands.
      2: 3 source operands.
+     3: 2 XOP source operands but order reversed.
    */
 #define XOP2SOURCES	1
 #define VEX3SOURCES	2
+#define XOP2REVSOURCES	3
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
@@ -366,6 +374,7 @@ typedef struct i386_opcode_modifier
   unsigned int w:1;
   unsigned int s:1;
   unsigned int modrm:1;
+  unsigned int modrmregext:1;
   unsigned int shortform:1;
   unsigned int jump:1;
   unsigned int jumpdword:1;
@@ -401,7 +410,7 @@ typedef struct i386_opcode_modifier
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
-  unsigned int vexvvvv:2;
+  unsigned int vexvvvv:3;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f63919e..23eb2f2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,6 +2733,19 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
 
+// BMI instructions
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32, Reg32 }
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64, Reg64 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|ModrmRegExt|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+tzcnt,   2, 0xf30fbc, None, 2, CpuBMI, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+
 // AMD 3DNow! instructions.
 
 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5c4e7e8..72e1173 100644
Binary files a/opcodes/i386-tbl.h and b/opcodes/i386-tbl.h differ

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-20 23:25   ` Quentin Neill
  2010-12-21  2:30     ` Sebastian Pop
@ 2010-12-28 13:56     ` H.J. Lu
  2010-12-28 17:02       ` H.J. Lu
  1 sibling, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2010-12-28 13:56 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>> AMD bdver2 processors.
>>>
>>> The full encoding specification is delayed, however I have posted
>>> abbreviated specs on the gcc mailing list:
>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>
>>
>> Looks like your patch is reversed.  Could you please send another one
>> that you get from git format-patch -1
>>
>> Thanks,
>> Sebastian
>
> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
> --
> Quentin
>

Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
without ModrmRegExt.


-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-28 13:56     ` H.J. Lu
@ 2010-12-28 17:02       ` H.J. Lu
  2011-01-03 16:10         ` Quentin Neill
  2011-01-04 20:26         ` Quentin Neill
  0 siblings, 2 replies; 23+ messages in thread
From: H.J. Lu @ 2010-12-28 17:02 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>> AMD bdver2 processors.
>>>>
>>>> The full encoding specification is delayed, however I have posted
>>>> abbreviated specs on the gcc mailing list:
>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>
>>>
>>> Looks like your patch is reversed.  Could you please send another one
>>> that you get from git format-patch -1
>>>
>>> Thanks,
>>> Sebastian
>>
>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>> --
>> Quentin
>>
>
> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
> without ModrmRegExt.
>
>

You should check i.tm.extension_opcode != None instead.

-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-28 17:02       ` H.J. Lu
@ 2011-01-03 16:10         ` Quentin Neill
  2011-01-03 16:36           ` H.J. Lu
  2011-01-04 20:26         ` Quentin Neill
  1 sibling, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2011-01-03 16:10 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Sebastian Pop, binutils

On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>> AMD bdver2 processors.
>>>>>
>>>>> The full encoding specification is delayed, however I have posted
>>>>> abbreviated specs on the gcc mailing list:
>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>
>>>>
>>>> Looks like your patch is reversed.  Could you please send another one
>>>> that you get from git format-patch -1
>>>>
>>>> Thanks,
>>>> Sebastian
>>>
>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>> --
>>> Quentin
>>>
>>
>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>> without ModrmRegExt.
>>
>>
>
> You should check i.tm.extension_opcode != None instead.
>
> --
> H.J.

Hi H.J.,
Thanks for the feedback.
So you are saying remove ModrmRegExt from both patches, right?
-- 
Quentin

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-03 16:10         ` Quentin Neill
@ 2011-01-03 16:36           ` H.J. Lu
  2011-01-04  0:06             ` Quentin Neill
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-03 16:36 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Mon, Jan 3, 2011 at 8:10 AM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>> AMD bdver2 processors.
>>>>>>
>>>>>> The full encoding specification is delayed, however I have posted
>>>>>> abbreviated specs on the gcc mailing list:
>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>
>>>>>
>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>> that you get from git format-patch -1
>>>>>
>>>>> Thanks,
>>>>> Sebastian
>>>>
>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>> --
>>>> Quentin
>>>>
>>>
>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>> without ModrmRegExt.
>>>
>>>
>>
>> You should check i.tm.extension_opcode != None instead.
>>
>> --
>> H.J.
>
> Hi H.J.,
> Thanks for the feedback.
> So you are saying remove ModrmRegExt from both patches, right?

Yes.


-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-03 16:36           ` H.J. Lu
@ 2011-01-04  0:06             ` Quentin Neill
  2011-01-04  0:35               ` H.J. Lu
  0 siblings, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2011-01-04  0:06 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Sebastian Pop, binutils

On Mon, Jan 3, 2011 at 10:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, Jan 3, 2011 at 8:10 AM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>> AMD bdver2 processors.
>>>>>>>
>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>
>>>>>>
>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>> that you get from git format-patch -1
>>>>>>
>>>>>> Thanks,
>>>>>> Sebastian
>>>>>
>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>> --
>>>>> Quentin
>>>>>
>>>>
>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>> without ModrmRegExt.
>>>>
>>>>
>>>
>>> You should check i.tm.extension_opcode != None instead.
>>>
>>> --
>>> H.J.
>>
>> Hi H.J.,
>> Thanks for the feedback.
>> So you are saying remove ModrmRegExt from both patches, right?
>
> Yes.

Hi H.J.,

I concur that ModrmRegExt is not needed (I see opcode_extension used
later to encode modrm.reg).  But I need a way to distinguish TBM/BMI
from LWP instructions which don't swap the operand order:

lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|VexVVVV=3|Vex|...
llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|Vex|...
blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
blcmsk, 2, 0x02,  0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...

Is it okay to branch on the number of instructions to make encoding
decisions?   That seems about as kludgy as branching on the opcode or
opcode_modifier, but rather than post a patch I thought I'd email
first.
-- 
Quentin

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-04  0:06             ` Quentin Neill
@ 2011-01-04  0:35               ` H.J. Lu
  2011-01-04 15:12                 ` Quentin Neill
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-04  0:35 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Mon, Jan 3, 2011 at 4:06 PM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Mon, Jan 3, 2011 at 10:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Mon, Jan 3, 2011 at 8:10 AM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>>> AMD bdver2 processors.
>>>>>>>>
>>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>>
>>>>>>>
>>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>>> that you get from git format-patch -1
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Sebastian
>>>>>>
>>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>>> --
>>>>>> Quentin
>>>>>>
>>>>>
>>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>>> without ModrmRegExt.
>>>>>
>>>>>
>>>>
>>>> You should check i.tm.extension_opcode != None instead.
>>>>
>>>> --
>>>> H.J.
>>>
>>> Hi H.J.,
>>> Thanks for the feedback.
>>> So you are saying remove ModrmRegExt from both patches, right?
>>
>> Yes.
>
> Hi H.J.,
>
> I concur that ModrmRegExt is not needed (I see opcode_extension used
> later to encode modrm.reg).  But I need a way to distinguish TBM/BMI
> from LWP instructions which don't swap the operand order:
>
> lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|VexVVVV=3|Vex|...
> llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|Vex|...
> blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
> blcmsk, 2, 0x02,  0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>
> Is it okay to branch on the number of instructions to make encoding
> decisions?   That seems about as kludgy as branching on the opcode or
> opcode_modifier, but rather than post a patch I thought I'd email
> first.

x86 assembler always swap operands, except for

  /* All intel opcodes have reversed operands except for "bound" and
     "enter".  We also don't reverse intersegment "jmp" and "call"
     instructions with 2 immediate operands so that the immediate segment
     precedes the offset, as it does when in AT&T mode. */
  if (intel_syntax
      && i.operands > 1
      && (strcmp (mnemonic, "bound") != 0)
      && (strcmp (mnemonic, "invlpga") != 0)
      && !(operand_type_check (i.types[0], imm)
           && operand_type_check (i.types[1], imm)))
    swap_operands ();

What is the problem with TBM/BMI/LWP?

-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-04  0:35               ` H.J. Lu
@ 2011-01-04 15:12                 ` Quentin Neill
  2011-01-04 15:24                   ` H.J. Lu
  0 siblings, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2011-01-04 15:12 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Sebastian Pop, binutils

On Mon, Jan 3, 2011 at 6:35 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Mon, Jan 3, 2011 at 4:06 PM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Mon, Jan 3, 2011 at 10:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Mon, Jan 3, 2011 at 8:10 AM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>>>> AMD bdver2 processors.
>>>>>>>>>
>>>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>>>
>>>>>>>>
>>>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>>>> that you get from git format-patch -1
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>> Sebastian
>>>>>>>
>>>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>>>> --
>>>>>>> Quentin
>>>>>>>
>>>>>>
>>>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>>>> without ModrmRegExt.
>>>>>>
>>>>>>
>>>>>
>>>>> You should check i.tm.extension_opcode != None instead.
>>>>>
>>>>> --
>>>>> H.J.
>>>>
>>>> Hi H.J.,
>>>> Thanks for the feedback.
>>>> So you are saying remove ModrmRegExt from both patches, right?
>>>
>>> Yes.
>>
>> Hi H.J.,
>>
>> I concur that ModrmRegExt is not needed (I see opcode_extension used
>> later to encode modrm.reg).  But I need a way to distinguish TBM/BMI
>> from LWP instructions which don't swap the operand order:
>>
>> lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|VexVVVV=3|Vex|...
>> llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|Vex|...
>> blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>> blcmsk, 2, 0x02,  0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>>
>> Is it okay to branch on the number of instructions to make encoding
>> decisions?   That seems about as kludgy as branching on the opcode or
>> opcode_modifier, but rather than post a patch I thought I'd email
>> first.
>
> x86 assembler always swap operands, except for
>
>  /* All intel opcodes have reversed operands except for "bound" and
>     "enter".  We also don't reverse intersegment "jmp" and "call"
>     instructions with 2 immediate operands so that the immediate segment
>     precedes the offset, as it does when in AT&T mode. */
>  if (intel_syntax
>      && i.operands > 1
>      && (strcmp (mnemonic, "bound") != 0)
>      && (strcmp (mnemonic, "invlpga") != 0)
>      && !(operand_type_check (i.types[0], imm)
>           && operand_type_check (i.types[1], imm)))
>    swap_operands ();
>
> What is the problem with TBM/BMI/LWP?
>
> --
> H.J.

For LWP (3 operands)
vvvv = i.op[2].regs
modrm.rm = i.op[1].regs->reg_num

For BMI/TBM (2 operands)
vvvv = i.op[1].regs
modrm.rm = i.op[0].regs->reg_num

I will post another patch presently that will ask the same question in
the form of a code review :)
-- 
Quentin

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-04 15:12                 ` Quentin Neill
@ 2011-01-04 15:24                   ` H.J. Lu
  2011-01-04 20:21                     ` Quentin Neill
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-04 15:24 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Tue, Jan 4, 2011 at 7:12 AM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Mon, Jan 3, 2011 at 6:35 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Mon, Jan 3, 2011 at 4:06 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Mon, Jan 3, 2011 at 10:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Mon, Jan 3, 2011 at 8:10 AM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>>>>> AMD bdver2 processors.
>>>>>>>>>>
>>>>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>>>>> that you get from git format-patch -1
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>> Sebastian
>>>>>>>>
>>>>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>>>>> --
>>>>>>>> Quentin
>>>>>>>>
>>>>>>>
>>>>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>>>>> without ModrmRegExt.
>>>>>>>
>>>>>>>
>>>>>>
>>>>>> You should check i.tm.extension_opcode != None instead.
>>>>>>
>>>>>> --
>>>>>> H.J.
>>>>>
>>>>> Hi H.J.,
>>>>> Thanks for the feedback.
>>>>> So you are saying remove ModrmRegExt from both patches, right?
>>>>
>>>> Yes.
>>>
>>> Hi H.J.,
>>>
>>> I concur that ModrmRegExt is not needed (I see opcode_extension used
>>> later to encode modrm.reg).  But I need a way to distinguish TBM/BMI
>>> from LWP instructions which don't swap the operand order:
>>>
>>> lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|VexVVVV=3|Vex|...
>>> llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|Vex|...
>>> blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>>> blcmsk, 2, 0x02,  0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>>>
>>> Is it okay to branch on the number of instructions to make encoding
>>> decisions?   That seems about as kludgy as branching on the opcode or
>>> opcode_modifier, but rather than post a patch I thought I'd email
>>> first.
>>
>> x86 assembler always swap operands, except for
>>
>>  /* All intel opcodes have reversed operands except for "bound" and
>>     "enter".  We also don't reverse intersegment "jmp" and "call"
>>     instructions with 2 immediate operands so that the immediate segment
>>     precedes the offset, as it does when in AT&T mode. */
>>  if (intel_syntax
>>      && i.operands > 1
>>      && (strcmp (mnemonic, "bound") != 0)
>>      && (strcmp (mnemonic, "invlpga") != 0)
>>      && !(operand_type_check (i.types[0], imm)
>>           && operand_type_check (i.types[1], imm)))
>>    swap_operands ();
>>
>> What is the problem with TBM/BMI/LWP?
>>
>> --
>> H.J.
>
> For LWP (3 operands)
> vvvv = i.op[2].regs
> modrm.rm = i.op[1].regs->reg_num

How is op0 encoded?

> For BMI/TBM (2 operands)
> vvvv = i.op[1].regs
> modrm.rm = i.op[0].regs->reg_num
>
> I will post another patch presently that will ask the same question in
> the form of a code review :)


-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-04 15:24                   ` H.J. Lu
@ 2011-01-04 20:21                     ` Quentin Neill
  0 siblings, 0 replies; 23+ messages in thread
From: Quentin Neill @ 2011-01-04 20:21 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Sebastian Pop, binutils

On Tue, Jan 4, 2011 at 9:24 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Tue, Jan 4, 2011 at 7:12 AM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Mon, Jan 3, 2011 at 6:35 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Mon, Jan 3, 2011 at 4:06 PM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Mon, Jan 3, 2011 at 10:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Mon, Jan 3, 2011 at 8:10 AM, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>>>>>> AMD bdver2 processors.
>>>>>>>>>>>
>>>>>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>>>>>> that you get from git format-patch -1
>>>>>>>>>>
>>>>>>>>>> Thanks,
>>>>>>>>>> Sebastian
>>>>>>>>>
>>>>>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>>>>>> --
>>>>>>>>> Quentin
>>>>>>>>>
>>>>>>>>
>>>>>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>>>>>> without ModrmRegExt.
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>> You should check i.tm.extension_opcode != None instead.
>>>>>>>
>>>>>>> --
>>>>>>> H.J.
>>>>>>
>>>>>> Hi H.J.,
>>>>>> Thanks for the feedback.
>>>>>> So you are saying remove ModrmRegExt from both patches, right?
>>>>>
>>>>> Yes.
>>>>
>>>> Hi H.J.,
>>>>
>>>> I concur that ModrmRegExt is not needed (I see opcode_extension used
>>>> later to encode modrm.reg).  But I need a way to distinguish TBM/BMI
>>>> from LWP instructions which don't swap the operand order:
>>>>
>>>> lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|VexVVVV=3|Vex|...
>>>> llwpcb, 1, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=4|VexW=1|Vex|...
>>>> blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>>>> blcmsk, 2, 0x02,  0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|...
>>>>
>>>> Is it okay to branch on the number of instructions to make encoding
>>>> decisions?   That seems about as kludgy as branching on the opcode or
>>>> opcode_modifier, but rather than post a patch I thought I'd email
>>>> first.
>>>
>>> x86 assembler always swap operands, except for
>>>
>>>  /* All intel opcodes have reversed operands except for "bound" and
>>>     "enter".  We also don't reverse intersegment "jmp" and "call"
>>>     instructions with 2 immediate operands so that the immediate segment
>>>     precedes the offset, as it does when in AT&T mode. */
>>>  if (intel_syntax
>>>      && i.operands > 1
>>>      && (strcmp (mnemonic, "bound") != 0)
>>>      && (strcmp (mnemonic, "invlpga") != 0)
>>>      && !(operand_type_check (i.types[0], imm)
>>>           && operand_type_check (i.types[1], imm)))
>>>    swap_operands ();
>>>
>>> What is the problem with TBM/BMI/LWP?
>>>
>>> --
>>> H.J.
>>
>> For LWP (3 operands)
>> vvvv = i.op[2].regs
>> modrm.rm = i.op[1].regs->reg_num
>
> How is op0 encoded?
>
>> For BMI/TBM (2 operands)
>> vvvv = i.op[1].regs
>> modrm.rm = i.op[0].regs->reg_num
>>
>> I will post another patch presently that will ask the same question in
>> the form of a code review :)
>
>
> --
> H.J.

For LWP insns with 3 insns, op0 is always an immediate.
-- 
Quentin

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2010-12-28 17:02       ` H.J. Lu
  2011-01-03 16:10         ` Quentin Neill
@ 2011-01-04 20:26         ` Quentin Neill
  2011-01-04 20:58           ` H.J. Lu
  1 sibling, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2011-01-04 20:26 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Sebastian Pop, binutils

[-- Attachment #1: Type: text/plain, Size: 1367 bytes --]

On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>> AMD bdver2 processors.
>>>>>
>>>>> The full encoding specification is delayed, however I have posted
>>>>> abbreviated specs on the gcc mailing list:
>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>
>>>>
>>>> Looks like your patch is reversed.  Could you please send another one
>>>> that you get from git format-patch -1
>>>>
>>>> Thanks,
>>>> Sebastian
>>>
>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>> --
>>> Quentin
>>>
>>
>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>> without ModrmRegExt.
>>
>>
>
> You should check i.tm.extension_opcode != None instead.
>
> --
> H.J.

Fixed with the attached.
Tested and passes with "make check RUNTESTFLAGS=i386.exp".
Okay to commit?
-- 
Quentin

[-- Attachment #2: 7041_bdver2_bmi.diff.txt --]
[-- Type: text/plain, Size: 112937 bytes --]

diff --git a/bfd/version.h b/bfd/version.h
index d669cfd..8b00b82 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -1,4 +1,4 @@
-#define BFD_VERSION_DATE 20110102
+#define BFD_VERSION_DATE 20110103
 #define BFD_VERSION @bfd_version@
 #define BFD_VERSION_STRING  @bfd_version_package@ @bfd_version_string@
 #define REPORT_BUGS_TO @report_bugs_to@
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 63868a0..02f4856 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,17 @@
+2011-01-04  Quentin Neill  <quentin.neill@amd.com>
+
+	* doc/c-i386.texi (i386-TBM): New section.
+
+	* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
+
+2011-01-04  Quentin Neill  <quentin.neill@amd.com>
+
+	* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
+	(build_modrm_byte): Add BMI instruction encoding.
+	VEXLWP renamed VEXVRM.
+
+	* doc/c-i386.texi (i386-BMI): New section.
+
 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas.c (parse_args): Update copyright to 2011.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 7ca97a6..9cd2976 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -725,6 +725,10 @@ static const arch_entry cpu_arch[] =
     CPU_SSE4A_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
     CPU_ABM_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
+    CPU_BMI_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
+    CPU_TBM_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF
@@ -5563,7 +5567,8 @@ build_modrm_byte (void)
       else
 	mem = ~0;
 
-      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
+      if (i.tm.opcode_modifier.vexsources == XOP2SOURCES
+          || i.tm.opcode_modifier.vexsources == XOP2REVSOURCES)
 	{
 	  if (operand_type_check (i.types[0], imm))
 	    i.vex.register_specifier = NULL;
@@ -5571,7 +5576,8 @@ build_modrm_byte (void)
 	    {
 	      /* VEX.vvvv encodes one of the sources when the first
 		 operand is not an immediate.  */
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if (i.tm.opcode_modifier.vexsources == XOP2SOURCES
+                  && i.tm.opcode_modifier.vexw == VEXW0)
 		i.vex.register_specifier = i.op[0].regs;
 	      else
 		i.vex.register_specifier = i.op[1].regs;
@@ -5588,7 +5594,8 @@ build_modrm_byte (void)
 	    {
 	      i.rm.mode = 3;
 
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
+              if (i.tm.opcode_modifier.vexsources == XOP2SOURCES
+                  && i.tm.opcode_modifier.vexw == VEXW0)
 		i.rm.regmem = i.op[1].regs->reg_num;
 	      else
 		i.rm.regmem = i.op[0].regs->reg_num;
@@ -5597,17 +5604,32 @@ build_modrm_byte (void)
 		i.rex |= REX_B;
 	    }
 	}
-      else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
+      else if (i.tm.opcode_modifier.vexvvvv == VEXVRM)
 	{
-	  i.vex.register_specifier = i.op[2].regs;
+	  unsigned int regspec_op = MAX_OPERANDS;
+	  unsigned int regmem_op = MAX_OPERANDS; 
+	  if (i.operands == 2
+              && i.tm.extension_opcode != None)
+	    {
+	      regspec_op = 1;
+	      regmem_op = 0;
+	    }
+	  else
+	    {
+	      regspec_op = 2;
+	      regmem_op = 1;
+	    }
+
+	  i.vex.register_specifier = i.op[regspec_op].regs;
 	  if (!i.mem_operands)
 	    {
 	      i.rm.mode = 3;
-	      i.rm.regmem = i.op[1].regs->reg_num;
-	      if ((i.op[1].regs->reg_flags & RegRex) != 0)
+	      i.rm.regmem = i.op[regmem_op].regs->reg_num;
+	      if ((i.op[regmem_op].regs->reg_flags & RegRex) != 0)
 		i.rex |= REX_B;
 	    }
 	}
+
       /* Fill in i.rm.reg or i.rm.regmem field with register operand
 	 (if any) based on i.tm.extension_opcode.  Again, we must be
 	 careful to make sure that segment/control/debug/test/MMX
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index c3956a8..719107e 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,6 +35,8 @@ extending the Intel architecture to 64-bits.
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-LWP::                    AMD's Lightweight Profiling Instructions
+* i386-TBM::                    AMD's Trailing Bit Manipulation Instructions
+* i386-BMI::                    Bit Manipulation Instructions
 * i386-16bit::                  Writing 16-bit Code
 * i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
@@ -845,6 +847,36 @@ For detailed information on the LWP instruction set, see the
 @cite{AMD Lightweight Profiling Specification} available at
 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
 
+@node i386-TBM
+@section AMD's Trailing Bit Manipulation Instructions
+
+@cindex TBM, i386
+@cindex TBM, x86-64
+
+@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
+instruction set, available on AMD's BDVER2 processors (Trinity and
+Viperfish).
+
+TBM instructions provide instructions implementing individual bit
+manipulation operations such as isolating, masking, setting, resetting,
+complementing, and operations on trailing zeros and ones.
+
+@c Need to add a specification citation here.
+
+@node i386-BMI
+@section Bit Manipulation Instructions
+
+@cindex BMI, i386
+@cindex BMI, x86-64
+
+@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
+
+BMI instructions provide several instructions implementing individual
+bit manipulation operations such as isolation, masking, setting, or
+resetting.  
+
+@c Need to add a specification citation here.
+
 @node i386-16bit
 @section Writing 16-bit Code
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 0aeed72..b2c0273 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,35 @@
+2011-01-04  Quentin Neill  <quentin.neill@amd.com>
+
+	* gas/i386/i386.exp: Run tbm and x86-64-tbm.
+	* gas/i386/tbm.d: New.
+	* gas/i386/tbm.s: New.
+	* gas/i386/x86-64-tbm.d: New.
+	* gas/i386/x86-64-tbm.s: New.
+	* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
+	* gas/i386/arch-10.s: Add a TBM instruction.
+	* gas/i386/arch-10-1.l: Add TBM instruction pattern.
+	* gas/i386/arch-10-2.l: Likewise.
+	* gas/i386/arch-10-3.l: Likewise.
+	* gas/i386/arch-10-4.l: Likewise.
+	* gas/i386/x86-64-arch-2.s: Likewise.
+	* gas/i386/x86-64-arch-2.d: Likewise.
+
+2011-01-04  Quentin Neill  <quentin.neill@amd.com>
+
+	* gas/i386/i386.exp: Run bmi and x86-64-bmi.
+	* gas/i386/bmi.d: New.
+	* gas/i386/bmi.s: New.
+	* gas/i386/x86-64-bmi.d: New.
+	* gas/i386/x86-64-bmi.s: New.
+	* gas/i386/arch-10.s: Add a BMI instruction.
+	* gas/i386/x86-64-arch-2.s: Likewise.
+	* gas/i386/arch-10.d: Add bmi flag and BMI instruction pattern.
+	* gas/i386/x86-64-arch-2.d: Likewise.
+	* gas/i386/arch-10-1.l: Add BMI instruction pattern.
+	* gas/i386/arch-10-2.l: Likewise.
+	* gas/i386/arch-10-3.l: Likewise.
+	* gas/i386/arch-10-4.l: Likewise.
+
 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/ilp32/lns/lns-common-1.d: Also expect .zdebug in
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 0b78958..706a7a8 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -29,6 +29,8 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
+.*:66: Error: .*
 GAS LISTING .*
 
 
@@ -96,5 +98,9 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# TBM
+[ 	]*62[ 	]+blcfill %ecx,%ebx
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
+[ 	]*65[ 	]+\# nop
+[ 	]*66[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index d9e1b51..a6b6542 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -28,6 +28,8 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
+.*:66: Error: .*
 GAS LISTING .*
 
 
@@ -95,5 +97,9 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# TBM
+[ 	]*62[ 	]+blcfill %ecx,%ebx
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
+[ 	]*65[ 	]+\# nop
+[ 	]*66[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 75c07ec..afc94e2 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -21,6 +21,8 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
+.*:66: Error: .*
 GAS LISTING .*
 
 
@@ -91,5 +93,9 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# TBM
+[ 	]*62[ 	]+blcfill %ecx,%ebx
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
+[ 	]*65[ 	]+\# nop
+[ 	]*66[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 3c40045..ae7702c 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -19,6 +19,8 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
+.*:66: Error: .*
 GAS LISTING .*
 
 
@@ -89,5 +91,9 @@ GAS LISTING .*
 [ 	]*58[ 	]+lzcnt %ecx,%ebx
 [ 	]*59[ 	]+\# PadLock
 [ 	]*60[ 	]+xstorerng
-[ 	]*61[ 	]+\# nop
-[ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*61[ 	]+\# TBM
+[ 	]*62[ 	]+blcfill %ecx,%ebx
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
+[ 	]*65[ 	]+\# nop
+[ 	]*66[ 	]+nopl \(%eax\)
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 3efd52d..ae5d098 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+tbm+bmi
 #objdump: -dw
 #name: i386 arch 10
 
@@ -36,5 +36,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	8f e9 60 01 c9       	blcfill %ecx,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
 #pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index d0fb12b..9a70258 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -58,5 +58,9 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# TBM
+blcfill %ecx,%ebx
+# BMI
+blsr %ecx,%ebx
 # nop
 nopl (%eax)
diff --git a/gas/testsuite/gas/i386/bmi.d b/gas/testsuite/gas/i386/bmi.d
new file mode 100644
index 0000000..1f89b7c
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.d
@@ -0,0 +1,153 @@
+#objdump: -dw
+#name: i386 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 ff       	andn   %edi,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 70 f2 0c fa    	andn   \(%edx,%edi,8\),%ecx,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c3       	andn   %ebx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 14 9b    	andn   \(%ebx,%ebx,4\),%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 b1 dc 36 00 00 	andn   0x36dc\(%ecx\),%edi,%esi
+[ 	]*[a-f0-9]+:	c4 e2 48 f2 1b       	andn   \(%ebx\),%esi,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f8       	andn   %eax,%ebx,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f2 c1       	andn   %ecx,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 a4 5e 86 a9 9d ae 	andn   -0x5162567a\(%esi,%ebx,2\),%edx,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f2 2e       	andn   \(%esi\),%edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 c2       	andn   %edx,%esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f2 d6       	andn   %esi,%ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 be 53 21 ff ff 	andn   -0xdead\(%esi\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f2 74 19 0a 	andn   0xa\(%ecx,%ebx,1\),%esp,%esi
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 00       	andn   \(%eax\),%edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f2 7c 13 ce 	andn   -0x32\(%ebx,%edx,1\),%edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 3b       	bextr  %eax,\(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 31       	bextr  %edi,\(%ecx\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 58 f7 cf       	bextr  %esp,%edi,%ecx
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 c1       	bextr  %ebp,%ecx,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 f8       	bextr  %ebx,%eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 d3       	bextr  %esi,%ebx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 68 f7 04 07    	bextr  %edx,\(%edi,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 2f       	bextr  %edi,\(%edi\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f7 e6       	bextr  %ecx,%esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 18       	bextr  %edi,\(%eax\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 05 00 00 00 00 	bextr  %eax,0x0\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f7 22       	bextr  %ebp,\(%edx\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 48 f7 2c 85 0f a9 00 00 	bextr  %esi,0xa90f\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 60 f7 7c 03 03 	bextr  %ebx,0x3\(%ebx,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f7 b9 ff ff ff 3f 	bextr  %edi,0x3fffffff\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 04 12    	bextr  %eax,\(%edx,%edx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 df       	blsi   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1b       	blsi   \(%ebx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 de       	blsi   %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 da       	blsi   %edx,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 1f       	blsi   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 59 08    	blsi   0x8\(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1a       	blsi   \(%edx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 19       	blsi   \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 dd       	blsi   %ebp,%esp
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 1c 19    	blsi   \(%ecx,%ebx,1\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 1c 4d 03 00 00 00 	blsi   0x3\(,%ecx,2\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 1c 02    	blsi   \(%edx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 71    	blsi   \(%ecx,%esi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d8       	blsi   %eax,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%eax\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 d2       	blsmsk %edx,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d7       	blsmsk %edi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 d5       	blsmsk %ebp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 d3       	blsmsk %ebx,%esi
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 17       	blsmsk \(%edi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 11       	blsmsk \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 14 85 00 00 00 00 	blsmsk 0x0\(,%eax,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d4       	blsmsk %esp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 13       	blsmsk \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 d3    	blsmsk \(%ebx,%edx,8\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 d6       	blsmsk %esi,%esp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 94 7f af e6 3d a1 	blsmsk -0x5ec21951\(%edi,%edi,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 48    	blsmsk \(%eax,%ecx,2\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 14 1b    	blsmsk \(%ebx,%ebx,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 14 83    	blsmsk \(%ebx,%eax,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 8c 92 fe ca 00 00 	blsr   0xcafe\(%edx,%edx,4\),%esp
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cf       	blsr   %edi,%eax
+[ 	]*[a-f0-9]+:	c4 e2 48 f3 0c cd 00 00 00 00 	blsr   0x0\(,%ecx,8\),%esi
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 c8       	blsr   %eax,%edx
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 0e       	blsr   \(%esi\),%ecx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 9d 51 35 b0 66 	blsr   0x66b03551\(,%ebx,4\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 50 f3 0c 85 0a ff ff ff 	blsr   -0xf6\(,%eax,4\),%ebp
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 ce       	blsr   %esi,%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0b       	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 8c 7b 3a f2 00 00 	blsr   0xf23a\(%ebx,%edi,2\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 09       	blsr   \(%ecx\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 0c 05 05 00 00 00 	blsr   0x5\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 cd       	blsr   %ebp,%eax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 8c 03 c3 41 00 00 	blsr   0x41c3\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 0c 5d 03 00 00 00 	blsr   0x3\(,%ebx,2\),%edi
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 49 5a    	blsr   0x5a\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	66 f3 0f bd 38       	lzcnt  \(%eax\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd e7       	lzcnt  %di,%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bd 06       	lzcnt  \(%esi\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 cd 00 00 00 00 	lzcnt  0x0\(,%ecx,8\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fc       	lzcnt  %sp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 14 35 09 60 ff ff 	lzcnt  -0x9ff7\(,%esi,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bd bc cb 4d 6e 00 00 	lzcnt  0x6e4d\(%ebx,%ecx,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2a       	lzcnt  \(%edx\),%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bd c9       	lzcnt  %cx,%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bd dd       	lzcnt  %bp,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	66 f3 0f bd 04 05 00 00 00 00 	lzcnt  0x0\(,%eax,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bd f8       	lzcnt  %ax,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd db       	lzcnt  %bx,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bd fa       	lzcnt  %dx,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 1f       	lzcnt  \(%edi\),%bx
+[ 	]*[a-f0-9]+:	f3 0f bd db          	lzcnt  %ebx,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd f9          	lzcnt  %ecx,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 14 09       	lzcnt  \(%ecx,%ecx,1\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd cf          	lzcnt  %edi,%ecx
+[ 	]*[a-f0-9]+:	f3 0f bd fc          	lzcnt  %esp,%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 34 7d 00 00 00 00 	lzcnt  0x0\(,%edi,2\),%esi
+[ 	]*[a-f0-9]+:	f3 0f bd 03          	lzcnt  \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bd 3c 43       	lzcnt  \(%ebx,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 1f          	lzcnt  \(%edi\),%ebx
+[ 	]*[a-f0-9]+:	f3 0f bd ed          	lzcnt  %ebp,%ebp
+[ 	]*[a-f0-9]+:	f3 0f bd a3 ad de 00 00 	lzcnt  0xdead\(%ebx\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bd c6          	lzcnt  %esi,%eax
+[ 	]*[a-f0-9]+:	f3 0f bd bc 00 05 63 00 00 	lzcnt  0x6305\(%eax,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd bc 07 74 8f ff ff 	lzcnt  -0x708c\(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bd 06          	lzcnt  \(%esi\),%eax
+[ 	]*[a-f0-9]+:	66 f3 0f bc eb       	tzcnt  %bx,%bp
+[ 	]*[a-f0-9]+:	66 f3 0f bc c7       	tzcnt  %di,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc fd       	tzcnt  %bp,%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 14 16    	tzcnt  \(%esi,%edx,1\),%dx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0f       	tzcnt  \(%edi\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 0a       	tzcnt  \(%edx\),%cx
+[ 	]*[a-f0-9]+:	66 f3 0f bc d8       	tzcnt  %ax,%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc 24 8d 00 00 00 00 	tzcnt  0x0\(,%ecx,4\),%sp
+[ 	]*[a-f0-9]+:	66 f3 0f bc 31       	tzcnt  \(%ecx\),%si
+[ 	]*[a-f0-9]+:	66 f3 0f bc 03       	tzcnt  \(%ebx\),%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc 3c c7    	tzcnt  \(%edi,%eax,8\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc 1c 3b    	tzcnt  \(%ebx,%edi,1\),%bx
+[ 	]*[a-f0-9]+:	66 f3 0f bc c1       	tzcnt  %cx,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc b9 63 27 ff ff 	tzcnt  -0xd89d\(%ecx\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	66 f3 0f bc c5       	tzcnt  %bp,%ax
+[ 	]*[a-f0-9]+:	f3 0f bc f8          	tzcnt  %eax,%edi
+[ 	]*[a-f0-9]+:	f3 0f bc f7          	tzcnt  %edi,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 44 3b 61    	tzcnt  0x61\(%ebx,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc de          	tzcnt  %esi,%ebx
+[ 	]*[a-f0-9]+:	f3 0f bc 2a          	tzcnt  \(%edx\),%ebp
+[ 	]*[a-f0-9]+:	f3 0f bc 16          	tzcnt  \(%esi\),%edx
+[ 	]*[a-f0-9]+:	f3 0f bc 0c 0f       	tzcnt  \(%edi,%ecx,1\),%ecx
+[ 	]*[a-f0-9]+:	f3 0f bc f5          	tzcnt  %ebp,%esi
+[ 	]*[a-f0-9]+:	f3 0f bc 07          	tzcnt  \(%edi\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 07       	tzcnt  \(%edi,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 00       	tzcnt  \(%eax,%eax,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc 00          	tzcnt  \(%eax\),%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3c 45 bf ff ff ff 	tzcnt  -0x41\(,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	f3 0f bc 24 1d 01 00 00 c0 	tzcnt  -0x3fffffff\(,%ebx,1\),%esp
+[ 	]*[a-f0-9]+:	f3 0f bc c3          	tzcnt  %ebx,%eax
+[ 	]*[a-f0-9]+:	f3 0f bc 3b          	tzcnt  \(%ebx\),%edi
+
diff --git a/gas/testsuite/gas/i386/bmi.s b/gas/testsuite/gas/i386/bmi.s
new file mode 100644
index 0000000..f3f9c38
--- /dev/null
+++ b/gas/testsuite/gas/i386/bmi.s
@@ -0,0 +1,151 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %edi,%eax,%edi
+    ANDN     (%edx,%edi,8),%ecx,%ecx
+    ANDN     %ebx,%esp,%eax
+    ANDN     (%ebx,%ebx,4),%ebp,%edx
+    ANDN     0x36DC(%ecx),%edi,%esi
+    ANDN     (%ebx),%esi,%ebx
+    ANDN     %eax,%ebx,%edi
+    ANDN     %ecx,%eax,%eax
+    ANDN     -0x5162567A(%esi,%ebx,2),%edx,%esp
+    ANDN     (%esi),%edx,%ebp
+    ANDN     %edx,%esp,%eax
+    ANDN     %esi,%ebp,%edx
+    ANDN     -0xDEAD(%esi),%edi,%edi
+    ANDN     0xA(%ecx,%ebx),%esp,%esi
+    ANDN     (%eax),%edi,%eax
+    ANDN     -0x32(%ebx,%edx),%edi,%edi
+    BEXTR    %eax,(%ebx),%edi
+    BEXTR    %edi,(%ecx),%esi
+    BEXTR    %esp,%edi,%ecx
+    BEXTR    %ebp,%ecx,%eax
+    BEXTR    %ebx,%eax,%edi
+    BEXTR    %esi,%ebx,%edx
+    BEXTR    %edx,(%edi,%eax),%eax
+    BEXTR    %edi,(%edi),%ebp
+    BEXTR    %ecx,%esi,%esp
+    BEXTR    %edi,0x0(%eax),%ebx
+    BEXTR    %eax,(,%eax,1),%eax
+    BEXTR    %ebp,(%edx),%esp
+    BEXTR    %esi,0xA90F(,%eax,4),%ebp
+    BEXTR    %ebx,0x3(%ebx,%eax),%edi
+    BEXTR    %edi,0x3FFFFFFF(%ecx),%edi
+    BEXTR    %eax,(%edx,%edx),%eax
+    BLSI     %edi,%eax
+    BLSI     %eax,%edi
+    BLSI     (%ebx),%edi
+    BLSI     %esi,%esp
+    BLSI     %edx,%edx
+    BLSI     (%edi),%esi
+    BLSI     0x8(%ecx),%ebx
+    BLSI     (%edx),%eax
+    BLSI     (%ecx),%eax
+    BLSI     %ebp,%esp
+    BLSI     (%ecx,%ebx),%ebp
+    BLSI     0x3(,%ecx,2),%ecx
+    BLSI     (%edx,%eax),%eax
+    BLSI     (%ecx,%esi,2),%edi
+    BLSI     %eax,%edi
+    BLSI     (%eax),%eax
+    BLSMSK   %edx,%ebp
+    BLSMSK   %edi,%edi
+    BLSMSK   %eax,%eax
+    BLSMSK   %ebp,%edx
+    BLSMSK   %ebx,%esi
+    BLSMSK   (%edi),%ecx
+    BLSMSK   (%ecx),%ebx
+    BLSMSK   (,%eax,4),%esp
+    BLSMSK   %esp,%eax
+    BLSMSK   (%ebx),%eax
+    BLSMSK   (%ebx,%edx,8),%eax
+    BLSMSK   %esi,%esp
+    BLSMSK   -0x5EC21951(%edi,%edi,2),%edi
+    BLSMSK   (%eax,%ecx,2),%eax
+    BLSMSK   (%ebx,%ebx),%eax
+    BLSMSK   (%ebx,%eax,4),%edi
+    BLSR     0xCAFE(%edx,%edx,4),%esp
+    BLSR     %edi,%eax
+    BLSR     (,%ecx,8),%esi
+    BLSR     %eax,%edx
+    BLSR     (%esi),%ecx
+    BLSR     0x66B03551(,%ebx,4),%edi
+    BLSR     -0xF6(,%eax,4),%ebp
+    BLSR     %esi,%edi
+    BLSR     (%ebx),%eax
+    BLSR     0xF23A(%ebx,%edi,2),%ebx
+    BLSR     (%ecx),%edi
+    BLSR     0x5(,%eax),%eax
+    BLSR     %ebp,%eax
+    BLSR     0x41C3(%ebx,%eax),%eax
+    BLSR     0x3(,%ebx,2),%edi
+    BLSR     0x5A(%ecx),%edi
+    LZCNT    (%eax),%di
+    LZCNT    %di,%sp
+    LZCNT    (%esi),%ax
+    LZCNT    (,%ecx,8),%dx
+    LZCNT    %sp,%di
+    LZCNT    -0x9FF7(,%esi),%dx
+    LZCNT    0x6E4D(%ebx,%ecx,8),%di
+    LZCNT    (%edx),%bp
+    LZCNT    %cx,%cx
+    LZCNT    %bp,%bx
+    LZCNT    %si,%si
+    LZCNT    (,%eax,1),%ax
+    LZCNT    %ax,%di
+    LZCNT    %bx,%bx
+    LZCNT    %dx,%di
+    LZCNT    (%edi),%bx
+    LZCNT    %ebx,%ebx
+    LZCNT    %ecx,%edi
+    LZCNT    (%ecx,%ecx),%edx
+    LZCNT    %eax,%eax
+    LZCNT    %edi,%ecx
+    LZCNT    %esp,%edi
+    LZCNT    (,%edi,2),%esi
+    LZCNT    (%ebx),%eax
+    LZCNT    (%ebx,%eax,2),%edi
+    LZCNT    (%edi),%ebx
+    LZCNT    %ebp,%ebp
+    LZCNT    0xDEAD(%ebx),%esp
+    LZCNT    %esi,%eax
+    LZCNT    0x6305(%eax,%eax,1),%edi
+    LZCNT    -0x708C(%edi,%eax),%edi
+    LZCNT    (%esi),%eax
+    TZCNT    %bx,%bp
+    TZCNT    %di,%ax
+    TZCNT    %bp,%di
+    TZCNT    (%esi,%edx,1),%dx
+    TZCNT    (%edi),%cx
+    TZCNT    (%edx),%cx
+    TZCNT    %ax,%bx
+    TZCNT    (,%ecx,4),%sp
+    TZCNT    (%ecx),%si
+    TZCNT    (%ebx),%ax
+    TZCNT    (%edi,%eax,8),%di
+    TZCNT    (%ebx,%edi),%bx
+    TZCNT    %cx,%ax
+    TZCNT    -0xD89D(%ecx),%di
+    TZCNT    %bp,%ax
+    TZCNT    %bp,%ax
+    TZCNT    %eax,%edi
+    TZCNT    %edi,%esi
+    TZCNT    0x61(%ebx,%edi),%eax
+    TZCNT    %esi,%ebx
+    TZCNT    (%edx),%ebp
+    TZCNT    (%esi),%edx
+    TZCNT    (%edi,%ecx),%ecx
+    TZCNT    %ebp,%esi
+    TZCNT    (%edi),%eax
+    TZCNT    (%edi,%eax,1),%edi
+    TZCNT    (%eax,%eax),%esp
+    TZCNT    (%eax),%eax
+    TZCNT    -0x41(,%eax,2),%edi
+    TZCNT    -0x3FFFFFFF(,%ebx),%esp
+    TZCNT    %ebx,%eax
+    TZCNT    (%ebx),%edi
+
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3a966d7..aee5330 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -173,6 +173,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
+    run_dump_test "tbm"
+    run_dump_test "bmi"
     run_dump_test "f16c"
     run_dump_test "f16c-intel"
     run_dump_test "fsgs"
@@ -372,6 +374,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
+    run_dump_test "x86-64-tbm"
+    run_dump_test "x86-64-bmi"
     run_dump_test "x86-64-f16c"
     run_dump_test "x86-64-f16c-intel"
     run_dump_test "x86-64-fsgs"
diff --git a/gas/testsuite/gas/i386/tbm.d b/gas/testsuite/gas/i386/tbm.d
new file mode 100644
index 0000000..29a4b08
--- /dev/null
+++ b/gas/testsuite/gas/i386/tbm.d
@@ -0,0 +1,168 @@
+#objdump: -dw
+#name: i386 TBM
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	8f ea 78 10 1c f2 67 00 00 00 	bextr  \$0x67,\(%edx,%esi,8\),%ebx
+[ 	]*[a-f0-9]+:	8f ea 78 10 c6 00 00 00 00 	bextr  \$0x0,%esi,%eax
+[ 	]*[a-f0-9]+:	8f ea 78 10 f8 ff ff ff 7f 	bextr  \$0x7fffffff,%eax,%edi
+[ 	]*[a-f0-9]+:	8f ea 78 10 26 b2 35 00 00 	bextr  \$0x35b2,\(%esi\),%esp
+[ 	]*[a-f0-9]+:	8f ea 78 10 ef 86 9c 00 00 	bextr  \$0x9c86,%edi,%ebp
+[ 	]*[a-f0-9]+:	8f ea 78 10 c9 03 00 00 00 	bextr  \$0x3,%ecx,%ecx
+[ 	]*[a-f0-9]+:	8f ea 78 10 74 43 fd ee 00 00 00 	bextr  \$0xee,-0x3\(%ebx,%eax,2\),%esi
+[ 	]*[a-f0-9]+:	8f ea 78 10 23 55 00 00 00 	bextr  \$0x55,\(%ebx\),%esp
+[ 	]*[a-f0-9]+:	8f ea 78 10 12 e8 4e 00 00 	bextr  \$0x4ee8,\(%edx\),%edx
+[ 	]*[a-f0-9]+:	8f ea 78 10 fb 00 00 00 00 	bextr  \$0x0,%ebx,%edi
+[ 	]*[a-f0-9]+:	8f ea 78 10 f4 dc 00 00 00 	bextr  \$0xdc,%esp,%esi
+[ 	]*[a-f0-9]+:	8f ea 78 10 00 a9 00 00 00 	bextr  \$0xa9,\(%eax\),%eax
+[ 	]*[a-f0-9]+:	8f ea 78 10 ea 89 01 00 00 	bextr  \$0x189,%edx,%ebp
+[ 	]*[a-f0-9]+:	8f ea 78 10 0c 41 84 00 00 00 	bextr  \$0x84,\(%ecx,%eax,2\),%ecx
+[ 	]*[a-f0-9]+:	8f ea 78 10 04 01 fe ca 00 00 	bextr  \$0xcafe,\(%ecx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	8f ea 78 10 bc 3e 09 71 00 00 ad de 00 00 	bextr  \$0xdead,0x7109\(%esi,%edi,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 09       	blcfill \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 ce       	blcfill %esi,%edi
+[ 	]*[a-f0-9]+:	8f e9 70 01 c8       	blcfill %eax,%ecx
+[ 	]*[a-f0-9]+:	8f e9 48 01 cf       	blcfill %edi,%esi
+[ 	]*[a-f0-9]+:	8f e9 58 01 0e       	blcfill \(%esi\),%esp
+[ 	]*[a-f0-9]+:	8f e9 50 01 0b       	blcfill \(%ebx\),%ebp
+[ 	]*[a-f0-9]+:	8f e9 68 01 8c 03 95 1a 00 00 	blcfill 0x1a95\(%ebx,%eax,1\),%edx
+[ 	]*[a-f0-9]+:	8f e9 40 01 0a       	blcfill \(%edx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 cb       	blcfill %ebx,%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 8c 30 ce 00 00 00 	blcfill 0xce\(%eax,%esi,1\),%eax
+[ 	]*[a-f0-9]+:	8f e9 78 01 0c 1d 02 35 ff ff 	blcfill -0xcafe\(,%ebx,1\),%eax
+[ 	]*[a-f0-9]+:	8f e9 60 01 0c 05 a1 51 ff ff 	blcfill -0xae5f\(,%eax,1\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 40 01 c9       	blcfill %ecx,%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 cc       	blcfill %esp,%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 cd       	blcfill %ebp,%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 0c 4e    	blcfill \(%esi,%ecx,2\),%eax
+[ 	]*[a-f0-9]+:	8f e9 70 02 f0       	blci   %eax,%ecx
+[ 	]*[a-f0-9]+:	8f e9 60 02 f1       	blci   %ecx,%ebx
+[ 	]*[a-f0-9]+:	8f e9 78 02 34 45 b0 12 00 00 	blci   0x12b0\(,%eax,2\),%eax
+[ 	]*[a-f0-9]+:	8f e9 40 02 30       	blci   \(%eax\),%edi
+[ 	]*[a-f0-9]+:	8f e9 48 02 f7       	blci   %edi,%esi
+[ 	]*[a-f0-9]+:	8f e9 68 02 f4       	blci   %esp,%edx
+[ 	]*[a-f0-9]+:	8f e9 50 02 f6       	blci   %esi,%ebp
+[ 	]*[a-f0-9]+:	8f e9 78 02 f2       	blci   %edx,%eax
+[ 	]*[a-f0-9]+:	8f e9 58 02 b4 83 57 8d ff ff 	blci   -0x72a9\(%ebx,%eax,4\),%esp
+[ 	]*[a-f0-9]+:	8f e9 60 02 36       	blci   \(%esi\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 78 02 34 73    	blci   \(%ebx,%esi,2\),%eax
+[ 	]*[a-f0-9]+:	8f e9 68 02 33       	blci   \(%ebx\),%edx
+[ 	]*[a-f0-9]+:	8f e9 78 02 f3       	blci   %ebx,%eax
+[ 	]*[a-f0-9]+:	8f e9 70 02 b4 93 a2 e0 00 00 	blci   0xe0a2\(%ebx,%edx,4\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 02 37       	blci   \(%edi\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 02 34 45 ff ff ff 3f 	blci   0x3fffffff\(,%eax,2\),%eax
+[ 	]*[a-f0-9]+:	8f e9 70 01 ef       	blcic  %edi,%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 01 e8       	blcic  %eax,%edi
+[ 	]*[a-f0-9]+:	8f e9 60 01 28       	blcic  \(%eax\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 68 01 e9       	blcic  %ecx,%edx
+[ 	]*[a-f0-9]+:	8f e9 58 01 ee       	blcic  %esi,%esp
+[ 	]*[a-f0-9]+:	8f e9 50 01 2c 1d 02 35 ff ff 	blcic  -0xcafe\(,%ebx,1\),%ebp
+[ 	]*[a-f0-9]+:	8f e9 78 01 ed       	blcic  %ebp,%eax
+[ 	]*[a-f0-9]+:	8f e9 48 01 2e       	blcic  \(%esi\),%esi
+[ 	]*[a-f0-9]+:	8f e9 60 01 ec       	blcic  %esp,%ebx
+[ 	]*[a-f0-9]+:	8f e9 48 01 2c 3f    	blcic  \(%edi,%edi,1\),%esi
+[ 	]*[a-f0-9]+:	8f e9 50 01 2c 35 01 00 00 c0 	blcic  -0x3fffffff\(,%esi,1\),%ebp
+[ 	]*[a-f0-9]+:	8f e9 40 01 2b       	blcic  \(%ebx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 6c c7 08 	blcic  0x8\(%edi,%eax,8\),%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 a9 d1 4a 57 3a 	blcic  0x3a574ad1\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 ec       	blcic  %esp,%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 ea       	blcic  %edx,%edi
+[ 	]*[a-f0-9]+:	8f e9 40 02 48 0c    	blcmsk 0xc\(%eax\),%edi
+[ 	]*[a-f0-9]+:	8f e9 50 02 0c 16    	blcmsk \(%esi,%edx,1\),%ebp
+[ 	]*[a-f0-9]+:	8f e9 70 02 8f 00 22 3d e2 	blcmsk -0x1dc2de00\(%edi\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 58 02 c8       	blcmsk %eax,%esp
+[ 	]*[a-f0-9]+:	8f e9 78 02 0c 57    	blcmsk \(%edi,%edx,2\),%eax
+[ 	]*[a-f0-9]+:	8f e9 68 02 0b       	blcmsk \(%ebx\),%edx
+[ 	]*[a-f0-9]+:	8f e9 40 02 0a       	blcmsk \(%edx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 48 02 ce       	blcmsk %esi,%esi
+[ 	]*[a-f0-9]+:	8f e9 40 02 cc       	blcmsk %esp,%edi
+[ 	]*[a-f0-9]+:	8f e9 58 02 cf       	blcmsk %edi,%esp
+[ 	]*[a-f0-9]+:	8f e9 60 02 0c c3    	blcmsk \(%ebx,%eax,8\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 78 02 0f       	blcmsk \(%edi\),%eax
+[ 	]*[a-f0-9]+:	8f e9 78 02 ca       	blcmsk %edx,%eax
+[ 	]*[a-f0-9]+:	8f e9 40 02 4c 3b 67 	blcmsk 0x67\(%ebx,%edi,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 40 02 0c 05 a0 d8 12 aa 	blcmsk -0x55ed2760\(,%eax,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 02 0c 05 01 00 00 00 	blcmsk 0x1\(,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	8f e9 48 01 da       	blcs   %edx,%esi
+[ 	]*[a-f0-9]+:	8f e9 78 01 1b       	blcs   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 d8       	blcs   %eax,%edi
+[ 	]*[a-f0-9]+:	8f e9 58 01 9c 01 fe ca 00 00 	blcs   0xcafe\(%ecx,%eax,1\),%esp
+[ 	]*[a-f0-9]+:	8f e9 50 01 df       	blcs   %edi,%ebp
+[ 	]*[a-f0-9]+:	8f e9 70 01 1a       	blcs   \(%edx\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 01 1f       	blcs   \(%edi\),%edi
+[ 	]*[a-f0-9]+:	8f e9 60 01 9b 02 35 ff ff 	blcs   -0xcafe\(%ebx\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 70 01 dc       	blcs   %esp,%ecx
+[ 	]*[a-f0-9]+:	8f e9 68 01 de       	blcs   %esi,%edx
+[ 	]*[a-f0-9]+:	8f e9 40 01 18       	blcs   \(%eax\),%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 1c 0d 01 00 00 00 	blcs   0x1\(,%ecx,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 d9       	blcs   %ecx,%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 1c 13    	blcs   \(%ebx,%edx,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 9c 00 53 21 ff ff 	blcs   -0xdead\(%eax,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 1c 13    	blcs   \(%ebx,%edx,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 d0       	blsfill %eax,%eax
+[ 	]*[a-f0-9]+:	8f e9 48 01 d1       	blsfill %ecx,%esi
+[ 	]*[a-f0-9]+:	8f e9 40 01 10       	blsfill \(%eax\),%edi
+[ 	]*[a-f0-9]+:	8f e9 58 01 d3       	blsfill %ebx,%esp
+[ 	]*[a-f0-9]+:	8f e9 68 01 d2       	blsfill %edx,%edx
+[ 	]*[a-f0-9]+:	8f e9 70 01 11       	blsfill \(%ecx\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 01 d7       	blsfill %edi,%edi
+[ 	]*[a-f0-9]+:	8f e9 50 01 d5       	blsfill %ebp,%ebp
+[ 	]*[a-f0-9]+:	8f e9 40 01 17       	blsfill \(%edi\),%edi
+[ 	]*[a-f0-9]+:	8f e9 60 01 13       	blsfill \(%ebx\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 78 01 16       	blsfill \(%esi\),%eax
+[ 	]*[a-f0-9]+:	8f e9 78 01 14 80    	blsfill \(%eax,%eax,4\),%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 d6       	blsfill %esi,%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 94 18 21 a2 00 00 	blsfill 0xa221\(%eax,%ebx,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 14 00    	blsfill \(%eax,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	8f e9 70 01 14 5d f8 ff ff ff 	blsfill -0x8\(,%ebx,2\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 01 f0       	blsic  %eax,%edi
+[ 	]*[a-f0-9]+:	8f e9 60 01 36       	blsic  \(%esi\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 50 01 34 5d 00 00 00 00 	blsic  0x0\(,%ebx,2\),%ebp
+[ 	]*[a-f0-9]+:	8f e9 78 01 34 41    	blsic  \(%ecx,%eax,2\),%eax
+[ 	]*[a-f0-9]+:	8f e9 58 01 37       	blsic  \(%edi\),%esp
+[ 	]*[a-f0-9]+:	8f e9 78 01 33       	blsic  \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	8f e9 70 01 f7       	blsic  %edi,%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 01 74 18 51 	blsic  0x51\(%eax,%ebx,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 68 01 f4       	blsic  %esp,%edx
+[ 	]*[a-f0-9]+:	8f e9 68 01 74 3e 99 	blsic  -0x67\(%esi,%edi,1\),%edx
+[ 	]*[a-f0-9]+:	8f e9 40 01 31       	blsic  \(%ecx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 48 01 74 8e 67 	blsic  0x67\(%esi,%ecx,4\),%esi
+[ 	]*[a-f0-9]+:	8f e9 40 01 b4 d3 81 00 00 00 	blsic  0x81\(%ebx,%edx,8\),%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 74 11 0e 	blsic  0xe\(%ecx,%edx,1\),%edi
+[ 	]*[a-f0-9]+:	8f e9 58 01 70 3b    	blsic  0x3b\(%eax\),%esp
+[ 	]*[a-f0-9]+:	8f e9 40 01 f1       	blsic  %ecx,%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 f8       	t1mskc %eax,%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 ff       	t1mskc %edi,%edi
+[ 	]*[a-f0-9]+:	8f e9 70 01 39       	t1mskc \(%ecx\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 48 01 3c 33    	t1mskc \(%ebx,%esi,1\),%esi
+[ 	]*[a-f0-9]+:	8f e9 50 01 fa       	t1mskc %edx,%ebp
+[ 	]*[a-f0-9]+:	8f e9 68 01 3c 0d 00 00 00 00 	t1mskc 0x0\(,%ecx,1\),%edx
+[ 	]*[a-f0-9]+:	8f e9 58 01 3c b5 00 00 00 00 	t1mskc 0x0\(,%esi,4\),%esp
+[ 	]*[a-f0-9]+:	8f e9 70 01 fb       	t1mskc %ebx,%ecx
+[ 	]*[a-f0-9]+:	8f e9 60 01 3b       	t1mskc \(%ebx\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 40 01 fc       	t1mskc %esp,%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 38       	t1mskc \(%eax\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 01 f9       	t1mskc %ecx,%eax
+[ 	]*[a-f0-9]+:	8f e9 40 01 b8 ad de 00 00 	t1mskc 0xdead\(%eax\),%edi
+[ 	]*[a-f0-9]+:	8f e9 68 01 f9       	t1mskc %ecx,%edx
+[ 	]*[a-f0-9]+:	8f e9 60 01 3c 15 ad de 00 00 	t1mskc 0xdead\(,%edx,1\),%ebx
+[ 	]*[a-f0-9]+:	8f e9 40 01 3a       	t1mskc \(%edx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 58 01 23       	tzmsk  \(%ebx\),%esp
+[ 	]*[a-f0-9]+:	8f e9 78 01 e7       	tzmsk  %edi,%eax
+[ 	]*[a-f0-9]+:	8f e9 48 01 a7 02 35 ff ff 	tzmsk  -0xcafe\(%edi\),%esi
+[ 	]*[a-f0-9]+:	8f e9 68 01 24 3d 00 00 00 00 	tzmsk  0x0\(,%edi,1\),%edx
+[ 	]*[a-f0-9]+:	8f e9 50 01 e0       	tzmsk  %eax,%ebp
+[ 	]*[a-f0-9]+:	8f e9 60 01 e5       	tzmsk  %ebp,%ebx
+[ 	]*[a-f0-9]+:	8f e9 40 01 26       	tzmsk  \(%esi\),%edi
+[ 	]*[a-f0-9]+:	8f e9 70 01 21       	tzmsk  \(%ecx\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 40 01 24 45 00 00 00 00 	tzmsk  0x0\(,%eax,2\),%edi
+[ 	]*[a-f0-9]+:	8f e9 40 01 e7       	tzmsk  %edi,%edi
+[ 	]*[a-f0-9]+:	8f e9 68 01 e4       	tzmsk  %esp,%edx
+[ 	]*[a-f0-9]+:	8f e9 70 01 20       	tzmsk  \(%eax\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 78 01 24 3a    	tzmsk  \(%edx,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	8f e9 78 01 23       	tzmsk  \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	8f e9 78 01 a3 d9 c6 2a 2a 	tzmsk  0x2a2ac6d9\(%ebx\),%eax
+[ 	]*[a-f0-9]+:	8f e9 70 01 a4 01 47 e9 ff ff 	tzmsk  -0x16b9\(%ecx,%eax,1\),%ecx
diff --git a/gas/testsuite/gas/i386/tbm.s b/gas/testsuite/gas/i386/tbm.s
new file mode 100644
index 0000000..1f970ac
--- /dev/null
+++ b/gas/testsuite/gas/i386/tbm.s
@@ -0,0 +1,167 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    BEXTR    $0x67,(%edx,%esi,8),%ebx
+    BEXTR    $0x0,%esi,%eax
+    BEXTR    $0x7FFFFFFF,%eax,%edi
+    BEXTR    $0x35B2,(%esi),%esp
+    BEXTR    $0x9C86,%edi,%ebp
+    BEXTR    $0x3,%ecx,%ecx
+    BEXTR    $0xEE,-0x3(%ebx,%eax,2),%esi
+    BEXTR    $0x55,(%ebx),%esp
+    BEXTR    $0x4EE8,(%edx),%edx
+    BEXTR    $0x0,%ebx,%edi
+    BEXTR    $0xDC,%esp,%esi
+    BEXTR    $0xA9,(%eax),%eax
+    BEXTR    $0x189,%edx,%ebp
+    BEXTR    $0x84,0x0(%ecx,%eax,2),%ecx
+    BEXTR    $0xCAFE,(%ecx,%eax),%eax
+    BEXTR    $0xDEAD,0x7109(%esi,%edi),%edi
+    BLCFILL  (%ecx),%eax
+    BLCFILL  %esi,%edi
+    BLCFILL  %eax,%ecx
+    BLCFILL  %edi,%esi
+    BLCFILL  (%esi),%esp
+    BLCFILL  (%ebx),%ebp
+    BLCFILL  0x1A95(%ebx,%eax),%edx
+    BLCFILL  (%edx),%edi
+    BLCFILL  %ebx,%edi
+    BLCFILL  0xCE(%eax,%esi),%eax
+    BLCFILL  -0xCAFE(,%ebx,1),%eax
+    BLCFILL  -0xAE5F(,%eax),%ebx
+    BLCFILL  %ecx,%edi
+    BLCFILL  %esp,%eax
+    BLCFILL  %ebp,%edi
+    BLCFILL  (%esi,%ecx,2),%eax
+    BLCI     %eax,%ecx
+    BLCI     %ecx,%ebx
+    BLCI     0x12B0(,%eax,2),%eax
+    BLCI     (%eax),%edi
+    BLCI     %edi,%esi
+    BLCI     %esp,%edx
+    BLCI     %esi,%ebp
+    BLCI     %edx,%eax
+    BLCI     -0x72A9(%ebx,%eax,4),%esp
+    BLCI     (%esi),%ebx
+    BLCI     (%ebx,%esi,2),%eax
+    BLCI     (%ebx),%edx
+    BLCI     %ebx,%eax
+    BLCI     0xE0A2(%ebx,%edx,4),%ecx
+    BLCI     (%edi),%edi
+    BLCI     0x3FFFFFFF(,%eax,2),%eax
+    BLCIC    %edi,%ecx
+    BLCIC    %eax,%edi
+    BLCIC    (%eax),%ebx
+    BLCIC    %ecx,%edx
+    BLCIC    %esi,%esp
+    BLCIC    -0xCAFE(,%ebx),%ebp
+    BLCIC    %ebp,%eax
+    BLCIC    (%esi),%esi
+    BLCIC    %esp,%ebx
+    BLCIC    0x0(%edi,%edi,1),%esi
+    BLCIC    -0x3FFFFFFF(,%esi),%ebp
+    BLCIC    (%ebx),%edi
+    BLCIC    0x8(%edi,%eax,8),%eax
+    BLCIC    0x3A574AD1(%ecx),%edi
+    BLCIC    %esp,%edi
+    BLCIC    %edx,%edi
+    BLCMSK   0xC(%eax),%edi
+    BLCMSK   (%esi,%edx),%ebp
+    BLCMSK   -0x1DC2DE00(%edi),%ecx
+    BLCMSK   %eax,%esp
+    BLCMSK   0x0(%edi,%edx,2),%eax
+    BLCMSK   (%ebx),%edx
+    BLCMSK   (%edx),%edi
+    BLCMSK   %esi,%esi
+    BLCMSK   %esp,%edi
+    BLCMSK   %edi,%esp
+    BLCMSK   -0x0(%ebx,%eax,8),%ebx
+    BLCMSK   (%edi),%eax
+    BLCMSK   %edx,%eax
+    BLCMSK   0x67(%ebx,%edi),%edi
+    BLCMSK   -0x55ED2760(,%eax),%edi
+    BLCMSK   0x1(,%eax),%eax
+    BLCS     %edx,%esi
+    BLCS     (%ebx),%eax
+    BLCS     %eax,%edi
+    BLCS     0xCAFE(%ecx,%eax),%esp
+    BLCS     %edi,%ebp
+    BLCS     (%edx),%ecx
+    BLCS     (%edi),%edi
+    BLCS     -0xCAFE(%ebx),%ebx
+    BLCS     %esp,%ecx
+    BLCS     %esi,%edx
+    BLCS     (%eax),%edi
+    BLCS     0x1(,%ecx,1),%edi
+    BLCS     %ecx,%eax
+    BLCS     (%ebx,%edx),%edi
+    BLCS     -0xDEAD(%eax,%eax),%eax
+    BLCS     0x0(%ebx,%edx),%edi
+    BLSFILL  %eax,%eax
+    BLSFILL  %ecx,%esi
+    BLSFILL  (%eax),%edi
+    BLSFILL  %ebx,%esp
+    BLSFILL  %edx,%edx
+    BLSFILL  (%ecx),%ecx
+    BLSFILL  %edi,%edi
+    BLSFILL  %ebp,%ebp
+    BLSFILL  (%edi),%edi
+    BLSFILL  (%ebx),%ebx
+    BLSFILL  (%esi),%eax
+    BLSFILL  (%eax,%eax,4),%eax
+    BLSFILL  %esi,%edi
+    BLSFILL  0xA221(%eax,%ebx),%edi
+    BLSFILL  (%eax,%eax,1),%eax
+    BLSFILL  -0x8(,%ebx,2),%ecx
+    BLSIC    %eax,%edi
+    BLSIC    (%esi),%ebx
+    BLSIC    (,%ebx,2),%ebp
+    BLSIC    (%ecx,%eax,2),%eax
+    BLSIC    (%edi),%esp
+    BLSIC    (%ebx),%eax
+    BLSIC    %edi,%ecx
+    BLSIC    0x51(%eax,%ebx,1),%edi
+    BLSIC    %esp,%edx
+    BLSIC    -0x67(%esi,%edi),%edx
+    BLSIC    (%ecx),%edi
+    BLSIC    0x67(%esi,%ecx,4),%esi
+    BLSIC    0x81(%ebx,%edx,8),%edi
+    BLSIC    0xE(%ecx,%edx),%edi
+    BLSIC    0x3B(%eax),%esp
+    BLSIC    %ecx,%edi
+    T1MSKC   %eax,%eax
+    T1MSKC   %edi,%edi
+    T1MSKC   (%ecx),%ecx
+    T1MSKC   (%ebx,%esi,1),%esi
+    T1MSKC   %edx,%ebp
+    T1MSKC   0x0(,%ecx,1),%edx
+    T1MSKC   (,%esi,4),%esp
+    T1MSKC   %ebx,%ecx
+    T1MSKC   (%ebx),%ebx
+    T1MSKC   %esp,%edi
+    T1MSKC   (%eax),%edi
+    T1MSKC   %ecx,%eax
+    T1MSKC   0xDEAD(%eax),%edi
+    T1MSKC   %ecx,%edx
+    T1MSKC   0xDEAD(,%edx),%ebx
+    T1MSKC   (%edx),%edi
+    TZMSK    (%ebx),%esp
+    TZMSK    %edi,%eax
+    TZMSK    -0xCAFE(%edi),%esi
+    TZMSK    (,%edi,1),%edx
+    TZMSK    %eax,%ebp
+    TZMSK    %ebp,%ebx
+    TZMSK    (%esi),%edi
+    TZMSK    (%ecx),%ecx
+    TZMSK    (,%eax,2),%edi
+    TZMSK    %edi,%edi
+    TZMSK    %esp,%edx
+    TZMSK    (%eax),%ecx
+    TZMSK    (%edx,%edi),%eax
+    TZMSK    (%ebx),%eax
+    TZMSK    0x2A2AC6D9(%ebx),%eax
+    TZMSK    -0x16B9(%ecx,%eax,1),%ecx
+
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 9cd1306..36c335a 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+tbm+bmi
 #objdump: -dw
 #name: x86-64 arch 2
 
@@ -36,4 +36,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	8f e9 60 01 c9       	blcfill %ecx,%ebx
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index ddc0d40..5d574ee 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,3 +58,7 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# TBM
+blcfill %ecx,%ebx
+# BMI
+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.d b/gas/testsuite/gas/i386/x86-64-bmi.d
new file mode 100644
index 0000000..180e40f
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.d
@@ -0,0 +1,265 @@
+#objdump: -dw
+#name: x86-64 BMI
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	c4 c2 00 f2 c0       	andn   %r8d,%r15d,%eax
+[ 	]*[a-f0-9]+:	c4 62 78 f2 14 0e    	andn   \(%rsi,%rcx,1\),%eax,%r10d
+[ 	]*[a-f0-9]+:	67 c4 c2 48 f2 2e    	andn   \(%r14d\),%esi,%ebp
+[ 	]*[a-f0-9]+:	c4 42 40 f2 7d 00    	andn   0x0\(%r13\),%edi,%r15d
+[ 	]*[a-f0-9]+:	c4 42 18 f2 fe       	andn   %r14d,%r12d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 08 f2 3c 50 	andn   \(%r8d,%r10d,2\),%r14d,%edi
+[ 	]*[a-f0-9]+:	67 c4 42 28 f2 29    	andn   \(%r9d\),%r10d,%r13d
+[ 	]*[a-f0-9]+:	67 c4 22 70 f2 0c bd 00 00 00 00 	andn   0x0\(,%r15d,4\),%ecx,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 38 f2 24 85 00 00 00 00 	andn   0x0\(,%r8,4\),%r8d,%esp
+[ 	]*[a-f0-9]+:	c4 62 38 f2 24 07    	andn   \(%rdi,%rax,1\),%r8d,%r12d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f2 44 1d 00 	andn   0x0\(%r13d,%ebx,1\),%r11d,%eax
+[ 	]*[a-f0-9]+:	c4 e2 60 f2 f2       	andn   %edx,%ebx,%esi
+[ 	]*[a-f0-9]+:	c4 c2 58 f2 11       	andn   \(%r9\),%esp,%edx
+[ 	]*[a-f0-9]+:	c4 e2 00 f2 0f       	andn   \(%rdi\),%r15d,%ecx
+[ 	]*[a-f0-9]+:	67 c4 62 50 f2 37    	andn   \(%edi\),%ebp,%r14d
+[ 	]*[a-f0-9]+:	c4 a2 28 f2 84 83 fa b5 bb c6 	andn   -0x39444a06\(%rbx,%r8,4\),%r10d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f2 02    	andn   \(%r10d\),%rax,%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f2 16    	andn   \(%r14d\),%r15,%rdx
+[ 	]*[a-f0-9]+:	c4 02 d8 f2 bc 0f 93 5b 00 00 	andn   0x5b93\(%r15,%r9,1\),%rsp,%r15
+[ 	]*[a-f0-9]+:	c4 42 a0 f2 09       	andn   \(%r9\),%r11,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f2 3c 45 00 00 00 00 	andn   0x0\(,%eax,2\),%r15,%rdi
+[ 	]*[a-f0-9]+:	c4 62 c8 f2 dd       	andn   %rbp,%rsi,%r11
+[ 	]*[a-f0-9]+:	c4 42 e0 f2 45 00    	andn   0x0\(%r13\),%rbx,%r8
+[ 	]*[a-f0-9]+:	c4 62 c0 f2 d0       	andn   %rax,%rdi,%r10
+[ 	]*[a-f0-9]+:	c4 c2 98 f2 e4       	andn   %r12,%r12,%rsp
+[ 	]*[a-f0-9]+:	67 c4 62 a8 f2 3e    	andn   \(%esi\),%r10,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f2 3a    	andn   \(%edx\),%rax,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f2 37    	andn   \(%r15d\),%r8,%rsi
+[ 	]*[a-f0-9]+:	67 c4 42 80 f2 20    	andn   \(%r8d\),%r15,%r12
+[ 	]*[a-f0-9]+:	c4 c2 80 f2 ef       	andn   %r15,%r15,%rbp
+[ 	]*[a-f0-9]+:	c4 a2 d0 f2 0c e5 00 00 00 00 	andn   0x0\(,%r12,8\),%rbp,%rcx
+[ 	]*[a-f0-9]+:	c4 62 f0 f2 2a       	andn   \(%rdx\),%rcx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 00 f7 c0       	bextr  %r15d,%eax,%eax
+[ 	]*[a-f0-9]+:	c4 42 78 f7 fa       	bextr  %eax,%r10d,%r15d
+[ 	]*[a-f0-9]+:	67 c4 82 68 f7 0c cf 	bextr  %edx,\(%r15d,%r9d,8\),%ecx
+[ 	]*[a-f0-9]+:	c4 02 50 f7 54 3d 00 	bextr  %ebp,0x0\(%r13,%r15,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 20 f7 ef       	bextr  %r11d,%r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 82 00 f7 64 35 00 	bextr  %r15d,0x0\(%r13,%r14,1\),%esp
+[ 	]*[a-f0-9]+:	67 c4 02 30 f7 84 c3 ad de 00 00 	bextr  %r9d,0xdead\(%r11d,%r8d,8\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 20 f7 44 04 01 	bextr  %r11d,0x1\(%r12d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 42 28 f7 76 f4 	bextr  %r10d,-0xc\(%r14d\),%r14d
+[ 	]*[a-f0-9]+:	c4 62 78 f7 18       	bextr  %eax,\(%rax\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 c2 60 f7 14 24 	bextr  %ebx,\(%r12d\),%edx
+[ 	]*[a-f0-9]+:	67 c4 62 48 f7 28    	bextr  %esi,\(%eax\),%r13d
+[ 	]*[a-f0-9]+:	c4 e2 78 f7 dd       	bextr  %eax,%ebp,%ebx
+[ 	]*[a-f0-9]+:	c4 c2 78 f7 04 24    	bextr  %eax,\(%r12\),%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 50 f7 04 02 	bextr  %ebp,\(%r10d,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	67 c4 e2 10 f7 44 03 99 	bextr  %r13d,-0x67\(%ebx,%eax,1\),%eax
+[ 	]*[a-f0-9]+:	c4 82 a8 f7 84 7b fe ca 00 00 	bextr  %r10,0xcafe\(%r11,%r15,2\),%rax
+[ 	]*[a-f0-9]+:	c4 42 a8 f7 b1 fe ca 00 00 	bextr  %r10,0xcafe\(%r9\),%r14
+[ 	]*[a-f0-9]+:	c4 62 f8 f7 ff       	bextr  %rax,%rdi,%r15
+[ 	]*[a-f0-9]+:	67 c4 62 f8 f7 2a    	bextr  %rax,\(%edx\),%r13
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 17       	bextr  %rax,\(%r15\),%r10
+[ 	]*[a-f0-9]+:	c4 c2 80 f7 ea       	bextr  %r15,%r10,%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 f8 f7 3e    	bextr  %rax,\(%esi\),%rdi
+[ 	]*[a-f0-9]+:	c4 42 98 f7 e1       	bextr  %r12,%r9,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f7 dd       	bextr  %r8,%r13,%rbx
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 24 24    	bextr  %rax,\(%r12\),%rsp
+[ 	]*[a-f0-9]+:	c4 42 f8 f7 5d 00    	bextr  %rax,0x0\(%r13\),%r11
+[ 	]*[a-f0-9]+:	c4 c2 f8 f7 30       	bextr  %rax,\(%r8\),%rsi
+[ 	]*[a-f0-9]+:	c4 e2 f0 f7 d6       	bextr  %rcx,%rsi,%rdx
+[ 	]*[a-f0-9]+:	67 c4 02 b8 f7 7c 0a 03 	bextr  %r8,0x3\(%r10d,%r9d,1\),%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 07    	bextr  %rax,\(%r15d\),%rax
+[ 	]*[a-f0-9]+:	67 c4 c2 f8 f7 08    	bextr  %rax,\(%r8d\),%rcx
+[ 	]*[a-f0-9]+:	67 c4 a2 48 f3 1c 7d f3 ff ff ff 	blsi   -0xd\(,%r15d,2\),%esi
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 df       	blsi   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d8       	blsi   %eax,%eax
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 19       	blsi   \(%r9\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 dd       	blsi   %ebp,%r9d
+[ 	]*[a-f0-9]+:	c4 a2 68 f3 1c 4d 05 00 00 00 	blsi   0x5\(,%r9,2\),%edx
+[ 	]*[a-f0-9]+:	c4 a2 70 f3 1c 5d 96 ff ff ff 	blsi   -0x6a\(,%r11,2\),%ecx
+[ 	]*[a-f0-9]+:	67 c4 e2 50 f3 19    	blsi   \(%ecx\),%ebp
+[ 	]*[a-f0-9]+:	67 c4 e2 20 f3 1f    	blsi   \(%edi\),%r11d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 5f f9    	blsi   -0x7\(%rdi\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 c2 10 f3 18    	blsi   \(%r8d\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 60 f3 1a       	blsi   \(%r10\),%ebx
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 1c 05 fe ca 00 00 	blsi   0xcafe\(,%rax,1\),%edi
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 1e    	blsi   \(%esi\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 78 f3 d9       	blsi   %r9d,%eax
+[ 	]*[a-f0-9]+:	67 c4 c2 78 f3 5c 3a 99 	blsi   -0x67\(%r10d,%edi,1\),%eax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 5a 0f    	blsi   0xf\(%r10\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 df       	blsi   %r15,%rax
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 d8       	blsi   %rax,%rsp
+[ 	]*[a-f0-9]+:	67 c4 e2 a8 f3 18    	blsi   \(%eax\),%r10
+[ 	]*[a-f0-9]+:	67 c4 c2 90 f3 18    	blsi   \(%r8d\),%r13
+[ 	]*[a-f0-9]+:	67 c4 a2 88 f3 9c cf 85 00 00 00 	blsi   0x85\(%edi,%r9d,8\),%r14
+[ 	]*[a-f0-9]+:	c4 c2 98 f3 da       	blsi   %r10,%r12
+[ 	]*[a-f0-9]+:	c4 c2 b8 f3 1b       	blsi   \(%r11\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 b0 f3 9f 20 d6 db b8 	blsi   -0x472429e0\(%r15\),%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 e8 f3 1f    	blsi   \(%edi\),%rdx
+[ 	]*[a-f0-9]+:	67 c4 e2 e0 f3 1c 95 00 00 00 00 	blsi   0x0\(,%edx,4\),%rbx
+[ 	]*[a-f0-9]+:	67 c4 e2 c0 f3 1b    	blsi   \(%ebx\),%rdi
+[ 	]*[a-f0-9]+:	c4 c2 f0 f3 9a ad de 00 00 	blsi   0xdead\(%r10\),%rcx
+[ 	]*[a-f0-9]+:	c4 82 c0 f3 5c f7 1b 	blsi   0x1b\(%r15,%r14,8\),%rdi
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 1b       	blsi   \(%rbx\),%r11
+[ 	]*[a-f0-9]+:	c4 82 f8 f3 5c 08 0a 	blsi   0xa\(%r8,%r9,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 78 f3 d0       	blsmsk %eax,%eax
+[ 	]*[a-f0-9]+:	c4 a2 48 f3 14 8d 00 00 00 00 	blsmsk 0x0\(,%r9,4\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 00 f3 14 7d 00 00 00 00 	blsmsk 0x0\(,%edi,2\),%r15d
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 17       	blsmsk \(%rdi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 c2 70 f3 55 00 	blsmsk 0x0\(%r13d\),%ecx
+[ 	]*[a-f0-9]+:	c4 c2 08 f3 d1       	blsmsk %r9d,%r14d
+[ 	]*[a-f0-9]+:	c4 e2 38 f3 12       	blsmsk \(%rdx\),%r8d
+[ 	]*[a-f0-9]+:	67 c4 e2 18 f3 16    	blsmsk \(%esi\),%r12d
+[ 	]*[a-f0-9]+:	c4 c2 20 f3 94 15 c5 22 f8 65 	blsmsk 0x65f822c5\(%r13,%rdx,1\),%r11d
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 54 0b fd 	blsmsk -0x3\(%ebx,%ecx,1\),%r10d
+[ 	]*[a-f0-9]+:	c4 c2 50 f3 d7       	blsmsk %r15d,%ebp
+[ 	]*[a-f0-9]+:	c4 e2 10 f3 d6       	blsmsk %esi,%r13d
+[ 	]*[a-f0-9]+:	c4 c2 68 f3 17       	blsmsk \(%r15\),%edx
+[ 	]*[a-f0-9]+:	c4 c2 28 f3 16       	blsmsk \(%r14\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 d5       	blsmsk %ebp,%edi
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 14 21    	blsmsk \(%rcx,%r12,1\),%ebx
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 d7       	blsmsk %r15,%rdx
+[ 	]*[a-f0-9]+:	c4 e2 f8 f3 14 c8    	blsmsk \(%rax,%rcx,8\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 d1       	blsmsk %r9,%r15
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 17    	blsmsk \(%r15d\),%r8
+[ 	]*[a-f0-9]+:	c4 e2 80 f3 d0       	blsmsk %rax,%r15
+[ 	]*[a-f0-9]+:	c4 e2 98 f3 56 fd    	blsmsk -0x3\(%rsi\),%r12
+[ 	]*[a-f0-9]+:	c4 e2 c8 f3 14 12    	blsmsk \(%rdx,%rdx,1\),%rsi
+[ 	]*[a-f0-9]+:	c4 c2 e0 f3 16       	blsmsk \(%r14\),%rbx
+[ 	]*[a-f0-9]+:	c4 c2 c0 f3 17       	blsmsk \(%r15\),%rdi
+[ 	]*[a-f0-9]+:	c4 a2 d0 f3 14 25 24 ff ff ff 	blsmsk -0xdc\(,%r12,1\),%rbp
+[ 	]*[a-f0-9]+:	67 c4 e2 a0 f3 13    	blsmsk \(%ebx\),%r11
+[ 	]*[a-f0-9]+:	67 c4 a2 f8 f3 14 35 b8 43 00 00 	blsmsk 0x43b8\(,%r14d,1\),%rax
+[ 	]*[a-f0-9]+:	c4 e2 90 f3 d2       	blsmsk %rdx,%r13
+[ 	]*[a-f0-9]+:	c4 e2 b0 f3 d5       	blsmsk %rbp,%r9
+[ 	]*[a-f0-9]+:	67 c4 e2 d8 f3 10    	blsmsk \(%eax\),%rsp
+[ 	]*[a-f0-9]+:	67 c4 c2 80 f3 16    	blsmsk \(%r14d\),%r15
+[ 	]*[a-f0-9]+:	c4 c2 00 f3 cf       	blsr   %r15d,%r15d
+[ 	]*[a-f0-9]+:	c4 e2 30 f3 c8       	blsr   %eax,%r9d
+[ 	]*[a-f0-9]+:	67 c4 e2 08 f3 0c 15 01 00 00 00 	blsr   0x1\(,%edx,1\),%r14d
+[ 	]*[a-f0-9]+:	c4 e2 70 f3 ca       	blsr   %edx,%ecx
+[ 	]*[a-f0-9]+:	c4 a2 60 f3 0c 71    	blsr   \(%rcx,%r14,2\),%ebx
+[ 	]*[a-f0-9]+:	67 c4 a2 78 f3 0c 8d 4a 46 00 00 	blsr   0x464a\(,%r9d,4\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 58 f3 0e       	blsr   \(%rsi\),%esp
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 09    	blsr   \(%ecx\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 48 f3 0f    	blsr   \(%edi\),%esi
+[ 	]*[a-f0-9]+:	67 c4 e2 28 f3 0c 7d 00 00 00 00 	blsr   0x0\(,%edi,2\),%r10d
+[ 	]*[a-f0-9]+:	c4 e2 20 f3 0a       	blsr   \(%rdx\),%r11d
+[ 	]*[a-f0-9]+:	c4 c2 10 f3 0b       	blsr   \(%r11\),%r13d
+[ 	]*[a-f0-9]+:	c4 c2 38 f3 c9       	blsr   %r9d,%r8d
+[ 	]*[a-f0-9]+:	c4 e2 68 f3 cf       	blsr   %edi,%edx
+[ 	]*[a-f0-9]+:	67 c4 e2 78 f3 0b    	blsr   \(%ebx\),%eax
+[ 	]*[a-f0-9]+:	c4 e2 40 f3 08       	blsr   \(%rax\),%edi
+[ 	]*[a-f0-9]+:	c4 c2 80 f3 0b       	blsr   \(%r11\),%r15
+[ 	]*[a-f0-9]+:	67 c4 e2 b0 f3 0c 0d 03 00 00 00 	blsr   0x3\(,%ecx,1\),%r9
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 0e       	blsr   \(%rsi\),%rsp
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 4d 00    	blsr   0x0\(%r13\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 e8 f3 cf       	blsr   %r15,%rdx
+[ 	]*[a-f0-9]+:	67 c4 c2 b8 f3 0e    	blsr   \(%r14d\),%r8
+[ 	]*[a-f0-9]+:	c4 c2 f8 f3 0e       	blsr   \(%r14\),%rax
+[ 	]*[a-f0-9]+:	c4 c2 d0 f3 08       	blsr   \(%r8\),%rbp
+[ 	]*[a-f0-9]+:	c4 e2 a0 f3 ca       	blsr   %rdx,%r11
+[ 	]*[a-f0-9]+:	67 c4 e2 80 f3 0a    	blsr   \(%edx\),%r15
+[ 	]*[a-f0-9]+:	67 c4 a2 e0 f3 0c 25 7e 33 00 00 	blsr   0x337e\(,%r12d,1\),%rbx
+[ 	]*[a-f0-9]+:	c4 e2 f0 f3 08       	blsr   \(%rax\),%rcx
+[ 	]*[a-f0-9]+:	c4 e2 d8 f3 cd       	blsr   %rbp,%rsp
+[ 	]*[a-f0-9]+:	c4 e2 a8 f3 c8       	blsr   %rax,%r10
+[ 	]*[a-f0-9]+:	c4 82 98 f3 4c a5 67 	blsr   0x67\(%r13,%r12,4\),%r12
+[ 	]*[a-f0-9]+:	67 c4 a2 c0 f3 0c 2d 00 00 00 00 	blsr   0x0\(,%r13d,1\),%rdi
+[ 	]*[a-f0-9]+:	67 66 f3 46 0f bd 2c 05 5a 1f 00 00 	lzcnt  0x1f5a\(,%r8d,1\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd e0    	lzcnt  %ax,%r12w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 11    	lzcnt  \(%r9\),%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd c5    	lzcnt  %r13w,%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 3c c5 99 ff ff ff 	lzcnt  -0x67\(,%rax,8\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd 7c 15 00 	lzcnt  0x0\(%r13,%rdx,1\),%di
+[ 	]*[a-f0-9]+:	66 f3 0f bd 2f       	lzcnt  \(%rdi\),%bp
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 03    	lzcnt  \(%r11\),%r8w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bd f7    	lzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 26 	lzcnt  \(%r14d\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bd 09    	lzcnt  \(%rcx\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd 8c db e7 9a 00 00 	lzcnt  0x9ae7\(%r11,%rbx,8\),%r9w
+[ 	]*[a-f0-9]+:	66 f3 0f bd f6       	lzcnt  %si,%si
+[ 	]*[a-f0-9]+:	67 66 f3 0f bd 0b    	lzcnt  \(%ebx\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bd 1a 	lzcnt  \(%r10d\),%bx
+[ 	]*[a-f0-9]+:	66 f3 45 0f bd f1    	lzcnt  %r9w,%r14w
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 7d 00 	lzcnt  0x0\(%r13d\),%r15d
+[ 	]*[a-f0-9]+:	f3 0f bd e7          	lzcnt  %edi,%esp
+[ 	]*[a-f0-9]+:	67 f3 45 0f bd 2e    	lzcnt  \(%r14d\),%r13d
+[ 	]*[a-f0-9]+:	f3 41 0f bd 16       	lzcnt  \(%r14\),%edx
+[ 	]*[a-f0-9]+:	f3 45 0f bd df       	lzcnt  %r15d,%r11d
+[ 	]*[a-f0-9]+:	f3 0f bd c0          	lzcnt  %eax,%eax
+[ 	]*[a-f0-9]+:	f3 41 0f bd 30       	lzcnt  \(%r8\),%esi
+[ 	]*[a-f0-9]+:	f3 45 0f bd f9       	lzcnt  %r9d,%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd 04 24    	lzcnt  \(%r12\),%r8d
+[ 	]*[a-f0-9]+:	f3 41 0f bd e8       	lzcnt  %r8d,%ebp
+[ 	]*[a-f0-9]+:	67 f3 41 0f bd 1a    	lzcnt  \(%r10d\),%ebx
+[ 	]*[a-f0-9]+:	f3 41 0f bd 3c 0c    	lzcnt  \(%r12,%rcx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 44 0f bd 3f       	lzcnt  \(%rdi\),%r15d
+[ 	]*[a-f0-9]+:	67 f3 44 0f bd 3f    	lzcnt  \(%edi\),%r15d
+[ 	]*[a-f0-9]+:	f3 45 0f bd d4       	lzcnt  %r12d,%r10d
+[ 	]*[a-f0-9]+:	f3 42 0f bd 04 2d 00 00 00 00 	lzcnt  0x0\(,%r13,1\),%eax
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 6d 00 	lzcnt  0x0\(%r13d\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 02    	lzcnt  \(%r10d\),%r8
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 06    	lzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 4c 0f bd eb       	lzcnt  %rbx,%r13
+[ 	]*[a-f0-9]+:	f3 4d 0f bd 39       	lzcnt  \(%r9\),%r15
+[ 	]*[a-f0-9]+:	f3 48 0f bd ca       	lzcnt  %rdx,%rcx
+[ 	]*[a-f0-9]+:	f3 4a 0f bd 04 6d 00 00 00 00 	lzcnt  0x0\(,%r13,2\),%rax
+[ 	]*[a-f0-9]+:	67 f3 48 0f bd 30    	lzcnt  \(%eax\),%rsi
+[ 	]*[a-f0-9]+:	67 f3 49 0f bd 27    	lzcnt  \(%r15d\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4e 0f bd 1c bd 00 00 00 00 	lzcnt  0x0\(,%r15d,4\),%r11
+[ 	]*[a-f0-9]+:	f3 4d 0f bd e7       	lzcnt  %r15,%r12
+[ 	]*[a-f0-9]+:	f3 48 0f bd 17       	lzcnt  \(%rdi\),%rdx
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bd 0c 24 	lzcnt  \(%r12d\),%r9
+[ 	]*[a-f0-9]+:	f3 4d 0f bd d3       	lzcnt  %r11,%r10
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bd 2c dd fe ca 00 00 	lzcnt  0xcafe\(,%ebx,8\),%r13
+[ 	]*[a-f0-9]+:	f3 48 0f bd c0       	lzcnt  %rax,%rax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc f2    	tzcnt  %r10w,%r14w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 86 7a 73 00 00 	tzcnt  0x737a\(%r14\),%ax
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc d0    	tzcnt  %ax,%r10w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc f7    	tzcnt  %r15w,%si
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 3c 24 	tzcnt  \(%r12\),%r15w
+[ 	]*[a-f0-9]+:	67 66 f3 0f bc 22    	tzcnt  \(%edx\),%sp
+[ 	]*[a-f0-9]+:	66 f3 44 0f bc 28    	tzcnt  \(%rax\),%r13w
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc ec    	tzcnt  %r12w,%bp
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 81 ad 3c 00 00 	tzcnt  0x3cad\(%r9d\),%ax
+[ 	]*[a-f0-9]+:	66 f3 41 0f bc 44 12 06 	tzcnt  0x6\(%r10,%rdx,1\),%ax
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc dd    	tzcnt  %r13w,%r11w
+[ 	]*[a-f0-9]+:	67 66 f3 43 0f bc 0c 32 	tzcnt  \(%r10d,%r14d,1\),%cx
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc a4 9a 44 ae d0 4c 	tzcnt  0x4cd0ae44\(%r10d,%ebx,4\),%r12w
+[ 	]*[a-f0-9]+:	67 66 f3 45 0f bc 3f 	tzcnt  \(%r15d\),%r15w
+[ 	]*[a-f0-9]+:	66 f3 45 0f bc 08    	tzcnt  \(%r8\),%r9w
+[ 	]*[a-f0-9]+:	67 66 f3 41 0f bc 01 	tzcnt  \(%r9d\),%ax
+[ 	]*[a-f0-9]+:	f3 41 0f bc 10       	tzcnt  \(%r8\),%edx
+[ 	]*[a-f0-9]+:	67 f3 44 0f bc 1e    	tzcnt  \(%esi\),%r11d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 02       	tzcnt  \(%r10\),%eax
+[ 	]*[a-f0-9]+:	f3 45 0f bc 7c 16 c3 	tzcnt  -0x3d\(%r14,%rdx,1\),%r15d
+[ 	]*[a-f0-9]+:	f3 41 0f bc 75 00    	tzcnt  0x0\(%r13\),%esi
+[ 	]*[a-f0-9]+:	f3 44 0f bc 27       	tzcnt  \(%rdi\),%r12d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 01       	tzcnt  \(%ecx\),%eax
+[ 	]*[a-f0-9]+:	f3 47 0f bc ac e9 bc 9a ff ff 	tzcnt  -0x6544\(%r9,%r13,8\),%r13d
+[ 	]*[a-f0-9]+:	f3 0f bc e0          	tzcnt  %eax,%esp
+[ 	]*[a-f0-9]+:	f3 45 0f bc c7       	tzcnt  %r15d,%r8d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 3c 0d f1 ff ff ff 	tzcnt  -0xf\(,%ecx,1\),%edi
+[ 	]*[a-f0-9]+:	f3 45 0f bc 09       	tzcnt  \(%r9\),%r9d
+[ 	]*[a-f0-9]+:	f3 0f bc 21          	tzcnt  \(%rcx\),%esp
+[ 	]*[a-f0-9]+:	f3 43 0f bc 2c 10    	tzcnt  \(%r8,%r10,1\),%ebp
+[ 	]*[a-f0-9]+:	f3 46 0f bc 34 17    	tzcnt  \(%rdi,%r10,1\),%r14d
+[ 	]*[a-f0-9]+:	67 f3 0f bc 30       	tzcnt  \(%eax\),%esi
+[ 	]*[a-f0-9]+:	67 f3 4c 0f bc 0f    	tzcnt  \(%edi\),%r9
+[ 	]*[a-f0-9]+:	f3 49 0f bc 29       	tzcnt  \(%r9\),%rbp
+[ 	]*[a-f0-9]+:	67 f3 4d 0f bc 3c 9f 	tzcnt  \(%r15d,%ebx,4\),%r15
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 26       	tzcnt  \(%r14\),%r12
+[ 	]*[a-f0-9]+:	f3 4e 0f bc 14 05 0e 8a f2 62 	tzcnt  0x62f28a0e\(,%r8,1\),%r10
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 34 30    	tzcnt  \(%r8,%rsi,1\),%r14
+[ 	]*[a-f0-9]+:	67 f3 48 0f bc 06    	tzcnt  \(%esi\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc c5       	tzcnt  %r13,%rax
+[ 	]*[a-f0-9]+:	f3 4d 0f bc 81 6c 3d 00 00 	tzcnt  0x3d6c\(%r9\),%r8
+[ 	]*[a-f0-9]+:	f3 4c 0f bc f8       	tzcnt  %rax,%r15
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 24 4d 00 00 00 00 	tzcnt  0x0\(,%r9,2\),%rsp
+[ 	]*[a-f0-9]+:	67 f3 4a 0f bc 1c e5 00 00 00 00 	tzcnt  0x0\(,%r12d,8\),%rbx
+[ 	]*[a-f0-9]+:	f3 4c 0f bc 1c 16    	tzcnt  \(%rsi,%rdx,1\),%r11
+[ 	]*[a-f0-9]+:	f3 4a 0f bc 3c a9    	tzcnt  \(%rcx,%r13,4\),%rdi
+[ 	]*[a-f0-9]+:	f3 49 0f bc 44 c3 f1 	tzcnt  -0xf\(%r11,%rax,8\),%rax
+[ 	]*[a-f0-9]+:	f3 49 0f bc 00       	tzcnt  \(%r8\),%rax
+
diff --git a/gas/testsuite/gas/i386/x86-64-bmi.s b/gas/testsuite/gas/i386/x86-64-bmi.s
new file mode 100644
index 0000000..e4059ec
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bmi.s
@@ -0,0 +1,263 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    ANDN     %eax,%r15d,%eax
+    ANDN     (%rsi,%rcx),%eax,%r10d
+    ANDN     (%r14d),%esi,%ebp
+    ANDN     (%r13),%edi,%r15d
+    ANDN     %esi,%r12d,%r15d
+    ANDN     (%r8d,%r10d,2),%r14d,%edi
+    ANDN     (%r9d),%r10d,%r13d
+    ANDN     (,%r15d,4),%ecx,%r9d
+    ANDN     (,%r8,4),%r8d,%esp
+    ANDN     (%rdi,%rax),%r8d,%r12d
+    ANDN     (%r13d,%ebx),%r11d,%eax
+    ANDN     %edx,%ebx,%esi
+    ANDN     (%r9),%esp,%edx
+    ANDN     (%rdi),%r15d,%ecx
+    ANDN     (%edi),%ebp,%r14d
+    ANDN     -0x39444A06(%rbx,%r8,4),%r10d,%eax
+    ANDN     (%r10d),%rax,%rax
+    ANDN     (%r14d),%r15,%rdx
+    ANDN     0x5B93(%r15,%r9),%rsp,%r15
+    ANDN     (%r9),%r11,%r9
+    ANDN     (,%eax,2),%r15,%rdi
+    ANDN     %rbp,%rsi,%r11
+    ANDN     (%r13),%rbx,%r8
+    ANDN     %rax,%rdi,%r10
+    ANDN     %rsp,%r12,%rsp
+    ANDN     (%esi),%r10,%r15
+    ANDN     (%edx),%rax,%r15
+    ANDN     (%r15d),%r8,%rsi
+    ANDN     (%r8d),%r15,%r12
+    ANDN     %rdi,%r15,%rbp
+    ANDN     (,%r12,8),%rbp,%rcx
+    ANDN     (%rdx),%rcx,%r13
+    BEXTR    %r15d,%eax,%eax
+    BEXTR    %eax,%r10d,%r15d
+    BEXTR    %edx,(%r15d,%r9d,8),%ecx
+    BEXTR    %ebp,(%r13,%r15),%r10d
+    BEXTR    %r11d,%r15d,%ebp
+    BEXTR    %r15d,(%r13,%r14),%esp
+    BEXTR    %r9d,0xDEAD(%r11d,%r8d,8),%r8d
+    BEXTR    %r11d,0x1(%r12d,%eax),%eax
+    BEXTR    %r10d,-0xC(%r14d),%r14d
+    BEXTR    %eax,(%rax),%r11d
+    BEXTR    %ebx,(%r12d),%edx
+    BEXTR    %esi,(%eax),%r13d
+    BEXTR    %eax,%ebp,%ebx
+    BEXTR    %eax,(%r12),%eax
+    BEXTR    %ebp,(%r10d,%eax),%eax
+    BEXTR    %r13d,-0x67(%ebx,%eax),%eax
+    BEXTR    %r15,0xCAFE(%r11,%r15,2),%rax
+    BEXTR    %r14,0xCAFE(%r9),%r14
+    BEXTR    %rdi,%rax,%r15
+    BEXTR    %rax,(%edx),%r13
+    BEXTR    %rdx,(%r15),%r10
+    BEXTR    %r10,%r15,%rbp
+    BEXTR    %r12,(%esi),%rdi
+    BEXTR    %rcx,%r12,%r12
+    BEXTR    %rbp,%r8,%rbx
+    BEXTR    %rbx,(%r12),%rsp
+    BEXTR    %r9,(%r13),%r11
+    BEXTR    %r11,(%r8),%rsi
+    BEXTR    %rsi,%rcx,%rdx
+    BEXTR    %r13,0x3(%r10d,%r9d,1),%r15
+    BEXTR    %rax,(%r15d),%rax
+    BEXTR    %r15,(%r8d),%rcx
+    BLSI     -0xD(,%r15d,2),%esi
+    BLSI     %r15d,%r15d
+    BLSI     %eax,%eax
+    BLSI     (%r9),%r10d
+    BLSI     %ebp,%r9d
+    BLSI     0x5(,%r9,2),%edx
+    BLSI     -0x6A(,%r11,2),%ecx
+    BLSI     (%ecx),%ebp
+    BLSI     (%edi),%r11d
+    BLSI     -0x7(%rdi),%r8d
+    BLSI     (%r8d),%r13d
+    BLSI     (%r10),%ebx
+    BLSI     0xCAFE(,%rax),%edi
+    BLSI     (%esi),%eax
+    BLSI     %r9d,%eax
+    BLSI     -0x67(%r10d,%edi,1),%eax
+    BLSI     0xF(%r10),%r15
+    BLSI     %r15,%rax
+    BLSI     %rax,%rsp
+    BLSI     (%eax),%r10
+    BLSI     (%r8d),%r13
+    BLSI     0x85(%edi,%r9d,8),%r14
+    BLSI     %r10,%r12
+    BLSI     (%r11),%r8
+    BLSI     -0x472429E0(%r15),%r9
+    BLSI     (%edi),%rdx
+    BLSI     (,%edx,4),%rbx
+    BLSI     (%ebx),%rdi
+    BLSI     0xDEAD(%r10),%rcx
+    BLSI     0x1B(%r15,%r14,8),%rdi
+    BLSI     (%rbx),%r11
+    BLSI     0xA(%r8,%r9),%rax
+    BLSMSK   %eax,%eax
+    BLSMSK   (,%r9,4),%esi
+    BLSMSK   (,%edi,2),%r15d
+    BLSMSK   (%rdi),%esp
+    BLSMSK   (%r13d),%ecx
+    BLSMSK   %r9d,%r14d
+    BLSMSK   (%rdx),%r8d
+    BLSMSK   (%esi),%r12d
+    BLSMSK   0x65F822C5(%r13,%rdx),%r11d
+    BLSMSK   -0x3(%ebx,%ecx,1),%r10d
+    BLSMSK   %r15d,%ebp
+    BLSMSK   %esi,%r13d
+    BLSMSK   (%r15),%edx
+    BLSMSK   (%r14),%r10d
+    BLSMSK   %ebp,%edi
+    BLSMSK   (%rcx,%r12),%ebx
+    BLSMSK   %r15,%rdx
+    BLSMSK   (%rax,%rcx,8),%rax
+    BLSMSK   %r9,%r15
+    BLSMSK   (%r15d),%r8
+    BLSMSK   %rax,%r15
+    BLSMSK   -0x3(%rsi),%r12
+    BLSMSK   -0x0(%rdx,%rdx),%rsi
+    BLSMSK   (%r14),%rbx
+    BLSMSK   (%r15),%rdi
+    BLSMSK   -0xDC(,%r12),%rbp
+    BLSMSK   (%ebx),%r11
+    BLSMSK   0x43B8(,%r14d),%rax
+    BLSMSK   %rdx,%r13
+    BLSMSK   %rbp,%r9
+    BLSMSK   (%eax),%rsp
+    BLSMSK   (%r14d),%r15
+    BLSR     %r15d,%r15d
+    BLSR     %eax,%r9d
+    BLSR     0x1(,%edx),%r14d
+    BLSR     %edx,%ecx
+    BLSR     (%rcx,%r14,2),%ebx
+    BLSR     0x464A(,%r9d,4),%eax
+    BLSR     (%rsi),%esp
+    BLSR     (%ecx),%esi
+    BLSR     (%edi),%esi
+    BLSR     (,%edi,2),%r10d
+    BLSR     (%rdx),%r11d
+    BLSR     (%r11),%r13d
+    BLSR     %r9d,%r8d
+    BLSR     %edi,%edx
+    BLSR     (%ebx),%eax
+    BLSR     (%rax),%edi
+    BLSR     (%r11),%r15
+    BLSR     0x3(,%ecx),%r9
+    BLSR     (%rsi),%rsp
+    BLSR     (%r13),%rax
+    BLSR     %r15,%rdx
+    BLSR     (%r14d),%r8
+    BLSR     (%r14),%rax
+    BLSR     (%r8),%rbp
+    BLSR     %rdx,%r11
+    BLSR     (%edx),%r15
+    BLSR     0x337E(,%r12d),%rbx
+    BLSR     (%rax),%rcx
+    BLSR     %rbp,%rsp
+    BLSR     %rax,%r10
+    BLSR     0x67(%r13,%r12,4),%r12
+    BLSR     (,%r13d,1),%rdi
+    LZCNT    0x1F5A(,%r8d),%r13w
+    LZCNT    %ax,%r12w
+    LZCNT    (%r9),%r10w
+    LZCNT    %r13w,%ax
+    LZCNT    -0x67(,%rax,8),%r15w
+    LZCNT    (%r13,%rdx),%di
+    LZCNT    (%rdi),%bp
+    LZCNT    (%r11),%r8w
+    LZCNT    %r15w,%si
+    LZCNT    (%r14d),%sp
+    LZCNT    (%rcx),%r9w
+    LZCNT    0x9AE7(%r11,%rbx,8),%r9w
+    LZCNT    %si,%si
+    LZCNT    (%ebx),%cx
+    LZCNT    (%r10d),%bx
+    LZCNT    %r9w,%r14w
+    LZCNT    (%r13d),%r15d
+    LZCNT    %edi,%esp
+    LZCNT    (%r14d),%r13d
+    LZCNT    (%r14),%edx
+    LZCNT    %r15d,%r11d
+    LZCNT    %eax,%eax
+    LZCNT    (%r8),%esi
+    LZCNT    %r9d,%r15d
+    LZCNT    (%r12),%r8d
+    LZCNT    %r8d,%ebp
+    LZCNT    (%r10d),%ebx
+    LZCNT    (%r12,%rcx),%edi
+    LZCNT    (%rdi),%r15d
+    LZCNT    (%edi),%r15d
+    LZCNT    %r12d,%r10d
+    LZCNT    (,%r13,1),%eax
+    LZCNT    (%r13d),%rbp
+    LZCNT    (%r10d),%r8
+    LZCNT    (%esi),%rax
+    LZCNT    %rbx,%r13
+    LZCNT    (%r9),%r15
+    LZCNT    %rdx,%rcx
+    LZCNT    (,%r13,2),%rax
+    LZCNT    (%eax),%rsi
+    LZCNT    (%r15d),%rsp
+    LZCNT    (,%r15d,4),%r11
+    LZCNT    %r15,%r12
+    LZCNT    (%rdi),%rdx
+    LZCNT    (%r12d),%r9
+    LZCNT    %r11,%r10
+    LZCNT    0xCAFE(,%ebx,8),%r13
+    LZCNT    %rax,%rax
+    TZCNT    %r10w,%r14w
+    TZCNT    0x737A(%r14),%ax
+    TZCNT    %ax,%r10w
+    TZCNT    %r15w,%si
+    TZCNT    (%r12),%r15w
+    TZCNT    (%edx),%sp
+    TZCNT    (%rax),%r13w
+    TZCNT    %r12w,%bp
+    TZCNT    0x3CAD(%r9d),%ax
+    TZCNT    0x6(%r10,%rdx),%ax
+    TZCNT    %r13w,%r11w
+    TZCNT    (%r10d,%r14d),%cx
+    TZCNT    0x4CD0AE44(%r10d,%ebx,4),%r12w
+    TZCNT    (%r15d),%r15w
+    TZCNT    (%r8),%r9w
+    TZCNT    (%r9d),%ax
+    TZCNT    (%r8),%edx
+    TZCNT    (%esi),%r11d
+    TZCNT    (%r10),%eax
+    TZCNT    -0x3D(%r14,%rdx),%r15d
+    TZCNT    (%r13),%esi
+    TZCNT    (%rdi),%r12d
+    TZCNT    (%ecx),%eax
+    TZCNT    -0x6544(%r9,%r13,8),%r13d
+    TZCNT    %eax,%esp
+    TZCNT    %r15d,%r8d
+    TZCNT    -0xF(,%ecx),%edi
+    TZCNT    (%r9),%r9d
+    TZCNT    (%rcx),%esp
+    TZCNT    (%r8,%r10),%ebp
+    TZCNT    (%rdi,%r10),%r14d
+    TZCNT    (%eax),%esi
+    TZCNT    (%edi),%r9
+    TZCNT    (%r9),%rbp
+    TZCNT    (%r15d,%ebx,4),%r15
+    TZCNT    (%r14),%r12
+    TZCNT    0x62F28A0E(,%r8),%r10
+    TZCNT    (%r8,%rsi),%r14
+    TZCNT    (%esi),%rax
+    TZCNT    %r13,%rax
+    TZCNT    0x3D6C(%r9),%r8
+    TZCNT    %rax,%r15
+    TZCNT    (,%r9,2),%rsp
+    TZCNT    (,%r12d,8),%rbx
+    TZCNT    (%rsi,%rdx),%r11
+    TZCNT    (%rcx,%r13,4),%rdi
+    TZCNT    -0xF(%r11,%rax,8),%rax
+    TZCNT    (%r8),%rax
+
diff --git a/gas/testsuite/gas/i386/x86-64-tbm.d b/gas/testsuite/gas/i386/x86-64-tbm.d
new file mode 100644
index 0000000..b6807bb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-tbm.d
@@ -0,0 +1,328 @@
+#objdump: -dw
+#name: x86-64 TBM
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	8f 6a 78 10 f8 00 00 00 00 	bextr  \$0x0,%eax,%r15d
+[ 	]*[a-f0-9]+:	8f 4a 78 10 d7 f1 4d 00 00 	bextr  \$0x4df1,%r15d,%r10d
+[ 	]*[a-f0-9]+:	8f 4a 78 10 f5 92 5e a5 2d 	bextr  \$0x2da55e92,%r13d,%r14d
+[ 	]*[a-f0-9]+:	67 8f 8a 78 10 44 7d 06 ff ff ff 7f 	bextr  \$0x7fffffff,0x6\(%r13d,%r15d,2\),%eax
+[ 	]*[a-f0-9]+:	8f ca 78 10 eb 61 f7 1e 25 	bextr  \$0x251ef761,%r11d,%ebp
+[ 	]*[a-f0-9]+:	8f 6a 78 10 3c d7 39 2b 00 00 	bextr  \$0x2b39,\(%rdi,%rdx,8\),%r15d
+[ 	]*[a-f0-9]+:	8f 2a 78 10 0c 35 ad de 00 00 92 00 00 00 	bextr  \$0x92,0xdead\(,%r14,1\),%r9d
+[ 	]*[a-f0-9]+:	8f ca 78 10 75 00 87 68 00 00 	bextr  \$0x6887,0x0\(%r13\),%esi
+[ 	]*[a-f0-9]+:	67 8f ca 78 10 09 0d 00 00 00 	bextr  \$0xd,\(%r9d\),%ecx
+[ 	]*[a-f0-9]+:	8f ea 78 10 1c 05 d8 40 00 00 2b 00 00 00 	bextr  \$0x2b,0x40d8\(,%rax,1\),%ebx
+[ 	]*[a-f0-9]+:	8f 4a 78 10 00 2d ea 00 00 	bextr  \$0xea2d,\(%r8\),%r8d
+[ 	]*[a-f0-9]+:	67 8f 4a 78 10 65 00 6c 00 00 00 	bextr  \$0x6c,0x0\(%r13d\),%r12d
+[ 	]*[a-f0-9]+:	8f 6a 78 10 1c 0d 8f 8c 00 00 3b 9e 00 00 	bextr  \$0x9e3b,0x8c8f\(,%rcx,1\),%r11d
+[ 	]*[a-f0-9]+:	67 8f ca 78 10 24 02 0f 00 00 00 	bextr  \$0xf,\(%r10d,%eax,1\),%esp
+[ 	]*[a-f0-9]+:	67 8f aa 78 10 3c cd 00 00 00 00 ad de 00 00 	bextr  \$0xdead,0x0\(,%r9d,8\),%edi
+[ 	]*[a-f0-9]+:	8f ca 78 10 c0 fe ca 00 00 	bextr  \$0xcafe,%r8d,%eax
+[ 	]*[a-f0-9]+:	8f 4a f8 10 81 bc 10 00 00 b9 3b 26 7d 	bextr  \$0x7d263bb9,0x10bc\(%r9\),%r8
+[ 	]*[a-f0-9]+:	67 8f 2a f8 10 3c 65 00 00 00 00 67 00 00 00 	bextr  \$0x67,0x0\(,%r12d,2\),%r15
+[ 	]*[a-f0-9]+:	8f ea f8 10 c0 00 00 00 00 	bextr  \$0x0,%rax,%rax
+[ 	]*[a-f0-9]+:	67 8f ea f8 10 26 9b 53 00 00 	bextr  \$0x539b,\(%esi\),%rsp
+[ 	]*[a-f0-9]+:	8f ca f8 10 08 ff ff ff 7f 	bextr  \$0x7fffffff,\(%r8\),%rcx
+[ 	]*[a-f0-9]+:	67 8f ea f8 10 04 3d ff ff ff 3f 01 00 00 00 	bextr  \$0x1,0x3fffffff\(,%edi,1\),%rax
+[ 	]*[a-f0-9]+:	67 8f 8a f8 10 b4 30 84 dd ff ff 9e 00 00 00 	bextr  \$0x9e,-0x227c\(%r8d,%r14d,1\),%rsi
+[ 	]*[a-f0-9]+:	8f ca f8 10 c7 64 c4 a6 02 	bextr  \$0x2a6c464,%r15,%rax
+[ 	]*[a-f0-9]+:	67 8f 2a f8 10 4c 1f 02 04 00 00 00 	bextr  \$0x4,0x2\(%edi,%r11d,1\),%r9
+[ 	]*[a-f0-9]+:	8f ea f8 10 ef 02 00 00 00 	bextr  \$0x2,%rdi,%rbp
+[ 	]*[a-f0-9]+:	67 8f ca f8 10 14 16 fb 7e 1e 78 	bextr  \$0x781e7efb,\(%r14d,%edx,1\),%rdx
+[ 	]*[a-f0-9]+:	8f 0a f8 10 ac 2b 68 db 00 00 39 40 cb 70 	bextr  \$0x70cb4039,0xdb68\(%r11,%r13,1\),%r13
+[ 	]*[a-f0-9]+:	8f 4a f8 10 16 73 13 00 00 	bextr  \$0x1373,\(%r14\),%r10
+[ 	]*[a-f0-9]+:	67 8f 2a f8 10 3c af 6d 55 00 00 	bextr  \$0x556d,\(%edi,%r13d,4\),%r15
+[ 	]*[a-f0-9]+:	8f 4a f8 10 11 00 00 00 00 	bextr  \$0x0,\(%r9\),%r10
+[ 	]*[a-f0-9]+:	8f 6a f8 10 1f ef ee ee 7b 	bextr  \$0x7beeeeef,\(%rdi\),%r11
+[ 	]*[a-f0-9]+:	8f e9 00 01 cc       	blcfill %esp,%r15d
+[ 	]*[a-f0-9]+:	8f a9 68 01 0c a6    	blcfill \(%rsi,%r12,4\),%edx
+[ 	]*[a-f0-9]+:	67 8f e9 08 01 08    	blcfill \(%eax\),%r14d
+[ 	]*[a-f0-9]+:	8f a9 50 01 0c ad 00 00 00 00 	blcfill 0x0\(,%r13,4\),%ebp
+[ 	]*[a-f0-9]+:	67 8f c9 78 01 0e    	blcfill \(%r14d\),%eax
+[ 	]*[a-f0-9]+:	8f c9 30 01 0b       	blcfill \(%r11\),%r9d
+[ 	]*[a-f0-9]+:	8f a9 10 01 0c 45 ad de 00 00 	blcfill 0xdead\(,%r8,2\),%r13d
+[ 	]*[a-f0-9]+:	8f c9 00 01 cf       	blcfill %r15d,%r15d
+[ 	]*[a-f0-9]+:	8f c9 40 01 ce       	blcfill %r14d,%edi
+[ 	]*[a-f0-9]+:	8f e9 20 01 c8       	blcfill %eax,%r11d
+[ 	]*[a-f0-9]+:	8f c9 18 01 c9       	blcfill %r9d,%r12d
+[ 	]*[a-f0-9]+:	67 8f c9 60 01 4d 67 	blcfill 0x67\(%r13d\),%ebx
+[ 	]*[a-f0-9]+:	67 8f e9 00 01 0b    	blcfill \(%ebx\),%r15d
+[ 	]*[a-f0-9]+:	67 8f a9 08 01 4c 19 0b 	blcfill 0xb\(%ecx,%r11d,1\),%r14d
+[ 	]*[a-f0-9]+:	8f c9 78 01 8d 4a ff ff ff 	blcfill -0xb6\(%r13\),%eax
+[ 	]*[a-f0-9]+:	8f c9 48 01 09       	blcfill \(%r9\),%esi
+[ 	]*[a-f0-9]+:	8f c9 f8 01 cf       	blcfill %r15,%rax
+[ 	]*[a-f0-9]+:	8f c9 a0 01 cd       	blcfill %r13,%r11
+[ 	]*[a-f0-9]+:	8f c9 e0 01 c8       	blcfill %r8,%rbx
+[ 	]*[a-f0-9]+:	67 8f c9 80 01 0f    	blcfill \(%r15d\),%r15
+[ 	]*[a-f0-9]+:	67 8f c9 88 01 4d 00 	blcfill 0x0\(%r13d\),%r14
+[ 	]*[a-f0-9]+:	8f e9 b0 01 c8       	blcfill %rax,%r9
+[ 	]*[a-f0-9]+:	8f 89 e8 01 4c 24 0a 	blcfill 0xa\(%r12,%r12,1\),%rdx
+[ 	]*[a-f0-9]+:	8f c9 98 01 ce       	blcfill %r14,%r12
+[ 	]*[a-f0-9]+:	8f e9 a8 01 cf       	blcfill %rdi,%r10
+[ 	]*[a-f0-9]+:	67 8f c9 90 01 0b    	blcfill \(%r11d\),%r13
+[ 	]*[a-f0-9]+:	67 8f e9 b8 01 0c 15 25 c6 ff ff 	blcfill -0x39db\(,%edx,1\),%r8
+[ 	]*[a-f0-9]+:	8f c9 d8 01 0c 34    	blcfill \(%r12,%rsi,1\),%rsp
+[ 	]*[a-f0-9]+:	67 8f 89 b8 01 4c 6d 00 	blcfill 0x0\(%r13d,%r13d,2\),%r8
+[ 	]*[a-f0-9]+:	8f e9 d0 01 08       	blcfill \(%rax\),%rbp
+[ 	]*[a-f0-9]+:	8f c9 80 01 09       	blcfill \(%r9\),%r15
+[ 	]*[a-f0-9]+:	8f c9 f0 01 cb       	blcfill %r11,%rcx
+[ 	]*[a-f0-9]+:	8f c9 78 02 f7       	blci   %r15d,%eax
+[ 	]*[a-f0-9]+:	8f e9 00 02 32       	blci   \(%rdx\),%r15d
+[ 	]*[a-f0-9]+:	8f e9 28 02 f0       	blci   %eax,%r10d
+[ 	]*[a-f0-9]+:	67 8f e9 38 02 37    	blci   \(%edi\),%r8d
+[ 	]*[a-f0-9]+:	67 8f c9 68 02 75 00 	blci   0x0\(%r13d\),%edx
+[ 	]*[a-f0-9]+:	67 8f e9 20 02 32    	blci   \(%edx\),%r11d
+[ 	]*[a-f0-9]+:	67 8f e9 18 02 34 05 37 09 00 00 	blci   0x937\(,%eax,1\),%r12d
+[ 	]*[a-f0-9]+:	8f c9 70 02 31       	blci   \(%r9\),%ecx
+[ 	]*[a-f0-9]+:	67 8f c9 58 02 31    	blci   \(%r9d\),%esp
+[ 	]*[a-f0-9]+:	8f e9 48 02 f2       	blci   %edx,%esi
+[ 	]*[a-f0-9]+:	8f e9 08 02 f5       	blci   %ebp,%r14d
+[ 	]*[a-f0-9]+:	8f e9 78 02 f3       	blci   %ebx,%eax
+[ 	]*[a-f0-9]+:	8f e9 38 02 30       	blci   \(%rax\),%r8d
+[ 	]*[a-f0-9]+:	67 8f a9 40 02 34 75 00 00 00 00 	blci   0x0\(,%r14d,2\),%edi
+[ 	]*[a-f0-9]+:	8f e9 78 02 33       	blci   \(%rbx\),%eax
+[ 	]*[a-f0-9]+:	67 8f 89 30 02 b4 31 31 a3 4c 43 	blci   0x434ca331\(%r9d,%r14d,1\),%r9d
+[ 	]*[a-f0-9]+:	67 8f e9 a0 02 33    	blci   \(%ebx\),%r11
+[ 	]*[a-f0-9]+:	8f c9 f8 02 37       	blci   \(%r15\),%rax
+[ 	]*[a-f0-9]+:	67 8f c9 80 02 34 dc 	blci   \(%r12d,%ebx,8\),%r15
+[ 	]*[a-f0-9]+:	8f c9 d0 02 f7       	blci   %r15,%rbp
+[ 	]*[a-f0-9]+:	67 8f e9 d8 02 34 33 	blci   \(%ebx,%esi,1\),%rsp
+[ 	]*[a-f0-9]+:	8f c9 f0 02 f4       	blci   %r12,%rcx
+[ 	]*[a-f0-9]+:	8f c9 c0 02 31       	blci   \(%r9\),%rdi
+[ 	]*[a-f0-9]+:	67 8f c9 e0 02 34 3c 	blci   \(%r12d,%edi,1\),%rbx
+[ 	]*[a-f0-9]+:	8f e9 80 02 34 d5 19 5b 00 00 	blci   0x5b19\(,%rdx,8\),%r15
+[ 	]*[a-f0-9]+:	67 8f e9 a8 02 34 c5 00 00 00 00 	blci   0x0\(,%eax,8\),%r10
+[ 	]*[a-f0-9]+:	8f e9 b8 02 33       	blci   \(%rbx\),%r8
+[ 	]*[a-f0-9]+:	67 8f e9 b0 02 b4 50 0b ff ff ff 	blci   -0xf5\(%eax,%edx,2\),%r9
+[ 	]*[a-f0-9]+:	8f c9 88 02 75 00    	blci   0x0\(%r13\),%r14
+[ 	]*[a-f0-9]+:	8f e9 f8 02 f5       	blci   %rbp,%rax
+[ 	]*[a-f0-9]+:	67 8f e9 90 02 30    	blci   \(%eax\),%r13
+[ 	]*[a-f0-9]+:	8f c9 e8 02 34 24    	blci   \(%r12\),%rdx
+[ 	]*[a-f0-9]+:	67 8f c9 00 01 2c c6 	blcic  \(%r14d,%eax,8\),%r15d
+[ 	]*[a-f0-9]+:	8f c9 78 01 ef       	blcic  %r15d,%eax
+[ 	]*[a-f0-9]+:	8f c9 38 01 29       	blcic  \(%r9\),%r8d
+[ 	]*[a-f0-9]+:	8f c9 30 01 2c 59    	blcic  \(%r9,%rbx,2\),%r9d
+[ 	]*[a-f0-9]+:	67 8f e9 48 01 2b    	blcic  \(%ebx\),%esi
+[ 	]*[a-f0-9]+:	67 8f e9 50 01 2c 05 fe ff ff ff 	blcic  -0x2\(,%eax,1\),%ebp
+[ 	]*[a-f0-9]+:	8f e9 60 01 28       	blcic  \(%rax\),%ebx
+[ 	]*[a-f0-9]+:	8f c9 40 01 2b       	blcic  \(%r11\),%edi
+[ 	]*[a-f0-9]+:	8f e9 20 01 e8       	blcic  %eax,%r11d
+[ 	]*[a-f0-9]+:	8f c9 18 01 2e       	blcic  \(%r14\),%r12d
+[ 	]*[a-f0-9]+:	8f c9 78 01 eb       	blcic  %r11d,%eax
+[ 	]*[a-f0-9]+:	8f a9 00 01 2c 1d a7 d0 1a 14 	blcic  0x141ad0a7\(,%r11,1\),%r15d
+[ 	]*[a-f0-9]+:	8f a9 10 01 2c 88    	blcic  \(%rax,%r9,4\),%r13d
+[ 	]*[a-f0-9]+:	8f e9 00 01 2b       	blcic  \(%rbx\),%r15d
+[ 	]*[a-f0-9]+:	67 8f 89 28 01 2c 3f 	blcic  \(%r15d,%r15d,1\),%r10d
+[ 	]*[a-f0-9]+:	67 8f c9 68 01 29    	blcic  \(%r9d\),%edx
+[ 	]*[a-f0-9]+:	67 8f a9 f0 01 2c 2d b3 cb d3 59 	blcic  0x59d3cbb3\(,%r13d,1\),%rcx
+[ 	]*[a-f0-9]+:	8f c9 f8 01 ee       	blcic  %r14,%rax
+[ 	]*[a-f0-9]+:	67 8f c9 80 01 2c 24 	blcic  \(%r12d\),%r15
+[ 	]*[a-f0-9]+:	8f e9 88 01 e8       	blcic  %rax,%r14
+[ 	]*[a-f0-9]+:	8f c9 d0 01 ef       	blcic  %r15,%rbp
+[ 	]*[a-f0-9]+:	8f e9 d8 01 2b       	blcic  \(%rbx\),%rsp
+[ 	]*[a-f0-9]+:	8f e9 e8 01 eb       	blcic  %rbx,%rdx
+[ 	]*[a-f0-9]+:	8f c9 c0 01 e8       	blcic  %r8,%rdi
+[ 	]*[a-f0-9]+:	8f c9 c8 01 29       	blcic  \(%r9\),%rsi
+[ 	]*[a-f0-9]+:	8f e9 c0 01 2c c5 db db 00 00 	blcic  0xdbdb\(,%rax,8\),%rdi
+[ 	]*[a-f0-9]+:	8f c9 e0 01 ea       	blcic  %r10,%rbx
+[ 	]*[a-f0-9]+:	67 8f e9 a0 01 2b    	blcic  \(%ebx\),%r11
+[ 	]*[a-f0-9]+:	8f c9 b0 01 ed       	blcic  %r13,%r9
+[ 	]*[a-f0-9]+:	8f c9 f8 01 28       	blcic  \(%r8\),%rax
+[ 	]*[a-f0-9]+:	8f 89 98 01 ac 12 ad de 00 00 	blcic  0xdead\(%r10,%r10,1\),%r12
+[ 	]*[a-f0-9]+:	67 8f e9 f0 01 2c 02 	blcic  \(%edx,%eax,1\),%rcx
+[ 	]*[a-f0-9]+:	67 8f e9 00 02 09    	blcmsk \(%ecx\),%r15d
+[ 	]*[a-f0-9]+:	8f e9 78 02 cd       	blcmsk %ebp,%eax
+[ 	]*[a-f0-9]+:	67 8f e9 40 02 0b    	blcmsk \(%ebx\),%edi
+[ 	]*[a-f0-9]+:	8f e9 68 02 c8       	blcmsk %eax,%edx
+[ 	]*[a-f0-9]+:	8f a9 10 02 0c d5 00 00 00 00 	blcmsk 0x0\(,%r10,8\),%r13d
+[ 	]*[a-f0-9]+:	8f c9 30 02 09       	blcmsk \(%r9\),%r9d
+[ 	]*[a-f0-9]+:	8f c9 18 02 0a       	blcmsk \(%r10\),%r12d
+[ 	]*[a-f0-9]+:	8f e9 60 02 c9       	blcmsk %ecx,%ebx
+[ 	]*[a-f0-9]+:	67 8f e9 78 02 0a    	blcmsk \(%edx\),%eax
+[ 	]*[a-f0-9]+:	8f e9 20 02 ce       	blcmsk %esi,%r11d
+[ 	]*[a-f0-9]+:	8f a9 00 02 0c b5 00 00 00 00 	blcmsk 0x0\(,%r14,4\),%r15d
+[ 	]*[a-f0-9]+:	8f c9 78 02 cf       	blcmsk %r15d,%eax
+[ 	]*[a-f0-9]+:	67 8f c9 08 02 8e 5f f3 00 00 	blcmsk 0xf35f\(%r14d\),%r14d
+[ 	]*[a-f0-9]+:	67 8f c9 38 02 0c 30 	blcmsk \(%r8d,%esi,1\),%r8d
+[ 	]*[a-f0-9]+:	8f c9 58 02 0c 14    	blcmsk \(%r12,%rdx,1\),%esp
+[ 	]*[a-f0-9]+:	67 8f c9 28 02 08    	blcmsk \(%r8d\),%r10d
+[ 	]*[a-f0-9]+:	67 8f a9 98 02 0c 2d 00 00 00 00 	blcmsk 0x0\(,%r13d,1\),%r12
+[ 	]*[a-f0-9]+:	8f c9 e0 02 cf       	blcmsk %r15,%rbx
+[ 	]*[a-f0-9]+:	8f e9 80 02 c8       	blcmsk %rax,%r15
+[ 	]*[a-f0-9]+:	67 8f a9 b8 02 0c 0d 03 00 00 00 	blcmsk 0x3\(,%r9d,1\),%r8
+[ 	]*[a-f0-9]+:	8f 89 d0 02 8c 79 02 35 ff ff 	blcmsk -0xcafe\(%r9,%r15,2\),%rbp
+[ 	]*[a-f0-9]+:	8f c9 d8 02 4d 00    	blcmsk 0x0\(%r13\),%rsp
+[ 	]*[a-f0-9]+:	8f e9 f8 02 0a       	blcmsk \(%rdx\),%rax
+[ 	]*[a-f0-9]+:	8f c9 90 02 0c 24    	blcmsk \(%r12\),%r13
+[ 	]*[a-f0-9]+:	8f e9 e8 02 0c d5 f9 ff ff ff 	blcmsk -0x7\(,%rdx,8\),%rdx
+[ 	]*[a-f0-9]+:	8f c9 88 02 0b       	blcmsk \(%r11\),%r14
+[ 	]*[a-f0-9]+:	8f c9 b0 02 ce       	blcmsk %r14,%r9
+[ 	]*[a-f0-9]+:	8f e9 a0 02 09       	blcmsk \(%rcx\),%r11
+[ 	]*[a-f0-9]+:	67 8f c9 f8 02 0e    	blcmsk \(%r14d\),%rax
+[ 	]*[a-f0-9]+:	8f e9 c0 02 0c c5 00 00 00 00 	blcmsk 0x0\(,%rax,8\),%rdi
+[ 	]*[a-f0-9]+:	67 8f c9 90 02 0f    	blcmsk \(%r15d\),%r13
+[ 	]*[a-f0-9]+:	67 8f e9 88 02 0c 33 	blcmsk \(%ebx,%esi,1\),%r14
+[ 	]*[a-f0-9]+:	8f e9 00 01 18       	blcs   \(%rax\),%r15d
+[ 	]*[a-f0-9]+:	67 8f a9 38 01 1c 05 01 00 00 00 	blcs   0x1\(,%r8d,1\),%r8d
+[ 	]*[a-f0-9]+:	8f c9 70 01 da       	blcs   %r10d,%ecx
+[ 	]*[a-f0-9]+:	8f c9 28 01 df       	blcs   %r15d,%r10d
+[ 	]*[a-f0-9]+:	8f c9 78 01 db       	blcs   %r11d,%eax
+[ 	]*[a-f0-9]+:	67 8f e9 40 01 99 9b dc 68 81 	blcs   -0x7e972365\(%ecx\),%edi
+[ 	]*[a-f0-9]+:	67 8f e9 08 01 1e    	blcs   \(%esi\),%r14d
+[ 	]*[a-f0-9]+:	8f c9 20 01 5a fd    	blcs   -0x3\(%r10\),%r11d
+[ 	]*[a-f0-9]+:	8f e9 58 01 1f       	blcs   \(%rdi\),%esp
+[ 	]*[a-f0-9]+:	67 8f c9 60 01 1f    	blcs   \(%r15d\),%ebx
+[ 	]*[a-f0-9]+:	8f c9 10 01 1c b1    	blcs   \(%r9,%rsi,4\),%r13d
+[ 	]*[a-f0-9]+:	8f c9 30 01 1c 19    	blcs   \(%r9,%rbx,1\),%r9d
+[ 	]*[a-f0-9]+:	67 8f e9 00 01 1c 08 	blcs   \(%eax,%ecx,1\),%r15d
+[ 	]*[a-f0-9]+:	8f e9 48 01 db       	blcs   %ebx,%esi
+[ 	]*[a-f0-9]+:	8f e9 78 01 de       	blcs   %esi,%eax
+[ 	]*[a-f0-9]+:	8f e9 18 01 df       	blcs   %edi,%r12d
+[ 	]*[a-f0-9]+:	8f e9 f8 01 df       	blcs   %rdi,%rax
+[ 	]*[a-f0-9]+:	8f e9 98 01 18       	blcs   \(%rax\),%r12
+[ 	]*[a-f0-9]+:	8f c9 80 01 df       	blcs   %r15,%r15
+[ 	]*[a-f0-9]+:	8f c9 f0 01 da       	blcs   %r10,%rcx
+[ 	]*[a-f0-9]+:	67 8f e9 90 01 18    	blcs   \(%eax\),%r13
+[ 	]*[a-f0-9]+:	8f e9 b8 01 d8       	blcs   %rax,%r8
+[ 	]*[a-f0-9]+:	67 8f e9 c0 01 5a ff 	blcs   -0x1\(%edx\),%rdi
+[ 	]*[a-f0-9]+:	8f e9 a0 01 db       	blcs   %rbx,%r11
+[ 	]*[a-f0-9]+:	67 8f e9 d8 01 1c 45 00 00 00 00 	blcs   0x0\(,%eax,2\),%rsp
+[ 	]*[a-f0-9]+:	8f 89 a8 01 1c 29    	blcs   \(%r9,%r13,1\),%r10
+[ 	]*[a-f0-9]+:	67 8f a9 88 01 1c 05 cf 1d 00 00 	blcs   0x1dcf\(,%r8d,1\),%r14
+[ 	]*[a-f0-9]+:	67 8f a9 80 01 1c bd 00 00 00 00 	blcs   0x0\(,%r15d,4\),%r15
+[ 	]*[a-f0-9]+:	8f c9 d0 01 19       	blcs   \(%r9\),%rbp
+[ 	]*[a-f0-9]+:	67 8f c9 e8 01 5c 05 00 	blcs   0x0\(%r13d,%eax,1\),%rdx
+[ 	]*[a-f0-9]+:	8f c9 d8 01 dc       	blcs   %r12,%rsp
+[ 	]*[a-f0-9]+:	8f e9 e0 01 1f       	blcs   \(%rdi\),%rbx
+[ 	]*[a-f0-9]+:	67 8f e9 68 01 16    	blsfill \(%esi\),%edx
+[ 	]*[a-f0-9]+:	8f c9 78 01 11       	blsfill \(%r9\),%eax
+[ 	]*[a-f0-9]+:	67 8f e9 00 01 13    	blsfill \(%ebx\),%r15d
+[ 	]*[a-f0-9]+:	8f e9 20 01 d0       	blsfill %eax,%r11d
+[ 	]*[a-f0-9]+:	8f c9 38 01 14 24    	blsfill \(%r12\),%r8d
+[ 	]*[a-f0-9]+:	67 8f a9 00 01 14 0d 7e aa ff ff 	blsfill -0x5582\(,%r9d,1\),%r15d
+[ 	]*[a-f0-9]+:	8f e9 78 01 d4       	blsfill %esp,%eax
+[ 	]*[a-f0-9]+:	67 8f a9 50 01 14 65 00 00 00 00 	blsfill 0x0\(,%r12d,2\),%ebp
+[ 	]*[a-f0-9]+:	67 8f c9 60 01 10    	blsfill \(%r8d\),%ebx
+[ 	]*[a-f0-9]+:	67 8f e9 58 01 10    	blsfill \(%eax\),%esp
+[ 	]*[a-f0-9]+:	8f a9 18 01 14 1d 03 4f 00 00 	blsfill 0x4f03\(,%r11,1\),%r12d
+[ 	]*[a-f0-9]+:	67 8f a9 78 01 14 15 0f 00 00 00 	blsfill 0xf\(,%r10d,1\),%eax
+[ 	]*[a-f0-9]+:	67 8f c9 40 01 17    	blsfill \(%r15d\),%edi
+[ 	]*[a-f0-9]+:	8f e9 70 01 14 35 8f 22 00 00 	blsfill 0x228f\(,%rsi,1\),%ecx
+[ 	]*[a-f0-9]+:	67 8f e9 48 01 11    	blsfill \(%ecx\),%esi
+[ 	]*[a-f0-9]+:	8f c9 10 01 d0       	blsfill %r8d,%r13d
+[ 	]*[a-f0-9]+:	67 8f e9 80 01 14 85 f4 ff ff ff 	blsfill -0xc\(,%eax,4\),%r15
+[ 	]*[a-f0-9]+:	8f e9 98 01 d0       	blsfill %rax,%r12
+[ 	]*[a-f0-9]+:	8f e9 f8 01 d2       	blsfill %rdx,%rax
+[ 	]*[a-f0-9]+:	8f c9 d0 01 11       	blsfill \(%r9\),%rbp
+[ 	]*[a-f0-9]+:	67 8f e9 e0 01 17    	blsfill \(%edi\),%rbx
+[ 	]*[a-f0-9]+:	8f c9 b0 01 d7       	blsfill %r15,%r9
+[ 	]*[a-f0-9]+:	8f e9 d8 01 d3       	blsfill %rbx,%rsp
+[ 	]*[a-f0-9]+:	8f c9 f8 01 17       	blsfill \(%r15\),%rax
+[ 	]*[a-f0-9]+:	67 8f e9 a8 01 94 3f b9 56 00 00 	blsfill 0x56b9\(%edi,%edi,1\),%r10
+[ 	]*[a-f0-9]+:	67 8f c9 f0 01 94 b4 2f d4 ff ff 	blsfill -0x2bd1\(%r12d,%esi,4\),%rcx
+[ 	]*[a-f0-9]+:	8f c9 d8 01 13       	blsfill \(%r11\),%rsp
+[ 	]*[a-f0-9]+:	8f c9 b8 01 d5       	blsfill %r13,%r8
+[ 	]*[a-f0-9]+:	67 8f e9 f8 01 14 43 	blsfill \(%ebx,%eax,2\),%rax
+[ 	]*[a-f0-9]+:	67 8f e9 f8 01 13    	blsfill \(%ebx\),%rax
+[ 	]*[a-f0-9]+:	8f e9 a0 01 14 13    	blsfill \(%rbx,%rdx,1\),%r11
+[ 	]*[a-f0-9]+:	8f c9 c8 01 95 dc 2f 00 00 	blsfill 0x2fdc\(%r13\),%rsi
+[ 	]*[a-f0-9]+:	8f c9 00 01 f3       	blsic  %r11d,%r15d
+[ 	]*[a-f0-9]+:	8f e9 50 01 34 35 61 86 ff ff 	blsic  -0x799f\(,%rsi,1\),%ebp
+[ 	]*[a-f0-9]+:	8f c9 78 01 f7       	blsic  %r15d,%eax
+[ 	]*[a-f0-9]+:	8f a9 70 01 34 10    	blsic  \(%rax,%r10,1\),%ecx
+[ 	]*[a-f0-9]+:	8f e9 28 01 f0       	blsic  %eax,%r10d
+[ 	]*[a-f0-9]+:	67 8f c9 30 01 75 00 	blsic  0x0\(%r13d\),%r9d
+[ 	]*[a-f0-9]+:	8f c9 60 01 31       	blsic  \(%r9\),%ebx
+[ 	]*[a-f0-9]+:	67 8f e9 58 01 33    	blsic  \(%ebx\),%esp
+[ 	]*[a-f0-9]+:	67 8f c9 20 01 34 24 	blsic  \(%r12d\),%r11d
+[ 	]*[a-f0-9]+:	8f e9 68 01 34 3d fe bc 00 00 	blsic  0xbcfe\(,%rdi,1\),%edx
+[ 	]*[a-f0-9]+:	67 8f c9 40 01 36    	blsic  \(%r14d\),%edi
+[ 	]*[a-f0-9]+:	67 8f a9 00 01 34 2d ec 78 00 00 	blsic  0x78ec\(,%r13d,1\),%r15d
+[ 	]*[a-f0-9]+:	67 8f c9 48 01 33    	blsic  \(%r11d\),%esi
+[ 	]*[a-f0-9]+:	8f c9 08 01 32       	blsic  \(%r10\),%r14d
+[ 	]*[a-f0-9]+:	67 8f c9 00 01 31    	blsic  \(%r9d\),%r15d
+[ 	]*[a-f0-9]+:	8f c9 00 01 f2       	blsic  %r10d,%r15d
+[ 	]*[a-f0-9]+:	8f c9 f8 01 f7       	blsic  %r15,%rax
+[ 	]*[a-f0-9]+:	8f e9 b0 01 34 05 67 00 00 00 	blsic  0x67\(,%rax,1\),%r9
+[ 	]*[a-f0-9]+:	67 8f 89 e8 01 34 20 	blsic  \(%r8d,%r12d,1\),%rdx
+[ 	]*[a-f0-9]+:	67 8f c9 80 01 37    	blsic  \(%r15d\),%r15
+[ 	]*[a-f0-9]+:	8f c9 f0 01 f1       	blsic  %r9,%rcx
+[ 	]*[a-f0-9]+:	8f c9 c0 01 f2       	blsic  %r10,%rdi
+[ 	]*[a-f0-9]+:	8f a9 e0 01 34 05 ff ff ff 3f 	blsic  0x3fffffff\(,%r8,1\),%rbx
+[ 	]*[a-f0-9]+:	8f e9 80 01 f2       	blsic  %rdx,%r15
+[ 	]*[a-f0-9]+:	8f e9 c8 01 30       	blsic  \(%rax\),%rsi
+[ 	]*[a-f0-9]+:	67 8f c9 f8 01 37    	blsic  \(%r15d\),%rax
+[ 	]*[a-f0-9]+:	8f e9 80 01 33       	blsic  \(%rbx\),%r15
+[ 	]*[a-f0-9]+:	8f e9 b8 01 f0       	blsic  %rax,%r8
+[ 	]*[a-f0-9]+:	67 8f e9 f8 01 33    	blsic  \(%ebx\),%rax
+[ 	]*[a-f0-9]+:	8f e9 88 01 f1       	blsic  %rcx,%r14
+[ 	]*[a-f0-9]+:	67 8f c9 c8 01 34 07 	blsic  \(%r15d,%eax,1\),%rsi
+[ 	]*[a-f0-9]+:	8f c9 98 01 f5       	blsic  %r13,%r12
+[ 	]*[a-f0-9]+:	8f e9 00 01 7e fd    	t1mskc -0x3\(%rsi\),%r15d
+[ 	]*[a-f0-9]+:	8f c9 18 01 ff       	t1mskc %r15d,%r12d
+[ 	]*[a-f0-9]+:	8f c9 30 01 3c 24    	t1mskc \(%r12\),%r9d
+[ 	]*[a-f0-9]+:	8f e9 78 01 fe       	t1mskc %esi,%eax
+[ 	]*[a-f0-9]+:	67 8f c9 58 01 7a fe 	t1mskc -0x2\(%r10d\),%esp
+[ 	]*[a-f0-9]+:	67 8f e9 10 01 3c 45 00 00 00 00 	t1mskc 0x0\(,%eax,2\),%r13d
+[ 	]*[a-f0-9]+:	8f e9 48 01 f8       	t1mskc %eax,%esi
+[ 	]*[a-f0-9]+:	67 8f c9 78 01 3c 24 	t1mskc \(%r12d\),%eax
+[ 	]*[a-f0-9]+:	8f e9 28 01 3c 1d 9c f5 00 00 	t1mskc 0xf59c\(,%rbx,1\),%r10d
+[ 	]*[a-f0-9]+:	67 8f e9 20 01 3c 85 00 00 00 00 	t1mskc 0x0\(,%eax,4\),%r11d
+[ 	]*[a-f0-9]+:	67 8f e9 38 01 3b    	t1mskc \(%ebx\),%r8d
+[ 	]*[a-f0-9]+:	8f e9 60 01 ff       	t1mskc %edi,%ebx
+[ 	]*[a-f0-9]+:	67 8f e9 08 01 3a    	t1mskc \(%edx\),%r14d
+[ 	]*[a-f0-9]+:	67 8f c9 00 01 3b    	t1mskc \(%r11d\),%r15d
+[ 	]*[a-f0-9]+:	67 8f e9 70 01 3e    	t1mskc \(%esi\),%ecx
+[ 	]*[a-f0-9]+:	8f 89 40 01 3c 29    	t1mskc \(%r9,%r13,1\),%edi
+[ 	]*[a-f0-9]+:	8f c9 d8 01 be ff ff ff 3f 	t1mskc 0x3fffffff\(%r14\),%rsp
+[ 	]*[a-f0-9]+:	8f e9 f8 01 f8       	t1mskc %rax,%rax
+[ 	]*[a-f0-9]+:	8f c9 e0 01 38       	t1mskc \(%r8\),%rbx
+[ 	]*[a-f0-9]+:	67 8f c9 c0 01 3c 3c 	t1mskc \(%r12d,%edi,1\),%rdi
+[ 	]*[a-f0-9]+:	8f c9 f0 01 fb       	t1mskc %r11,%rcx
+[ 	]*[a-f0-9]+:	8f c9 88 01 7d 00    	t1mskc 0x0\(%r13\),%r14
+[ 	]*[a-f0-9]+:	67 8f e9 e8 01 3c c5 ad de 00 00 	t1mskc 0xdead\(,%eax,8\),%rdx
+[ 	]*[a-f0-9]+:	8f c9 80 01 ff       	t1mskc %r15,%r15
+[ 	]*[a-f0-9]+:	8f c9 d0 01 3f       	t1mskc \(%r15\),%rbp
+[ 	]*[a-f0-9]+:	8f e9 b0 01 fc       	t1mskc %rsp,%r9
+[ 	]*[a-f0-9]+:	8f e9 c8 01 3a       	t1mskc \(%rdx\),%rsi
+[ 	]*[a-f0-9]+:	8f c9 a8 01 fa       	t1mskc %r10,%r10
+[ 	]*[a-f0-9]+:	67 8f c9 90 01 39    	t1mskc \(%r9d\),%r13
+[ 	]*[a-f0-9]+:	8f e9 f8 01 fb       	t1mskc %rbx,%rax
+[ 	]*[a-f0-9]+:	8f c9 f8 01 39       	t1mskc \(%r9\),%rax
+[ 	]*[a-f0-9]+:	67 8f c9 a8 01 38    	t1mskc \(%r8d\),%r10
+[ 	]*[a-f0-9]+:	8f e9 28 01 e3       	tzmsk  %ebx,%r10d
+[ 	]*[a-f0-9]+:	8f c9 78 01 21       	tzmsk  \(%r9\),%eax
+[ 	]*[a-f0-9]+:	8f e9 00 01 22       	tzmsk  \(%rdx\),%r15d
+[ 	]*[a-f0-9]+:	8f e9 18 01 e5       	tzmsk  %ebp,%r12d
+[ 	]*[a-f0-9]+:	8f c9 10 01 e2       	tzmsk  %r10d,%r13d
+[ 	]*[a-f0-9]+:	8f c9 00 01 e7       	tzmsk  %r15d,%r15d
+[ 	]*[a-f0-9]+:	8f 89 60 01 a4 0b 02 35 ff ff 	tzmsk  -0xcafe\(%r11,%r9,1\),%ebx
+[ 	]*[a-f0-9]+:	67 8f a9 68 01 64 2e 01 	tzmsk  0x1\(%esi,%r13d,1\),%edx
+[ 	]*[a-f0-9]+:	67 8f c9 08 01 23    	tzmsk  \(%r11d\),%r14d
+[ 	]*[a-f0-9]+:	67 8f a9 70 01 24 a1 	tzmsk  \(%ecx,%r12d,4\),%ecx
+[ 	]*[a-f0-9]+:	67 8f e9 30 01 20    	tzmsk  \(%eax\),%r9d
+[ 	]*[a-f0-9]+:	8f e9 38 01 60 fa    	tzmsk  -0x6\(%rax\),%r8d
+[ 	]*[a-f0-9]+:	8f e9 48 01 e7       	tzmsk  %edi,%esi
+[ 	]*[a-f0-9]+:	8f e9 00 01 e0       	tzmsk  %eax,%r15d
+[ 	]*[a-f0-9]+:	8f e9 50 01 64 01 f1 	tzmsk  -0xf\(%rcx,%rax,1\),%ebp
+[ 	]*[a-f0-9]+:	67 8f c9 20 01 27    	tzmsk  \(%r15d\),%r11d
+[ 	]*[a-f0-9]+:	67 8f e9 e8 01 24 dd ad de 00 00 	tzmsk  0xdead\(,%ebx,8\),%rdx
+[ 	]*[a-f0-9]+:	67 8f e9 80 01 24 15 f8 ff ff ff 	tzmsk  -0x8\(,%edx,1\),%r15
+[ 	]*[a-f0-9]+:	8f e9 f8 01 e4       	tzmsk  %rsp,%rax
+[ 	]*[a-f0-9]+:	67 8f c9 b8 01 21    	tzmsk  \(%r9d\),%r8
+[ 	]*[a-f0-9]+:	8f e9 98 01 e0       	tzmsk  %rax,%r12
+[ 	]*[a-f0-9]+:	8f c9 d0 01 e7       	tzmsk  %r15,%rbp
+[ 	]*[a-f0-9]+:	8f 89 98 01 24 c9    	tzmsk  \(%r9,%r9,8\),%r12
+[ 	]*[a-f0-9]+:	67 8f e9 90 01 24 9f 	tzmsk  \(%edi,%ebx,4\),%r13
+[ 	]*[a-f0-9]+:	8f e9 c0 01 e7       	tzmsk  %rdi,%rdi
+[ 	]*[a-f0-9]+:	67 8f e9 f8 01 23    	tzmsk  \(%ebx\),%rax
+[ 	]*[a-f0-9]+:	8f e9 d8 01 26       	tzmsk  \(%rsi\),%rsp
+[ 	]*[a-f0-9]+:	8f c9 f0 01 a0 02 35 ff ff 	tzmsk  -0xcafe\(%r8\),%rcx
+[ 	]*[a-f0-9]+:	67 8f c9 88 01 a4 02 98 3c 00 00 	tzmsk  0x3c98\(%r10d,%eax,1\),%r14
+[ 	]*[a-f0-9]+:	67 8f c9 80 01 23    	tzmsk  \(%r11d\),%r15
+[ 	]*[a-f0-9]+:	8f e9 c8 01 e6       	tzmsk  %rsi,%rsi
+[ 	]*[a-f0-9]+:	8f a9 b0 01 24 05 53 21 ff ff 	tzmsk  -0xdead\(,%r8,1\),%r9
diff --git a/gas/testsuite/gas/i386/x86-64-tbm.s b/gas/testsuite/gas/i386/x86-64-tbm.s
new file mode 100644
index 0000000..e1bbb9d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-tbm.s
@@ -0,0 +1,327 @@
+
+	.allow_index_reg
+	.text
+	
+_start:
+
+    BEXTR    $0x0,%eax,%r15d
+    BEXTR    $0x4DF1,%r15d,%r10d
+    BEXTR    $0x2DA55E92,%r13d,%r14d
+    BEXTR    $0x7FFFFFFF,0x6(%r13d,%r15d,2),%eax
+    BEXTR    $0x251EF761,%r11d,%ebp
+    BEXTR    $0x2B39,(%rdi,%rdx,8),%r15d
+    BEXTR    $0x92,0xDEAD(,%r14),%r9d
+    BEXTR    $0x6887,(%r13),%esi
+    BEXTR    $0xD,(%r9d),%ecx
+    BEXTR    $0x2B,0x40D8(,%rax),%ebx
+    BEXTR    $0xEA2D,(%r8),%r8d
+    BEXTR    $0x6C,(%r13d),%r12d
+    BEXTR    $0x9E3B,0x8C8F(,%rcx),%r11d
+    BEXTR    $0xF,(%r10d,%eax),%esp
+    BEXTR    $0xDEAD,-0x0(,%r9d,8),%edi
+    BEXTR    $0xCAFE,%r8d,%eax
+    BEXTR    $0x7D263BB9,0x10BC(%r9),%r8
+    BEXTR    $0x67,(,%r12d,2),%r15
+    BEXTR    $0x0,%rax,%rax
+    BEXTR    $0x539B,(%esi),%rsp
+    BEXTR    $0x7FFFFFFF,(%r8),%rcx
+    BEXTR    $0x1,0x3FFFFFFF(,%edi),%rax
+    BEXTR    $0x9E,-0x227C(%r8d,%r14d),%rsi
+    BEXTR    $0x2A6C464,%r15,%rax
+    BEXTR    $0x4,0x2(%edi,%r11d,1),%r9
+    BEXTR    $0x2,%rdi,%rbp
+    BEXTR    $0x781E7EFB,(%r14d,%edx,1),%rdx
+    BEXTR    $0x70CB4039,0xDB68(%r11,%r13),%r13
+    BEXTR    $0x1373,(%r14),%r10
+    BEXTR    $0x556D,(%edi,%r13d,4),%r15
+    BEXTR    $0x0,(%r9),%r10
+    BEXTR    $0x7BEEEEEF,(%rdi),%r11
+    BLCFILL  %esp,%r15d
+    BLCFILL  (%rsi,%r12,4),%edx
+    BLCFILL  (%eax),%r14d
+    BLCFILL  (,%r13,4),%ebp
+    BLCFILL  (%r14d),%eax
+    BLCFILL  (%r11),%r9d
+    BLCFILL  0xDEAD(,%r8,2),%r13d
+    BLCFILL  %r15d,%r15d
+    BLCFILL  %r14d,%edi
+    BLCFILL  %eax,%r11d
+    BLCFILL  %r9d,%r12d
+    BLCFILL  0x67(%r13d),%ebx
+    BLCFILL  (%ebx),%r15d
+    BLCFILL  0xB(%ecx,%r11d),%r14d
+    BLCFILL  -0xB6(%r13),%eax
+    BLCFILL  (%r9),%esi
+    BLCFILL  %r15,%rax
+    BLCFILL  %r13,%r11
+    BLCFILL  %r8,%rbx
+    BLCFILL  (%r15d),%r15
+    BLCFILL  (%r13d),%r14
+    BLCFILL  %rax,%r9
+    BLCFILL  0xA(%r12,%r12,1),%rdx
+    BLCFILL  %r14,%r12
+    BLCFILL  %rdi,%r10
+    BLCFILL  (%r11d),%r13
+    BLCFILL  -0x39DB(,%edx),%r8
+    BLCFILL  (%r12,%rsi),%rsp
+    BLCFILL  (%r13d,%r13d,2),%r8
+    BLCFILL  (%rax),%rbp
+    BLCFILL  (%r9),%r15
+    BLCFILL  %r11,%rcx
+    BLCI     %r15d,%eax
+    BLCI     (%rdx),%r15d
+    BLCI     %eax,%r10d
+    BLCI     (%edi),%r8d
+    BLCI     (%r13d),%edx
+    BLCI     (%edx),%r11d
+    BLCI     0x937(,%eax),%r12d
+    BLCI     (%r9),%ecx
+    BLCI     (%r9d),%esp
+    BLCI     %edx,%esi
+    BLCI     %ebp,%r14d
+    BLCI     %ebx,%eax
+    BLCI     (%rax),%r8d
+    BLCI     (,%r14d,2),%edi
+    BLCI     (%rbx),%eax
+    BLCI     0x434CA331(%r9d,%r14d),%r9d
+    BLCI     (%ebx),%r11
+    BLCI     (%r15),%rax
+    BLCI     (%r12d,%ebx,8),%r15
+    BLCI     %r15,%rbp
+    BLCI     -0x0(%ebx,%esi),%rsp
+    BLCI     %r12,%rcx
+    BLCI     (%r9),%rdi
+    BLCI     (%r12d,%edi,1),%rbx
+    BLCI     0x5B19(,%rdx,8),%r15
+    BLCI     (,%eax,8),%r10
+    BLCI     (%rbx),%r8
+    BLCI     -0xF5(%eax,%edx,2),%r9
+    BLCI     (%r13),%r14
+    BLCI     %rbp,%rax
+    BLCI     (%eax),%r13
+    BLCI     (%r12),%rdx
+    BLCIC    (%r14d,%eax,8),%r15d
+    BLCIC    %r15d,%eax
+    BLCIC    (%r9),%r8d
+    BLCIC    (%r9,%rbx,2),%r9d
+    BLCIC    (%ebx),%esi
+    BLCIC    -0x2(,%eax),%ebp
+    BLCIC    (%rax),%ebx
+    BLCIC    (%r11),%edi
+    BLCIC    %eax,%r11d
+    BLCIC    (%r14),%r12d
+    BLCIC    %r11d,%eax
+    BLCIC    0x141AD0A7(,%r11),%r15d
+    BLCIC    (%rax,%r9,4),%r13d
+    BLCIC    (%rbx),%r15d
+    BLCIC    (%r15d,%r15d),%r10d
+    BLCIC    (%r9d),%edx
+    BLCIC    0x59D3CBB3(,%r13d,1),%rcx
+    BLCIC    %r14,%rax
+    BLCIC    (%r12d),%r15
+    BLCIC    %rax,%r14
+    BLCIC    %r15,%rbp
+    BLCIC    (%rbx),%rsp
+    BLCIC    %rbx,%rdx
+    BLCIC    %r8,%rdi
+    BLCIC    (%r9),%rsi
+    BLCIC    0xDBDB(,%rax,8),%rdi
+    BLCIC    %r10,%rbx
+    BLCIC    (%ebx),%r11
+    BLCIC    %r13,%r9
+    BLCIC    (%r8),%rax
+    BLCIC    0xDEAD(%r10,%r10,1),%r12
+    BLCIC    (%edx,%eax),%rcx
+    BLCMSK   (%ecx),%r15d
+    BLCMSK   %ebp,%eax
+    BLCMSK   (%ebx),%edi
+    BLCMSK   %eax,%edx
+    BLCMSK   (,%r10,8),%r13d
+    BLCMSK   (%r9),%r9d
+    BLCMSK   (%r10),%r12d
+    BLCMSK   %ecx,%ebx
+    BLCMSK   (%edx),%eax
+    BLCMSK   %esi,%r11d
+    BLCMSK   (,%r14,4),%r15d
+    BLCMSK   %r15d,%eax
+    BLCMSK   0xF35F(%r14d),%r14d
+    BLCMSK   (%r8d,%esi,1),%r8d
+    BLCMSK   (%r12,%rdx),%esp
+    BLCMSK   (%r8d),%r10d
+    BLCMSK   0x0(,%r13d),%r12
+    BLCMSK   %r15,%rbx
+    BLCMSK   %rax,%r15
+    BLCMSK   0x3(,%r9d,1),%r8
+    BLCMSK   -0xCAFE(%r9,%r15,2),%rbp
+    BLCMSK   (%r13),%rsp
+    BLCMSK   (%rdx),%rax
+    BLCMSK   (%r12),%r13
+    BLCMSK   -0x7(,%rdx,8),%rdx
+    BLCMSK   (%r11),%r14
+    BLCMSK   %r14,%r9
+    BLCMSK   (%rcx),%r11
+    BLCMSK   (%r14d),%rax
+    BLCMSK   (,%rax,8),%rdi
+    BLCMSK   (%r15d),%r13
+    BLCMSK   (%ebx,%esi),%r14
+    BLCS     (%rax),%r15d
+    BLCS     0x1(,%r8d,1),%r8d
+    BLCS     %r10d,%ecx
+    BLCS     %r15d,%r10d
+    BLCS     %r11d,%eax
+    BLCS     -0x7E972365(%ecx),%edi
+    BLCS     (%esi),%r14d
+    BLCS     -0x3(%r10),%r11d
+    BLCS     (%rdi),%esp
+    BLCS     (%r15d),%ebx
+    BLCS     (%r9,%rsi,4),%r13d
+    BLCS     0x0(%r9,%rbx,1),%r9d
+    BLCS     (%eax,%ecx),%r15d
+    BLCS     %ebx,%esi
+    BLCS     %esi,%eax
+    BLCS     %edi,%r12d
+    BLCS     %rdi,%rax
+    BLCS     (%rax),%r12
+    BLCS     %r15,%r15
+    BLCS     %r10,%rcx
+    BLCS     (%eax),%r13
+    BLCS     %rax,%r8
+    BLCS     -0x1(%edx),%rdi
+    BLCS     %rbx,%r11
+    BLCS     (,%eax,2),%rsp
+    BLCS     (%r9,%r13),%r10
+    BLCS     0x1DCF(,%r8d,1),%r14
+    BLCS     (,%r15d,4),%r15
+    BLCS     (%r9),%rbp
+    BLCS     (%r13d,%eax),%rdx
+    BLCS     %r12,%rsp
+    BLCS     (%rdi),%rbx
+    BLSFILL  (%esi),%edx
+    BLSFILL  (%r9),%eax
+    BLSFILL  (%ebx),%r15d
+    BLSFILL  %eax,%r11d
+    BLSFILL  (%r12),%r8d
+    BLSFILL  -0x5582(,%r9d),%r15d
+    BLSFILL  %esp,%eax
+    BLSFILL  (,%r12d,2),%ebp
+    BLSFILL  (%r8d),%ebx
+    BLSFILL  (%eax),%esp
+    BLSFILL  0x4F03(,%r11),%r12d
+    BLSFILL  0xF(,%r10d),%eax
+    BLSFILL  (%r15d),%edi
+    BLSFILL  0x228F(,%rsi,1),%ecx
+    BLSFILL  (%ecx),%esi
+    BLSFILL  %r8d,%r13d
+    BLSFILL  -0xC(,%eax,4),%r15
+    BLSFILL  %rax,%r12
+    BLSFILL  %rdx,%rax
+    BLSFILL  (%r9),%rbp
+    BLSFILL  (%edi),%rbx
+    BLSFILL  %r15,%r9
+    BLSFILL  %rbx,%rsp
+    BLSFILL  (%r15),%rax
+    BLSFILL  0x56B9(%edi,%edi),%r10
+    BLSFILL  -0x2BD1(%r12d,%esi,4),%rcx
+    BLSFILL  (%r11),%rsp
+    BLSFILL  %r13,%r8
+    BLSFILL  (%ebx,%eax,2),%rax
+    BLSFILL  (%ebx),%rax
+    BLSFILL  (%rbx,%rdx),%r11
+    BLSFILL  0x2FDC(%r13),%rsi
+    BLSIC    %r11d,%r15d
+    BLSIC    -0x799F(,%rsi),%ebp
+    BLSIC    %r15d,%eax
+    BLSIC    -0x0(%rax,%r10,1),%ecx
+    BLSIC    %eax,%r10d
+    BLSIC    (%r13d),%r9d
+    BLSIC    (%r9),%ebx
+    BLSIC    (%ebx),%esp
+    BLSIC    (%r12d),%r11d
+    BLSIC    0xBCFE(,%rdi,1),%edx
+    BLSIC    (%r14d),%edi
+    BLSIC    0x78EC(,%r13d),%r15d
+    BLSIC    (%r11d),%esi
+    BLSIC    (%r10),%r14d
+    BLSIC    (%r9d),%r15d
+    BLSIC    %r10d,%r15d
+    BLSIC    %r15,%rax
+    BLSIC    0x67(,%rax),%r9
+    BLSIC    (%r8d,%r12d),%rdx
+    BLSIC    (%r15d),%r15
+    BLSIC    %r9,%rcx
+    BLSIC    %r10,%rdi
+    BLSIC    0x3FFFFFFF(,%r8),%rbx
+    BLSIC    %rdx,%r15
+    BLSIC    (%rax),%rsi
+    BLSIC    0x0(%r15d),%rax
+    BLSIC    (%rbx),%r15
+    BLSIC    %rax,%r8
+    BLSIC    (%ebx),%rax
+    BLSIC    %rcx,%r14
+    BLSIC    (%r15d,%eax,1),%rsi
+    BLSIC    %r13,%r12
+    T1MSKC   -0x3(%rsi),%r15d
+    T1MSKC   %r15d,%r12d
+    T1MSKC   (%r12),%r9d
+    T1MSKC   %esi,%eax
+    T1MSKC   -0x2(%r10d),%esp
+    T1MSKC   (,%eax,2),%r13d
+    T1MSKC   %eax,%esi
+    T1MSKC   (%r12d),%eax
+    T1MSKC   0xF59C(,%rbx),%r10d
+    T1MSKC   (,%eax,4),%r11d
+    T1MSKC   (%ebx),%r8d
+    T1MSKC   %edi,%ebx
+    T1MSKC   (%edx),%r14d
+    T1MSKC   (%r11d),%r15d
+    T1MSKC   (%esi),%ecx
+    T1MSKC   (%r9,%r13),%edi
+    T1MSKC   0x3FFFFFFF(%r14),%rsp
+    T1MSKC   %rax,%rax
+    T1MSKC   (%r8),%rbx
+    T1MSKC   (%r12d,%edi),%rdi
+    T1MSKC   %r11,%rcx
+    T1MSKC   (%r13),%r14
+    T1MSKC   0xDEAD(,%eax,8),%rdx
+    T1MSKC   %r15,%r15
+    T1MSKC   (%r15),%rbp
+    T1MSKC   %rsp,%r9
+    T1MSKC   (%rdx),%rsi
+    T1MSKC   %r10,%r10
+    T1MSKC   (%r9d),%r13
+    T1MSKC   %rbx,%rax
+    T1MSKC   (%r9),%rax
+    T1MSKC   (%r8d),%r10
+    TZMSK    %ebx,%r10d
+    TZMSK    (%r9),%eax
+    TZMSK    (%rdx),%r15d
+    TZMSK    %ebp,%r12d
+    TZMSK    %r10d,%r13d
+    TZMSK    %r15d,%r15d
+    TZMSK    -0xCAFE(%r11,%r9,1),%ebx
+    TZMSK    0x1(%esi,%r13d),%edx
+    TZMSK    (%r11d),%r14d
+    TZMSK    (%ecx,%r12d,4),%ecx
+    TZMSK    (%eax),%r9d
+    TZMSK    -0x6(%rax),%r8d
+    TZMSK    %edi,%esi
+    TZMSK    %eax,%r15d
+    TZMSK    -0xF(%rcx,%rax,1),%ebp
+    TZMSK    (%r15d),%r11d
+    TZMSK    0xDEAD(,%ebx,8),%rdx
+    TZMSK    -0x8(,%edx),%r15
+    TZMSK    %rsp,%rax
+    TZMSK    (%r9d),%r8
+    TZMSK    %rax,%r12
+    TZMSK    %r15,%rbp
+    TZMSK    (%r9,%r9,8),%r12
+    TZMSK    (%edi,%ebx,4),%r13
+    TZMSK    %rdi,%rdi
+    TZMSK    (%ebx),%rax
+    TZMSK    (%rsi),%rsp
+    TZMSK    -0xCAFE(%r8),%rcx
+    TZMSK    0x3C98(%r10d,%eax),%r14
+    TZMSK    (%r11d),%r15
+    TZMSK    %rsi,%rsi
+    TZMSK    -0xDEAD(,%r8),%r9
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bd88388..02c92c8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,65 @@
+2011-01-04  Quentin Neill  <quentin.neill@amd.com>
+
+	* i386-dis.c (REG_XOP_TBM_01): New.
+	(REG_XOP_TBM_02): New.
+	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
+	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
+	entries, and add bextr instruction.
+	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
+	(cpu_flags): Add CpuTBM.
+	* i386-opc.h (CpuTBM) New.
+	(i386_cpu_flags): Add bit cputbm.
+
+	* i386-opc.tbl (bextr): Added.
+	(bextr): Added.
+	(blcfill): Added.
+	(blci): Added.
+	(blcic): Added.
+	(blcmsk): Added.
+	(blcs): Added.
+	(blsfill): Added.
+	(blsic): Added.
+	(t1mskc): Added.
+	(tzmsk): Added.
+
+	* i386-init.h: Regenerated.
+
+	* i386-tbl.h: Regenerated
+
+2011-01-04  Quentin Neill  <quentin.neill@amd.com>
+
+	* i386-dis.c (REG_XOP_BMI_F3): New.
+	(PREFIX_BMI_F30F): New.
+	(dis386_twobyte): Redirect to PREFIX_BMI_F30F entry.
+	(reg_table): Add REG_XOP_BMI_F3 table.
+	(prefix_table): Add PREFIX_BMI_F30F table.
+	(x86_64_table): Add andn, bextr, and redirect to
+	REG_XOP_BMI_F3 entry.
+
+	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS, CpuBMI.
+	(cpu_flags): Add CpuBMI.
+
+	* i386-opc.h (CpuBMI): New.
+	(i386_cpu_flags): Add bit cpubmi.
+	(VEXLWP): Rename to VEXVRM.
+	(XOP2REVSOURCESS): New VexSources encoding.
+
+	* i386-opc.tbl (andn): Added.
+	(andn): Added.
+	(bextr): Added.
+	(bextr): Added.
+	(blsi): Added.
+	(blsi): Added.
+	(blsmsk): Added.
+	(blsmsk): Added.
+	(blsr): Added.
+	(blsr): Added.
+	(tzcnt): Added.
+
+	* i386-init.h: Regenerated.
+
+	* i386-tbl.h: Regenerated
+
 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-gen.c (process_copyright): Update copyright to 2011.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 0c807ba..2d9244b 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -599,7 +599,10 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_XOP_LWPCB,
-  REG_XOP_LWP
+  REG_XOP_LWP,
+  REG_XOP_BMI_F3,
+  REG_XOP_TBM_01,
+  REG_XOP_TBM_02,
 };
 
 enum
@@ -1068,7 +1071,8 @@ enum
   PREFIX_VEX_0F3A7D,
   PREFIX_VEX_0F3A7E,
   PREFIX_VEX_0F3A7F,
-  PREFIX_VEX_0F3ADF
+  PREFIX_VEX_0F3ADF,
+  PREFIX_BMI_F30F
 };
 
 enum
@@ -2158,7 +2162,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "ud1",		{ XX } },
   { REG_TABLE (REG_0FBA) },
   { "btcS",		{ Ev, Gv } },
-  { "bsfS",		{ Gv, Ev } },
+  { PREFIX_TABLE (PREFIX_BMI_F30F) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",	{ Gv, Eb } },
   { "movs{wR|x}",	{ Gv, Ew } }, /* yes, there really is movsww ! */
@@ -2759,6 +2763,35 @@ static const struct dis386 reg_table[][8] = {
     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
     { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq } },
   },
+  /* REG_XOP_BMI_F3 */
+  {
+    { Bad_Opcode },
+    { "blsr",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsmsk",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsi",	{ { OP_LWP_E, 0 }, Ev } },
+  },
+  /* REG_XOP_TBM_01 */
+  {
+    { Bad_Opcode },
+    { "blcfill",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsfill",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blcs",	{ { OP_LWP_E, 0 }, Ev } },
+    { "tzmsk",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blcic",	{ { OP_LWP_E, 0 }, Ev } },
+    { "blsic",	{ { OP_LWP_E, 0 }, Ev } },
+    { "t1mskc",	{ { OP_LWP_E, 0 }, Ev } },
+  },
+  /* REG_XOP_TBM_02 */
+  {
+    { Bad_Opcode },
+    { "blcmsk",	{ { OP_LWP_E, 0 }, Ev } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "blci",	{ { OP_LWP_E, 0 }, Ev } },
+  },
+
 };
 
 static const struct dis386 prefix_table[][4] = {
@@ -5354,6 +5387,14 @@ static const struct dis386 prefix_table[][4] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
   },
+
+  /* PREFIX_BMI_F30F */
+  {
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+    { "bsfS",		{ Gv, Ev } },
+    { "tzcntS",		{ Gv, Ev } },
+  },
 };
 
 static const struct dis386 x86_64_table[][2] = {
@@ -6681,8 +6722,8 @@ static const struct dis386 xop_table[][256] = {
   {
     /* 00 */
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { REG_TABLE (REG_XOP_TBM_01) },
+    { REG_TABLE (REG_XOP_TBM_02) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -6989,7 +7030,7 @@ static const struct dis386 xop_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 10 */
-    { Bad_Opcode },
+    { "bextr",	{ Gv, Ev, Iq } },
     { Bad_Opcode },
     { REG_TABLE (REG_XOP_LWP) },
     { Bad_Opcode },
@@ -7828,12 +7869,12 @@ static const struct dis386 vex_table[][256] = {
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
+    { "andn",	{ Gv, { OP_LWP_E, 0 }, Ev } },
+    { REG_TABLE (REG_XOP_BMI_F3) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { "bextr",	{ Gv, Ev, { OP_LWP_E, 0 } } },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 81e51dd..dd73329 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -140,6 +140,10 @@ static initializer cpu_flag_init[] =
     "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4a|CpuABM|CpuAVX|CpuFMA4|CpuXOP" },
   { "CPU_LWP_FLAGS",
     "CpuLWP" },
+  { "CPU_TBM_FLAGS",
+    "CpuTBM" },
+  { "CPU_BMI_FLAGS",
+    "CpuBMI" },
   { "CPU_MOVBE_FLAGS",
     "CpuMovbe" },
   { "CPU_RDTSCP_FLAGS",
@@ -320,6 +324,8 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuFMA4),
   BITFIELD (CpuXOP),
   BITFIELD (CpuLWP),
+  BITFIELD (CpuTBM),
+  BITFIELD (CpuBMI),
   BITFIELD (CpuLM),
   BITFIELD (CpuMovbe),
   BITFIELD (CpuEPT),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index fe546b6..758aab0 100644
Binary files a/opcodes/i386-init.h and b/opcodes/i386-init.h differ
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index fe4fe97..06145d2 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -110,6 +110,10 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
+  /* TBM support required */
+  CpuTBM,
+  /* BMI support required */
+  CpuBMI,
   /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
@@ -186,6 +190,8 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
+      unsigned int cputbm:1;
+      unsigned int cpubmi:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
@@ -304,12 +310,12 @@ enum
 	For assembler, there are no difference between VEX.NDS and
 	VEX.DDS.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
-     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
+     3. VEX.VRM.  Register destination is encoded in VEX.vvvv and one
 	of the operands can access a memory location.
    */
 #define VEXXDS	1
 #define VEXNDD	2
-#define VEXLWP	3
+#define VEXVRM	3
   VexVVVV,
   /* How the VEX.W bit is used:
      0: Set by the REX.W bit.
@@ -338,9 +344,11 @@ enum
      0: <= 2 source operands.
      1: 2 XOP source operands.
      2: 3 source operands.
+     3: 2 XOP source operands but order reversed.
    */
 #define XOP2SOURCES	1
 #define VEX3SOURCES	2
+#define XOP2REVSOURCES	3
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f63919e..678cd1f 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2733,6 +2733,41 @@ lwpval, 3, 0x12, 0x1, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
 lwpins, 3, 0x12, 0x0, 1, CpuLWP, Modrm|VexOpcode=5|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexVVVV=3|NoRex64|Vex, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
 
+// TBM instructions
+bextr,   3, 0x10,     None, 1, CpuTBM, Modrm|VexOpcode=5|VexW=1|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm32|Imm32S, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+bextr,   3, 0x10,     None, 1, CpuTBM, Modrm|VexOpcode=5|VexW=2|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm32|Imm32S, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcfill, 2, 0x01,      0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcfill, 2, 0x01,      0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blci,    2, 0x02,      0x6, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blci,    2, 0x02,      0x6, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcic,   2, 0x01,      0x5, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcic,   2, 0x01,      0x5, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcmsk,  2, 0x02,      0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcmsk,  2, 0x02,      0x1, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blcs,    2, 0x01,      0x3, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blcs,    2, 0x01,      0x3, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsfill, 2, 0x01,      0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsfill, 2, 0x01,      0x2, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsic,   2, 0x01,      0x6, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsic,   2, 0x01,      0x6, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+t1mskc,  2, 0x01,      0x7, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+t1mskc,  2, 0x01,      0x7, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+tzmsk,   2, 0x01,      0x4, 1, CpuTBM, Modrm|VexOpcode=4|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+tzmsk,   2, 0x01,      0x4, 1, CpuTBM, Modrm|VexOpcode=4|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+
+// BMI instructions
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32, Reg32 }
+andn,    3, 0xF2,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64, Reg64 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+bextr,   3, 0xF7,     None, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|VexSources=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64, Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsi,    2, 0xF3,      0x3, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsmsk,  2, 0xF3,      0x2, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|VexOpcode=1|VexW=1|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Reg32|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32 }
+blsr,    2, 0xF3,      0x1, 1, CpuBMI, Modrm|VexOpcode=1|VexW=2|VexVVVV=3|Vex|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Dword|Reg64|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg64 }
+tzcnt,   2, 0xf30fbc, None, 2, CpuBMI, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+
 // AMD 3DNow! instructions.
 
 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5c4e7e8..07f4380 100644
Binary files a/opcodes/i386-tbl.h and b/opcodes/i386-tbl.h differ

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-04 20:26         ` Quentin Neill
@ 2011-01-04 20:58           ` H.J. Lu
  2011-01-05  0:23             ` H.J. Lu
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-04 20:58 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Tue, Jan 4, 2011 at 12:23 PM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>> AMD bdver2 processors.
>>>>>>
>>>>>> The full encoding specification is delayed, however I have posted
>>>>>> abbreviated specs on the gcc mailing list:
>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>
>>>>>
>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>> that you get from git format-patch -1
>>>>>
>>>>> Thanks,
>>>>> Sebastian
>>>>
>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>> --
>>>> Quentin
>>>>
>>>
>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>> without ModrmRegExt.
>>>
>>>
>>
>> You should check i.tm.extension_opcode != None instead.
>>
>> --
>> H.J.
>
> Fixed with the attached.
> Tested and passes with "make check RUNTESTFLAGS=i386.exp".
> Okay to commit?
> --

Comments on i386-dis.c:

1. For insns with VEX encoding, use XXX_VEX_0FXXXXX and sort them.
2. Use vex_len_table to handle invalid vector length.
3. Use VexGdq I just added instead of "{ OP_LWP_E, 0 }"
4. Properly add suffix with

{ "XXXS",          { Gdq, VexGdq, Edq } },


-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-04 20:58           ` H.J. Lu
@ 2011-01-05  0:23             ` H.J. Lu
  2011-01-05 16:46               ` Quentin Neill
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-05  0:23 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Tue, Jan 4, 2011 at 12:58 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Tue, Jan 4, 2011 at 12:23 PM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>> AMD bdver2 processors.
>>>>>>>
>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>
>>>>>>
>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>> that you get from git format-patch -1
>>>>>>
>>>>>> Thanks,
>>>>>> Sebastian
>>>>>
>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>> --
>>>>> Quentin
>>>>>
>>>>
>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>> without ModrmRegExt.
>>>>
>>>>
>>>
>>> You should check i.tm.extension_opcode != None instead.
>>>
>>> --
>>> H.J.
>>
>> Fixed with the attached.
>> Tested and passes with "make check RUNTESTFLAGS=i386.exp".
>> Okay to commit?
>> --
>
> Comments on i386-dis.c:
>
> 1. For insns with VEX encoding, use XXX_VEX_0FXXXXX and sort them.
> 2. Use vex_len_table to handle invalid vector length.
> 3. Use VexGdq I just added instead of "{ OP_LWP_E, 0 }"
> 4. Properly add suffix with
>
> { "XXXS",          { Gdq, VexGdq, Edq } },
>
>

Your BMI implementation has some issues:

[hjl@gnu-6 i386]$ head -7 x86-64-bmi.s

	.allow_index_reg
	.text
	
_start:

    ANDN     %eax,%r15d,%eax
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
[hjl@gnu-6 i386]$ head -9 x86-64-bmi.d
#objdump: -dw
#name: x86-64 BMI

.*: +file format .*

Disassembly of section .text:

0+ <_start>:
[ 	]*[a-f0-9]+:	c4 c2 00 f2 c0       	andn   %r8d,%r15d,%eax
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Your assembler doesn't match your disassembler. I checked in
my BMI implementation:

http://sourceware.org/ml/binutils/2011-01/msg00038.html

Please double check.

Thanks.

-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-05  0:23             ` H.J. Lu
@ 2011-01-05 16:46               ` Quentin Neill
  2011-01-05 17:33                 ` H.J. Lu
  0 siblings, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2011-01-05 16:46 UTC (permalink / raw)
  To: H.J. Lu; +Cc: Sebastian Pop, binutils

On Tue, Jan 4, 2011 at 6:23 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Tue, Jan 4, 2011 at 12:58 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Tue, Jan 4, 2011 at 12:23 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>>> AMD bdver2 processors.
>>>>>>>>
>>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>>
>>>>>>>
>>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>>> that you get from git format-patch -1
>>>>>>>
>>>>>>> Thanks,
>>>>>>> Sebastian
>>>>>>
>>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>>> --
>>>>>> Quentin
>>>>>>
>>>>>
>>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>>> without ModrmRegExt.
>>>>>
>>>>>
>>>>
>>>> You should check i.tm.extension_opcode != None instead.
>>>>
>>>> --
>>>> H.J.
>>>
>>> Fixed with the attached.
>>> Tested and passes with "make check RUNTESTFLAGS=i386.exp".
>>> Okay to commit?
>>> --
>>
>> Comments on i386-dis.c:
>>
>> 1. For insns with VEX encoding, use XXX_VEX_0FXXXXX and sort them.
>> 2. Use vex_len_table to handle invalid vector length.
>> 3. Use VexGdq I just added instead of "{ OP_LWP_E, 0 }"
>> 4. Properly add suffix with
>>
>> { "XXXS",          { Gdq, VexGdq, Edq } },
>>
>>
>
> Your BMI implementation has some issues:
>
> [hjl@gnu-6 i386]$ head -7 x86-64-bmi.s
>
>        .allow_index_reg
>        .text
>
> _start:
>
>    ANDN     %eax,%r15d,%eax
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> [hjl@gnu-6 i386]$ head -9 x86-64-bmi.d
> #objdump: -dw
> #name: x86-64 BMI
>
> .*: +file format .*
>
> Disassembly of section .text:
>
> 0+ <_start>:
> [       ]*[a-f0-9]+:    c4 c2 00 f2 c0          andn   %r8d,%r15d,%eax
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> Your assembler doesn't match your disassembler. I checked in
> my BMI implementation:
>
> http://sourceware.org/ml/binutils/2011-01/msg00038.html
>
> Please double check.
>
> Thanks.
>
> --
> H.J.
>

[Resending to the the list]

I'll work on a TBM patch based on this BMI code.

I looked at VEXNDS and VEXXDS encoding but didn't think modifying
those code paths was the way to go.

Looks okay to me, a couple of questions:
In tc-i386.c why use ~0 as a sentinel instead of MAX_OPERANDS (for mem
on line 5582, or vex_reg on line 5636)?
In i386-dis.c how did you name REG_VEX_0F38F3, I don't see a 0x38
anywhere in the encodings.

In i386-dis.c don't you need to order your REG_VEX enum and entry in
the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
+++ b/opcodes/i386-dis.c
@@ -598,8 +598,8 @@ enum
  REG_VEX_0F71,
  REG_VEX_0F72,
  REG_VEX_0F73,
-  REG_VEX_0FAE,
  REG_VEX_0F38F3,
+  REG_VEX_0FAE,
  REG_XOP_LWPCB,
  REG_XOP_LWP
 };
@@ -2755,13 +2755,6 @@ static const struct dis386 reg_table[][8] = {
    { MOD_TABLE (MOD_VEX_0F73_REG_6) },
    { MOD_TABLE (MOD_VEX_0F73_REG_7) },
  },
-  /* REG_VEX_0FAE */
-  {
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
-    { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
-  },
  /* REG_VEX_0F38F3 */
  {
    { Bad_Opcode },
@@ -2769,6 +2762,13 @@ static const struct dis386 reg_table[][8] = {
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
  },
+  /* REG_VEX_0FAE */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
+    { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
+  },
  /* REG_XOP_LWPCB */
  {
    { "llwpcb", { { OP_LWPCB_E, 0 } } },
-- 
Quentin

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-05 16:46               ` Quentin Neill
@ 2011-01-05 17:33                 ` H.J. Lu
       [not found]                   ` <AANLkTi=cPaH=pSNd+rF_-1y8CTihNUvdaemTKcVVO0s_@mail.gmail.com>
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-05 17:33 UTC (permalink / raw)
  To: Quentin Neill; +Cc: Sebastian Pop, binutils

On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Tue, Jan 4, 2011 at 6:23 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Tue, Jan 4, 2011 at 12:58 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Tue, Jan 4, 2011 at 12:23 PM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Tue, Dec 28, 2010 at 8:10 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Tue, Dec 28, 2010 at 5:53 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Mon, Dec 20, 2010 at 2:55 PM, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> On Mon, Dec 20, 2010 at 4:39 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>>>>>>>> On Mon, Dec 20, 2010 at 16:32, Quentin Neill
>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>> These two patches add support for BMI and TBM ISAs to be introduced in
>>>>>>>>> AMD bdver2 processors.
>>>>>>>>>
>>>>>>>>> The full encoding specification is delayed, however I have posted
>>>>>>>>> abbreviated specs on the gcc mailing list:
>>>>>>>>> BMI: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01766.html
>>>>>>>>> TBM: http://gcc.gnu.org/ml/gcc-patches/2010-10/msg01767.html
>>>>>>>>>
>>>>>>>>
>>>>>>>> Looks like your patch is reversed.  Could you please send another one
>>>>>>>> that you get from git format-patch -1
>>>>>>>>
>>>>>>>> Thanks,
>>>>>>>> Sebastian
>>>>>>>
>>>>>>> Oops.  Reposting with reversed patch.  Thanks for reviewing Sebastian.
>>>>>>> --
>>>>>>> Quentin
>>>>>>>
>>>>>>
>>>>>> Please don't add ModrmRegExt, There are many examples in i386-opt.tbl
>>>>>> without ModrmRegExt.
>>>>>>
>>>>>>
>>>>>
>>>>> You should check i.tm.extension_opcode != None instead.
>>>>>
>>>>> --
>>>>> H.J.
>>>>
>>>> Fixed with the attached.
>>>> Tested and passes with "make check RUNTESTFLAGS=i386.exp".
>>>> Okay to commit?
>>>> --
>>>
>>> Comments on i386-dis.c:
>>>
>>> 1. For insns with VEX encoding, use XXX_VEX_0FXXXXX and sort them.
>>> 2. Use vex_len_table to handle invalid vector length.
>>> 3. Use VexGdq I just added instead of "{ OP_LWP_E, 0 }"
>>> 4. Properly add suffix with
>>>
>>> { "XXXS",          { Gdq, VexGdq, Edq } },
>>>
>>>
>>
>> Your BMI implementation has some issues:
>>
>> [hjl@gnu-6 i386]$ head -7 x86-64-bmi.s
>>
>>        .allow_index_reg
>>        .text
>>
>> _start:
>>
>>    ANDN     %eax,%r15d,%eax
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>> [hjl@gnu-6 i386]$ head -9 x86-64-bmi.d
>> #objdump: -dw
>> #name: x86-64 BMI
>>
>> .*: +file format .*
>>
>> Disassembly of section .text:
>>
>> 0+ <_start>:
>> [       ]*[a-f0-9]+:    c4 c2 00 f2 c0          andn   %r8d,%r15d,%eax
>> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>>
>> Your assembler doesn't match your disassembler. I checked in
>> my BMI implementation:
>>
>> http://sourceware.org/ml/binutils/2011-01/msg00038.html
>>
>> Please double check.
>>
>> Thanks.
>>
>> --
>> H.J.
>>
>
> [Resending to the the list]
>
> I'll work on a TBM patch based on this BMI code.
>
> I looked at VEXNDS and VEXXDS encoding but didn't think modifying
> those code paths was the way to go.
>
> Looks okay to me, a couple of questions:
> In tc-i386.c why use ~0 as a sentinel instead of MAX_OPERANDS (for mem
> on line 5582, or vex_reg on line 5636)?

I used unsigned ~0 to check incorrectly initialized operand.
Setting it to MAX_OPERANDS may still lead to legal, but bad
operand number.

> In i386-dis.c how did you name REG_VEX_0F38F3, I don't see a 0x38
> anywhere in the encodings.

VEX opcode prefixes can be 0F, 0F38 and 0F3A.  0F38F3
is 0F38 F3.

> In i386-dis.c don't you need to order your REG_VEX enum and entry in
> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
> +++ b/opcodes/i386-dis.c
> @@ -598,8 +598,8 @@ enum
>  REG_VEX_0F71,
>  REG_VEX_0F72,
>  REG_VEX_0F73,
> -  REG_VEX_0FAE,
>  REG_VEX_0F38F3,
> +  REG_VEX_0FAE,
>  REG_XOP_LWPCB,
>  REG_XOP_LWP
>  };

I have

  REG_VEX_0F73,
  REG_VEX_0FAE,
  REG_VEX_0F38F3,
  REG_XOP_LWPCB,
  REG_XOP_LWP

Please make sure your source is correct.


-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
       [not found]                         ` <AANLkTinPvGoqBf6gkOtJ_aE_biRPijcpUW6xBOcXKGw9@mail.gmail.com>
@ 2011-01-06 22:45                           ` Quentin Neill
  2011-01-06 22:49                             ` H.J. Lu
  0 siblings, 1 reply; 23+ messages in thread
From: Quentin Neill @ 2011-01-06 22:45 UTC (permalink / raw)
  To: H.J. Lu; +Cc: binutils, Sebastian Pop

[-- Attachment #1: Type: text/plain, Size: 1832 bytes --]

On Thu, Jan 6, 2011 at 2:26 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Jan 6, 2011 at 12:20 PM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Wed, Jan 5, 2011 at 12:22 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Wed, Jan 5, 2011 at 9:41 AM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Wed, Jan 5, 2011 at 11:33 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> In i386-dis.c don't you need to order your REG_VEX enum and entry in
>>>>>> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
>>>>>> +++ b/opcodes/i386-dis.c
>>>>>> @@ -598,8 +598,8 @@ enum
>>>>>>  REG_VEX_0F71,
>>>>>>  REG_VEX_0F72,
>>>>>>  REG_VEX_0F73,
>>>>>> -  REG_VEX_0FAE,
>>>>>>  REG_VEX_0F38F3,
>>>>>> +  REG_VEX_0FAE,
>>>>>>  REG_XOP_LWPCB,
>>>>>>  REG_XOP_LWP
>>>>>>  };
>>>>>
>>>>> I have
>>>>>
>>>>>  REG_VEX_0F73,
>>>>>  REG_VEX_0FAE,
>>>>>  REG_VEX_0F38F3,
>>>>>  REG_XOP_LWPCB,
>>>>>  REG_XOP_LWP
>>>>>
>>>>> Please make sure your source is correct.
>>>>>
>>>>>
>>>>> --
>>>>> H.J.
>>>>
>>>> That was a small patch I proposed to move REG_VEX_0F38F3 above
>>>> REG_VEX_0FAE to make them numerically sorted.
>>>
>>> That is wrong.  VEX opcodes are sorted by
>>>
>>> VEX_0FXX
>>> VEX_0F38XX
>>> VEX_0F3AXX
>>>
>>>
>>> --
>>> H.J.
>>>
>>
>> I also notice you did not implement ".bmi" cpu_arch entry in
>> tc-i386.c, can you comment on that?
>
> You should submit a new BMI patch minus what I have
> implemented for you.
>
>> Should I follow your lead concerning adding a ".tbm" directive?
>
> No.
>
>
> --
> H.J.
>

Patch adds BMI docs, .bmi arch directive and tests.

Passes "make -k check RUNTESTFLAGS=i386.exp", okay to commit?

-- 
Quentin

[-- Attachment #2: 7045_bdver2_bmi_fwp.diff.txt --]
[-- Type: text/plain, Size: 6736 bytes --]

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3177aa5..8d04da5 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2011-01-06  Quentin Neill  <quentin.neill@amd.com>
+
+	* config/tc-i386.c (cpu_arch): Add CPU_BMI_FLAGS.
+
+	* doc/c-i386.texi (i386-BMI): New section.
+
 2011-01-06  Paul Koning  <ni1d@arrl.net>
 
 	* config/tc-pdp11.c (parse_op_no_deferred): Allow PC-relative
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 2e28d8e..6f30dda 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -725,6 +725,8 @@ static const arch_entry cpu_arch[] =
     CPU_SSE4A_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
     CPU_ABM_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
+    CPU_BMI_FLAGS, 0, 0 },
 };
 
 #ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 5c1c6bd..4ea33f6 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -35,6 +35,7 @@ extending the Intel architecture to 64-bits.
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-LWP::                    AMD's Lightweight Profiling Instructions
+* i386-BMI::                    Bit Manipulation Instruction
 * i386-16bit::                  Writing 16-bit Code
 * i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
@@ -845,6 +846,21 @@ For detailed information on the LWP instruction set, see the
 @cite{AMD Lightweight Profiling Specification} available at
 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
 
+@node i386-BMI
+@section Bit Manipulation Instructions
+
+@cindex BMI, i386
+@cindex BMI, x86-64
+
+@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
+
+BMI instructions provide several instructions implementing individual
+bit manipulation operations such as isolation, masking, setting, or
+resetting.  
+
+@c Need to add a specification citation here when available.
+
+
 @node i386-16bit
 @section Writing 16-bit Code
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d13c734..f87d642 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2011-01-06  Quentin Neill  <quentin.neill@amd.com>
+
+	* gas/i386/arch-10.s: Add a BMI instruction.
+	* gas/i386/x86-64-arch-2.s: Likewise.
+	* gas/i386/arch-10.d: Add bmi flag and BMI instruction pattern.
+	* gas/i386/x86-64-arch-2.d: Likewise.
+	* gas/i386/arch-10-1.l: Add BMI instruction pattern.
+	* gas/i386/arch-10-2.l: Likewise.
+	* gas/i386/arch-10-3.l: Likewise.
+	* gas/i386/arch-10-4.l: Likewise.
+
 2011-01-06  Paul Koning  <ni1d@arrl.net>
 
 	* gas/pdp11/absreloc.s: New.
diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l
index 0b78958..ee1e316 100644
--- a/gas/testsuite/gas/i386/arch-10-1.l
+++ b/gas/testsuite/gas/i386/arch-10-1.l
@@ -29,6 +29,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -98,3 +99,5 @@ GAS LISTING .*
 [ 	]*60[ 	]+xstorerng
 [ 	]*61[ 	]+\# nop
 [ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l
index d9e1b51..f1abcea 100644
--- a/gas/testsuite/gas/i386/arch-10-2.l
+++ b/gas/testsuite/gas/i386/arch-10-2.l
@@ -28,6 +28,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -97,3 +98,5 @@ GAS LISTING .*
 [ 	]*60[ 	]+xstorerng
 [ 	]*61[ 	]+\# nop
 [ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l
index 75c07ec..0b5d362 100644
--- a/gas/testsuite/gas/i386/arch-10-3.l
+++ b/gas/testsuite/gas/i386/arch-10-3.l
@@ -21,6 +21,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -93,3 +94,5 @@ GAS LISTING .*
 [ 	]*60[ 	]+xstorerng
 [ 	]*61[ 	]+\# nop
 [ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l
index 3c40045..8cca603 100644
--- a/gas/testsuite/gas/i386/arch-10-4.l
+++ b/gas/testsuite/gas/i386/arch-10-4.l
@@ -19,6 +19,7 @@
 .*:58: Error: .*
 .*:60: Error: .*
 .*:62: Error: .*
+.*:64: Error: .*
 GAS LISTING .*
 
 
@@ -91,3 +92,5 @@ GAS LISTING .*
 [ 	]*60[ 	]+xstorerng
 [ 	]*61[ 	]+\# nop
 [ 	]*62[ 	]+nopl \(%eax\)
+[ 	]*63[ 	]+\# BMI
+[ 	]*64[ 	]+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d
index 3efd52d..2225fe0 100644
--- a/gas/testsuite/gas/i386/arch-10.d
+++ b/gas/testsuite/gas/i386/arch-10.d
@@ -1,4 +1,4 @@
-#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: i386 arch 10
 
@@ -37,4 +37,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
 [ 	]*[a-f0-9]+:	0f 1f 00             	nopl   \(%eax\)
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s
index d0fb12b..f39f70b 100644
--- a/gas/testsuite/gas/i386/arch-10.s
+++ b/gas/testsuite/gas/i386/arch-10.s
@@ -60,3 +60,5 @@ lzcnt %ecx,%ebx
 xstorerng
 # nop
 nopl (%eax)
+# BMI
+blsr %ecx,%ebx
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.d b/gas/testsuite/gas/i386/x86-64-arch-2.d
index 9cd1306..ac09453 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.d
@@ -1,4 +1,4 @@
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: x86-64 arch 2
 
@@ -36,4 +36,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload 
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng 
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-2.s b/gas/testsuite/gas/i386/x86-64-arch-2.s
index ddc0d40..962f15e 100644
--- a/gas/testsuite/gas/i386/x86-64-arch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-arch-2.s
@@ -58,3 +58,5 @@ vmload
 lzcnt %ecx,%ebx
 # PadLock
 xstorerng
+# BMI
+blsr %ecx,%ebx

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-06 22:45                           ` Quentin Neill
@ 2011-01-06 22:49                             ` H.J. Lu
  2011-01-07 23:29                               ` H.J. Lu
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-06 22:49 UTC (permalink / raw)
  To: Quentin Neill; +Cc: binutils, Sebastian Pop

On Thu, Jan 6, 2011 at 2:45 PM, Quentin Neill
<quentin.neill.gnu@gmail.com> wrote:
> On Thu, Jan 6, 2011 at 2:26 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Thu, Jan 6, 2011 at 12:20 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Wed, Jan 5, 2011 at 12:22 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Wed, Jan 5, 2011 at 9:41 AM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Wed, Jan 5, 2011 at 11:33 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> In i386-dis.c don't you need to order your REG_VEX enum and entry in
>>>>>>> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
>>>>>>> +++ b/opcodes/i386-dis.c
>>>>>>> @@ -598,8 +598,8 @@ enum
>>>>>>>  REG_VEX_0F71,
>>>>>>>  REG_VEX_0F72,
>>>>>>>  REG_VEX_0F73,
>>>>>>> -  REG_VEX_0FAE,
>>>>>>>  REG_VEX_0F38F3,
>>>>>>> +  REG_VEX_0FAE,
>>>>>>>  REG_XOP_LWPCB,
>>>>>>>  REG_XOP_LWP
>>>>>>>  };
>>>>>>
>>>>>> I have
>>>>>>
>>>>>>  REG_VEX_0F73,
>>>>>>  REG_VEX_0FAE,
>>>>>>  REG_VEX_0F38F3,
>>>>>>  REG_XOP_LWPCB,
>>>>>>  REG_XOP_LWP
>>>>>>
>>>>>> Please make sure your source is correct.
>>>>>>
>>>>>>
>>>>>> --
>>>>>> H.J.
>>>>>
>>>>> That was a small patch I proposed to move REG_VEX_0F38F3 above
>>>>> REG_VEX_0FAE to make them numerically sorted.
>>>>
>>>> That is wrong.  VEX opcodes are sorted by
>>>>
>>>> VEX_0FXX
>>>> VEX_0F38XX
>>>> VEX_0F3AXX
>>>>
>>>>
>>>> --
>>>> H.J.
>>>>
>>>
>>> I also notice you did not implement ".bmi" cpu_arch entry in
>>> tc-i386.c, can you comment on that?
>>
>> You should submit a new BMI patch minus what I have
>> implemented for you.
>>
>>> Should I follow your lead concerning adding a ".tbm" directive?
>>
>> No.
>>
>>
>> --
>> H.J.
>>
>
> Patch adds BMI docs, .bmi arch directive and tests.
>
> Passes "make -k check RUNTESTFLAGS=i386.exp", okay to commit?
>

OK.

Thanks.


-- 
H.J.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-06 22:49                             ` H.J. Lu
@ 2011-01-07 23:29                               ` H.J. Lu
  2011-01-10 14:15                                 ` Quentin Neill
  0 siblings, 1 reply; 23+ messages in thread
From: H.J. Lu @ 2011-01-07 23:29 UTC (permalink / raw)
  To: Quentin Neill; +Cc: binutils, Sebastian Pop

On Thu, Jan 6, 2011 at 2:49 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Jan 6, 2011 at 2:45 PM, Quentin Neill
> <quentin.neill.gnu@gmail.com> wrote:
>> On Thu, Jan 6, 2011 at 2:26 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> On Thu, Jan 6, 2011 at 12:20 PM, Quentin Neill
>>> <quentin.neill.gnu@gmail.com> wrote:
>>>> On Wed, Jan 5, 2011 at 12:22 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>> On Wed, Jan 5, 2011 at 9:41 AM, Quentin Neill
>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>> On Wed, Jan 5, 2011 at 11:33 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>>> On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>> In i386-dis.c don't you need to order your REG_VEX enum and entry in
>>>>>>>> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
>>>>>>>> +++ b/opcodes/i386-dis.c
>>>>>>>> @@ -598,8 +598,8 @@ enum
>>>>>>>>  REG_VEX_0F71,
>>>>>>>>  REG_VEX_0F72,
>>>>>>>>  REG_VEX_0F73,
>>>>>>>> -  REG_VEX_0FAE,
>>>>>>>>  REG_VEX_0F38F3,
>>>>>>>> +  REG_VEX_0FAE,
>>>>>>>>  REG_XOP_LWPCB,
>>>>>>>>  REG_XOP_LWP
>>>>>>>>  };
>>>>>>>
>>>>>>> I have
>>>>>>>
>>>>>>>  REG_VEX_0F73,
>>>>>>>  REG_VEX_0FAE,
>>>>>>>  REG_VEX_0F38F3,
>>>>>>>  REG_XOP_LWPCB,
>>>>>>>  REG_XOP_LWP
>>>>>>>
>>>>>>> Please make sure your source is correct.
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> H.J.
>>>>>>
>>>>>> That was a small patch I proposed to move REG_VEX_0F38F3 above
>>>>>> REG_VEX_0FAE to make them numerically sorted.
>>>>>
>>>>> That is wrong.  VEX opcodes are sorted by
>>>>>
>>>>> VEX_0FXX
>>>>> VEX_0F38XX
>>>>> VEX_0F3AXX
>>>>>
>>>>>
>>>>> --
>>>>> H.J.
>>>>>
>>>>
>>>> I also notice you did not implement ".bmi" cpu_arch entry in
>>>> tc-i386.c, can you comment on that?
>>>
>>> You should submit a new BMI patch minus what I have
>>> implemented for you.
>>>
>>>> Should I follow your lead concerning adding a ".tbm" directive?
>>>
>>> No.
>>>
>>>
>>> --
>>> H.J.
>>>
>>
>> Patch adds BMI docs, .bmi arch directive and tests.
>>
>> Passes "make -k check RUNTESTFLAGS=i386.exp", okay to commit?
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Could you please remove "-k" next time when you run tests?
All x86 binutils tests should pass on Linux.  I checked in this
patch to fix the regression.

-- 
H.J.
----
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6f60a1a..67eee86 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-01-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/ilp32/x86-64-arch-2.d: Add bmi flag and BMI instruction
+	pattern.
+
 2011-01-07  Quentin Neill  <quentin.neill@amd.com>

 	* gas/i386/arch-10.s: Add a BMI instruction.
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d b/gas/testsuite/gas/i3
86/ilp32/x86-64-arch-2.d
index 10c3565..779a95a 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
@@ -1,5 +1,5 @@
 #source: ../x86-64-arch-2.s
-#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflu
sh+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
+#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflu
sh+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
 #objdump: -dw
 #name: x86-64 (ILP32) arch 2

@@ -37,4 +37,5 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	0f 01 da             	vmload
 [ 	]*[a-f0-9]+:	f3 0f bd d9          	lzcnt  %ecx,%ebx
 [ 	]*[a-f0-9]+:	0f a7 c0             	xstore-rng
+[ 	]*[a-f0-9]+:	c4 e2 60 f3 c9       	blsr   %ecx,%ebx
 #pass

^ permalink raw reply	[flat|nested] 23+ messages in thread

* Re: [PATCH] AMD bdver2 processors 1/2 - BMI
  2011-01-07 23:29                               ` H.J. Lu
@ 2011-01-10 14:15                                 ` Quentin Neill
  0 siblings, 0 replies; 23+ messages in thread
From: Quentin Neill @ 2011-01-10 14:15 UTC (permalink / raw)
  To: H.J. Lu; +Cc: binutils, Sebastian Pop

On Fri, Jan 7, 2011 at 5:29 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Jan 6, 2011 at 2:49 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Thu, Jan 6, 2011 at 2:45 PM, Quentin Neill
>> <quentin.neill.gnu@gmail.com> wrote:
>>> On Thu, Jan 6, 2011 at 2:26 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>> On Thu, Jan 6, 2011 at 12:20 PM, Quentin Neill
>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>> On Wed, Jan 5, 2011 at 12:22 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>> On Wed, Jan 5, 2011 at 9:41 AM, Quentin Neill
>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>> On Wed, Jan 5, 2011 at 11:33 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>>>>>>>> On Wed, Jan 5, 2011 at 8:45 AM, Quentin Neill
>>>>>>>> <quentin.neill.gnu@gmail.com> wrote:
>>>>>>>>> In i386-dis.c don't you need to order your REG_VEX enum and entry in
>>>>>>>>> the reg_table (move REG_VEX_0F38F3 above REG_VEX_0FAE):
>>>>>>>>> +++ b/opcodes/i386-dis.c
>>>>>>>>> @@ -598,8 +598,8 @@ enum
>>>>>>>>>  REG_VEX_0F71,
>>>>>>>>>  REG_VEX_0F72,
>>>>>>>>>  REG_VEX_0F73,
>>>>>>>>> -  REG_VEX_0FAE,
>>>>>>>>>  REG_VEX_0F38F3,
>>>>>>>>> +  REG_VEX_0FAE,
>>>>>>>>>  REG_XOP_LWPCB,
>>>>>>>>>  REG_XOP_LWP
>>>>>>>>>  };
>>>>>>>>
>>>>>>>> I have
>>>>>>>>
>>>>>>>>  REG_VEX_0F73,
>>>>>>>>  REG_VEX_0FAE,
>>>>>>>>  REG_VEX_0F38F3,
>>>>>>>>  REG_XOP_LWPCB,
>>>>>>>>  REG_XOP_LWP
>>>>>>>>
>>>>>>>> Please make sure your source is correct.
>>>>>>>>
>>>>>>>>
>>>>>>>> --
>>>>>>>> H.J.
>>>>>>>
>>>>>>> That was a small patch I proposed to move REG_VEX_0F38F3 above
>>>>>>> REG_VEX_0FAE to make them numerically sorted.
>>>>>>
>>>>>> That is wrong.  VEX opcodes are sorted by
>>>>>>
>>>>>> VEX_0FXX
>>>>>> VEX_0F38XX
>>>>>> VEX_0F3AXX
>>>>>>
>>>>>>
>>>>>> --
>>>>>> H.J.
>>>>>>
>>>>>
>>>>> I also notice you did not implement ".bmi" cpu_arch entry in
>>>>> tc-i386.c, can you comment on that?
>>>>
>>>> You should submit a new BMI patch minus what I have
>>>> implemented for you.
>>>>
>>>>> Should I follow your lead concerning adding a ".tbm" directive?
>>>>
>>>> No.
>>>>
>>>>
>>>> --
>>>> H.J.
>>>>
>>>
>>> Patch adds BMI docs, .bmi arch directive and tests.
>>>
>>> Passes "make -k check RUNTESTFLAGS=i386.exp", okay to commit?
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> Could you please remove "-k" next time when you run tests?
> All x86 binutils tests should pass on Linux.  I checked in this
> patch to fix the regression.
>
> --
> H.J.
> ----
> diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
> index 6f60a1a..67eee86 100644
> --- a/gas/testsuite/ChangeLog
> +++ b/gas/testsuite/ChangeLog
> @@ -1,3 +1,8 @@
> +2011-01-07  H.J. Lu  <hongjiu.lu@intel.com>
> +
> +       * gas/i386/ilp32/x86-64-arch-2.d: Add bmi flag and BMI instruction
> +       pattern.
> +
>  2011-01-07  Quentin Neill  <quentin.neill@amd.com>
>
>        * gas/i386/arch-10.s: Add a BMI instruction.
> diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d b/gas/testsuite/gas/i3
> 86/ilp32/x86-64-arch-2.d
> index 10c3565..779a95a 100644
> --- a/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
> +++ b/gas/testsuite/gas/i386/ilp32/x86-64-arch-2.d
> @@ -1,5 +1,5 @@
>  #source: ../x86-64-arch-2.s
> -#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflu
> sh+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock
> +#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflu
> sh+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
>  #objdump: -dw
>  #name: x86-64 (ILP32) arch 2
>
> @@ -37,4 +37,5 @@ Disassembly of section .text:
>  [      ]*[a-f0-9]+:    0f 01 da                vmload
>  [      ]*[a-f0-9]+:    f3 0f bd d9             lzcnt  %ecx,%ebx
>  [      ]*[a-f0-9]+:    0f a7 c0                xstore-rng
> +[      ]*[a-f0-9]+:    c4 e2 60 f3 c9          blsr   %ecx,%ebx
>  #pass

Yes.  Thanks for the fix.
-- 
Quentin

^ permalink raw reply	[flat|nested] 23+ messages in thread

end of thread, other threads:[~2011-01-10 14:15 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-12-20 22:33 [PATCH] AMD bdver2 processors 1/2 - BMI Quentin Neill
2010-12-20 22:56 ` Sebastian Pop
2010-12-20 23:25   ` Quentin Neill
2010-12-21  2:30     ` Sebastian Pop
2010-12-22  0:57       ` Quentin Neill
2010-12-28 13:56     ` H.J. Lu
2010-12-28 17:02       ` H.J. Lu
2011-01-03 16:10         ` Quentin Neill
2011-01-03 16:36           ` H.J. Lu
2011-01-04  0:06             ` Quentin Neill
2011-01-04  0:35               ` H.J. Lu
2011-01-04 15:12                 ` Quentin Neill
2011-01-04 15:24                   ` H.J. Lu
2011-01-04 20:21                     ` Quentin Neill
2011-01-04 20:26         ` Quentin Neill
2011-01-04 20:58           ` H.J. Lu
2011-01-05  0:23             ` H.J. Lu
2011-01-05 16:46               ` Quentin Neill
2011-01-05 17:33                 ` H.J. Lu
     [not found]                   ` <AANLkTi=cPaH=pSNd+rF_-1y8CTihNUvdaemTKcVVO0s_@mail.gmail.com>
     [not found]                     ` <AANLkTimgKyiu+X09MGXp8hsKpfDRLWKjQCtUNWYBDJN_@mail.gmail.com>
     [not found]                       ` <AANLkTinrtwjkqjc6owRxH3ppqn8BHCNGpPzpe9q13dcS@mail.gmail.com>
     [not found]                         ` <AANLkTinPvGoqBf6gkOtJ_aE_biRPijcpUW6xBOcXKGw9@mail.gmail.com>
2011-01-06 22:45                           ` Quentin Neill
2011-01-06 22:49                             ` H.J. Lu
2011-01-07 23:29                               ` H.J. Lu
2011-01-10 14:15                                 ` Quentin Neill

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