From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 442423858430 for ; Mon, 8 Jan 2024 07:59:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 442423858430 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 442423858430 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::62f ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704700793; cv=none; b=wHCLHoToZLLGEMY1jiTg9VXf8Bu1ZB+boRgziptsaXi7Bx4SiwhMopdtJQRKw5IoKNohG6SH+gr7UISAu5mG8tpMsGoaIUHXVhEH4wx/hsVMt/iaA2CCPcTjj4maB34uc06PlVOHaO+cfxK7ELVuUn7Tg6POjRgt02plN/O9RNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704700793; c=relaxed/simple; bh=AFnmcyvzsLjWAkXsAvSra+YbXbRNS3Dt+ZbmJG9zu1E=; h=DKIM-Signature:From:Message-Id:Mime-Version:Subject:Date:To; b=DYDc4K3L4urjYbywnUFT4m1u5QRvo7E2YixLMhNFV5ze8V0v6vVVo+ERnkQMa7MBToyvC3NTEAeiR0liHPAj35KqvredFX8yolQOP0s61I8WpD9WgA8o59MBpIVi9c7RHJFxDW4MUgcZHr+XBPVg6rqyhtfnSF5fDXZE1+osSq4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1d51bf8a7dcso2884135ad.1 for ; Sun, 07 Jan 2024 23:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704700787; x=1705305587; darn=sourceware.org; h=references:to:cc:in-reply-to:date:subject:mime-version:message-id :from:from:to:cc:subject:date:message-id:reply-to; bh=dInVS0miaaUA0r6+T4+CkfKZb5mvcp00Uys6Cs+pufE=; b=KGVacYNy7/yJQ3zS2snX0NVx6anrIssfNGIXvsHI28XAocMLABw8diZUxFXSmaUt3J SvnFrZ11qE2fJHXQHiWYN51tqB1mYCMGAc8ypvRPjIeKpYNjdschNHGH2qSajssVGsgF dq3cALaxehXGHJgh9fEZeRfarCm6rdeOUoFtFBAFayYXLwaeszFN9HMOroDMUPuVkI4a ClvUuu5nkOj+GkUnPFCZKjxvJoUlTOurkxwmr02rYeRiX5adyfGOWDciJCHKcZCZSWig BkwmXLvl53iW49KSumvr9iG1XKX1s8fsqzU1sjK0/mNyAr+WI7PdnM9H9y3euP0K4jt0 XdGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704700787; x=1705305587; h=references:to:cc:in-reply-to:date:subject:mime-version:message-id :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dInVS0miaaUA0r6+T4+CkfKZb5mvcp00Uys6Cs+pufE=; b=qp2YuwM5V9puXyXBeXuc9s+DZ/+SKZUDI4olU9eD7xyf2cJcCDJJbiqKVfFvoTZuKV ocq4zrfmP18U3ncs7IRu6Nwdw8xfORJfYiMHfAcmpLALGt1olO6lt50CBAtWvUOUEK6B gK6+tjNcTv/YLA4LiqPrIAnDmU0uZnbPDmiuPxjq+j4PiDUzzRQQI3sT8C4lqaQ9dUGb wwloKOvBA2s9IYjZWMdhed3IDAEjnV1PggM4tEW+gE/1MkbIgCihUHod3NeUSliQQ3vo NnwQPQHbHshy1yleS+FJIyj1VwK7f4L8vF2ZKbDdPDE8RUTUklozKI+KhDG9t4xn+xsN 0vZw== X-Gm-Message-State: AOJu0Yx7ShvSYiXWOw5EFABRTzUqggECtcKujUMJRQNrhT2x3JXgneTF OXkNfs6D6BBHfPMopctvnNNO90L6NkVbbEbz X-Google-Smtp-Source: AGHT+IEw+QaQrRcDqnOlq1nYvutzp6+Q5x3TbYOcKVhxtudpmaS3aHLDWwlMbgFvTmb3y99cFPLpZw== X-Received: by 2002:a17:902:dac1:b0:1d4:b46d:81fe with SMTP id q1-20020a170902dac100b001d4b46d81femr6848720plx.3.1704700786867; Sun, 07 Jan 2024 23:59:46 -0800 (PST) Received: from smtpclient.apple (zz20184013906F627101.userreverse.dion.ne.jp. [111.98.113.1]) by smtp.gmail.com with ESMTPSA id j4-20020a170902c3c400b001d472670a30sm3725017plj.162.2024.01.07.23.59.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jan 2024 23:59:46 -0800 (PST) From: Tatsuyuki Ishi Message-Id: Content-Type: multipart/alternative; boundary="Apple-Mail=_4DF606EC-8DB1-4765-888C-6522C0CE9EF5" Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.300.61.1.2\)) Subject: Re: [PATCH v5 4/5] LoongArch: Add support for TLS LD/GD/DESC relaxation Date: Mon, 8 Jan 2024 16:59:30 +0900 In-Reply-To: Cc: Fangrui Song , binutils@sourceware.org, xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, mengqinggang , xry111@xry111.site, i.swmail@xen0n.name, Fangrui Song , luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn To: Lulu Cai References: <20231222114243.1836112-1-cailulu@loongson.cn> <20231222114243.1836112-5-cailulu@loongson.cn> <6f636b66-e747-8882-0138-2f55529ef280@loongson.cn> <71198CD4-E934-4458-BF2F-1C46E792CCDE@gmail.com> X-Mailer: Apple Mail (2.3774.300.61.1.2) X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --Apple-Mail=_4DF606EC-8DB1-4765-888C-6522C0CE9EF5 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On Jan 8, 2024, at 15:00, Lulu Cai wrote: >=20 > On 1/8/24 8:22 AM, Fangrui Song wrote: >> On Sun, Jan 7, 2024 at 3:00=E2=80=AFPM Tatsuyuki Ishi > wrote: >>> On Dec 29, 2023, at 19:45, Lulu Cai wrote: >>>=20 >>> On 2023/12/28 at 10:38 PM, Tatsuyuki Ishi Wrote: >>>=20 >>> On Dec 22, 2023, at 20:42, Lulu Cai wrote: >>>=20 >>> From: mengqinggang >>>=20 >>> The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. >>> Relaxation is only performed when the TLS model transition is not possi= ble. >>> --- >>> bfd/bfd-in2.h | 3 + >>> bfd/elfnn-loongarch.c | 174 +++++++- >>> bfd/elfxx-loongarch.c | 60 +++ >>> bfd/libbfd.h | 3 + >>> bfd/reloc.c | 7 + >>> gas/config/tc-loongarch.c | 8 +- >>> gas/testsuite/gas/loongarch/macro_op.d | 128 +++--- >>> gas/testsuite/gas/loongarch/macro_op_32.d | 120 +++--- >>> .../gas/loongarch/macro_op_large_abs.d | 160 +++---- >>> .../gas/loongarch/macro_op_large_pc.d | 160 +++---- >>> include/elf/loongarch.h | 4 + >>> ld/testsuite/ld-loongarch-elf/macro_op.d | 391 +++++++++--------- >>> ld/testsuite/ld-loongarch-elf/macro_op_32.d | 120 +++--- >>> 13 files changed, 795 insertions(+), 543 deletions(-) >>>=20 >>> diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h >>> index 85251aa0edd..782845926ea 100644 >>> --- a/bfd/bfd-in2.h >>> +++ b/bfd/bfd-in2.h >>> @@ -7473,6 +7473,9 @@ enum bfd_reloc_code_real >>> BFD_RELOC_LARCH_TLS_DESC64_HI12, >>> BFD_RELOC_LARCH_TLS_DESC_LD, >>> BFD_RELOC_LARCH_TLS_DESC_CALL, >>> + BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, >>> + BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, >>> + BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, >>> BFD_RELOC_UNUSED >>> }; >>> typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; >>> diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c >>> index 1347d13d2e2..bd448cda453 100644 >>> --- a/bfd/elfnn-loongarch.c >>> +++ b/bfd/elfnn-loongarch.c >>> @@ -2285,7 +2285,9 @@ perform_relocation (const Elf_Internal_Rela *rel,= asection *input_section, >>> case R_LARCH_TLS_DESC_LO12: >>> case R_LARCH_TLS_DESC64_LO20: >>> case R_LARCH_TLS_DESC64_HI12: >>> - >>> + case R_LARCH_TLS_LD_PCREL20_S2: >>> + case R_LARCH_TLS_GD_PCREL20_S2: >>> + case R_LARCH_TLS_DESC_PCREL20_S2: >>> r =3D loongarch_check_offset (rel, input_section); >>> if (r !=3D bfd_reloc_ok) >>> break; >>> @@ -3674,6 +3676,9 @@ loongarch_elf_relocate_section (bfd *output_bfd, = struct bfd_link_info *info, >>> case R_LARCH_TLS_GD_HI20: >>> case R_LARCH_TLS_DESC_PC_HI20: >>> case R_LARCH_TLS_DESC_HI20: >>> + case R_LARCH_TLS_LD_PCREL20_S2: >>> + case R_LARCH_TLS_GD_PCREL20_S2: >>> + case R_LARCH_TLS_DESC_PCREL20_S2: >>> BFD_ASSERT (rel->r_addend =3D=3D 0); >>> unresolved_reloc =3D false; >>>=20 >>> @@ -3682,7 +3687,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, = struct bfd_link_info *info, >>> is_ie =3D true; >>>=20 >>> if (r_type =3D=3D R_LARCH_TLS_DESC_PC_HI20 >>> - || r_type =3D=3D R_LARCH_TLS_DESC_HI20) >>> + || r_type =3D=3D R_LARCH_TLS_DESC_HI20 >>> + || r_type =3D=3D R_LARCH_TLS_DESC_PCREL20_S2) >>> is_desc =3D true; >>>=20 >>> bfd_vma got_off =3D 0; >>> @@ -3813,7 +3819,11 @@ loongarch_elf_relocate_section (bfd *output_bfd,= struct bfd_link_info *info, >>> || r_type =3D=3D R_LARCH_TLS_IE_PC_HI20 >>> || r_type =3D=3D R_LARCH_TLS_DESC_PC_HI20) >>> RELOCATE_CALC_PC32_HI20 (relocation, pc); >>> - >>> + else if (r_type =3D=3D R_LARCH_TLS_LD_PCREL20_S2 >>> + || r_type =3D=3D R_LARCH_TLS_GD_PCREL20_S2 >>> + || r_type =3D=3D R_LARCH_TLS_DESC_PCREL20_S2) >>> + relocation -=3D pc; >>> + /* else {} ABS relocations. */ >>> break; >>>=20 >>> case R_LARCH_TLS_DESC_PC_LO12: >>> @@ -4244,6 +4254,85 @@ loongarch_relax_align (bfd *abfd, asection *sec, >>> addend - need_nop_bytes, link_info); >>> } >>>=20 >>> +/* Relax pcalau12i + addi.d of TLS LD/GD/DESC to pcaddi. */ >>> +static bool >>> +loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sy= m_sec, >>> + Elf_Internal_Rela *rel_hi, bfd_vma symval, >>> + struct bfd_link_info *info, bool *again) >>> +{ >>> + bfd_byte *contents =3D elf_section_data (sec)->this_hdr.contents; >>> + Elf_Internal_Rela *rel_lo =3D rel_hi + 2; >>> + uint32_t pca =3D bfd_get (32, abfd, contents + rel_hi->r_offset); >>> + uint32_t add =3D bfd_get (32, abfd, contents + rel_lo->r_offset); >>> + uint32_t rd =3D pca & 0x1f; >>> + >>> + /* This section's output_offset need to subtract the bytes of instru= ctions >>> + relaxed by the previous sections, so it needs to be updated befor= ehand. >>> + size_input_section already took care of updating it after relaxat= ion, >>> + so we additionally update once here. */ >>> + sec->output_offset =3D sec->output_section->size; >>> + bfd_vma pc =3D sec_addr (sec) + rel_hi->r_offset; >>> + >>> + /* If pc and symbol not in the same segment, add/sub segment alignme= nt. >>> + FIXME: if there are multiple readonly segments? */ >>> + if (!(sym_sec->flags & SEC_READONLY)) >>> + { >>> + if (symval > pc) >>> + pc -=3D info->maxpagesize; >>> + else if (symval < pc) >>> + pc +=3D info->maxpagesize; >>> + } >>> + >>> + const uint32_t addi_d =3D 0x02c00000; >>> + const uint32_t pcaddi =3D 0x18000000; >>> + >>> + /* Is pcalau12i + addi.d insns? */ >>> + if ((ELFNN_R_TYPE (rel_lo->r_info) !=3D R_LARCH_GOT_PC_LO12 >>> + && ELFNN_R_TYPE (rel_lo->r_info) !=3D R_LARCH_TLS_DESC_PC_LO12) >>> + || (ELFNN_R_TYPE ((rel_lo + 1)->r_info) !=3D R_LARCH_RELAX) >>> + || (ELFNN_R_TYPE ((rel_hi + 1)->r_info) !=3D R_LARCH_RELAX) >>> + || (rel_hi->r_offset + 4 !=3D rel_lo->r_offset) >>> + || ((add & addi_d) !=3D addi_d) >>> + /* Is pcalau12i $rd + addi.d $rd,$rd? */ >>> + || ((add & 0x1f) !=3D rd) >>> + || (((add >> 5) & 0x1f) !=3D rd) >>> + /* Can be relaxed to pcaddi? */ >>> + || (symval & 0x3) /* 4 bytes align. */ >>> + || ((bfd_signed_vma)(symval - pc) < (bfd_signed_vma)(int32_t)0xf= fe00000) >>> + || ((bfd_signed_vma)(symval - pc) > (bfd_signed_vma)(int32_t)0x1= ffffc)) >>> + return false; >>> + >>> + /* Continue next relax trip. */ >>> + *again =3D true; >>> + >>> + pca =3D pcaddi | rd; >>> + bfd_put (32, abfd, pca, contents + rel_hi->r_offset); >>> + >>> + /* Adjust relocations. */ >>> + switch (ELFNN_R_TYPE (rel_hi->r_info)) >>> + { >>> + case R_LARCH_TLS_LD_PC_HI20: >>> + rel_hi->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), >>> + R_LARCH_TLS_LD_PCREL20_S2); >>> + break; >>> + case R_LARCH_TLS_GD_PC_HI20: >>> + rel_hi->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), >>> + R_LARCH_TLS_GD_PCREL20_S2); >>> + break; >>> + case R_LARCH_TLS_DESC_PC_HI20: >>> + rel_hi->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (rel_hi->r_info), >>> + R_LARCH_TLS_DESC_PCREL20_S2); >>> + break; >>> + default: >>> + break; >>> + } >>> + rel_lo->r_info =3D ELFNN_R_INFO (0, R_LARCH_NONE); >>> + >>> + loongarch_relax_delete_bytes (abfd, sec, rel_lo->r_offset, 4, info); >>> + >>> + return true; >>> +} >>> + >>> static bool >>> loongarch_elf_relax_section (bfd *abfd, asection *sec, >>> struct bfd_link_info *info, >>> @@ -4288,15 +4377,23 @@ loongarch_elf_relax_section (bfd *abfd, asectio= n *sec, >>>=20 >>> for (unsigned int i =3D 0; i < sec->reloc_count; i++) >>> { >>> - Elf_Internal_Rela *rel =3D relocs + i; >>> - asection *sym_sec; >>> + char symtype; >>> bfd_vma symval; >>> - unsigned long r_symndx =3D ELFNN_R_SYM (rel->r_info); >>> - unsigned long r_type =3D ELFNN_R_TYPE (rel->r_info); >>> + asection *sym_sec; >>> bool local_got =3D false; >>> - char symtype; >>> + Elf_Internal_Rela *rel =3D relocs + i; >>> struct elf_link_hash_entry *h =3D NULL; >>> + unsigned long r_type =3D ELFNN_R_TYPE (rel->r_info); >>> + unsigned long r_symndx =3D ELFNN_R_SYM (rel->r_info); >>>=20 >>> + /* Four kind of relocations: >>> + Normal: symval is the symbol address. >>> + R_LARCH_ALIGN: symval is the address of the last NOP instruction >>> + added by this relocation, and then adds 4 more. >>> + R_LARCH_CALL36: symval is the symbol address for local symbols, >>> + or the PLT entry address of the symbol. (Todo) >>> + R_LARCHL_TLS_LD/GD/DESC_PC_HI20: symval is the GOT entry address >>> + of the symbol. */ >>> if (r_symndx < symtab_hdr->sh_info) >>> { >>> Elf_Internal_Sym *sym =3D (Elf_Internal_Sym *)symtab_hdr->contents >>> @@ -4304,7 +4401,24 @@ loongarch_elf_relax_section (bfd *abfd, asection= *sec, >>> if (ELF_ST_TYPE (sym->st_info) =3D=3D STT_GNU_IFUNC) >>> continue; >>>=20 >>> - if (sym->st_shndx =3D=3D SHN_UNDEF || R_LARCH_ALIGN =3D=3D r_type) >>> + if (R_LARCH_TLS_LD_PC_HI20 =3D=3D r_type >>> + || R_LARCH_TLS_GD_PC_HI20 =3D=3D r_type >>> + || R_LARCH_TLS_DESC_PC_HI20 =3D=3D r_type) >>> + { >>> + if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) >>> + continue; >>> + else >>> + { >>> + sym_sec =3D htab->elf.sgot; >>> + symval =3D elf_local_got_offsets (abfd)[r_symndx]; >>> + char tls_type =3D _bfd_loongarch_elf_tls_type (abfd, h, >>> + r_symndx); >>> + if (R_LARCH_TLS_DESC_PC_HI20 =3D=3D r_type >>> + && GOT_TLS_GD_BOTH_P (tls_type)) >>> + symval +=3D 2 * GOT_ENTRY_SIZE; >>> + } >>> + } >>> + else if (sym->st_shndx =3D=3D SHN_UNDEF || R_LARCH_ALIGN =3D=3D r_ty= pe) >>> { >>> sym_sec =3D sec; >>> symval =3D rel->r_offset; >>> @@ -4329,7 +4443,26 @@ loongarch_elf_relax_section (bfd *abfd, asection= *sec, >>> if (h !=3D NULL && h->type =3D=3D STT_GNU_IFUNC) >>> continue; >>>=20 >>> - if ((h->root.type =3D=3D bfd_link_hash_defined >>> + /* The GOT entry of tls symbols must in current execute file or >>> + shared object. */ >>> + if (R_LARCH_TLS_LD_PC_HI20 =3D=3D r_type >>> + || R_LARCH_TLS_GD_PC_HI20 =3D=3D r_type >>> + || R_LARCH_TLS_DESC_PC_HI20 =3D=3D r_type) >>> + { >>> + if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) >>> + continue; >>> + else >>> + { >>> + sym_sec =3D htab->elf.sgot; >>> + symval =3D h->got.offset; >>> + char tls_type =3D _bfd_loongarch_elf_tls_type (abfd, h, >>> + r_symndx); >>> + if (R_LARCH_TLS_DESC_PC_HI20 =3D=3D r_type >>> + && GOT_TLS_GD_BOTH_P (tls_type)) >>> + symval +=3D 2 * GOT_ENTRY_SIZE; >>> + } >>> + } >>> + else if ((h->root.type =3D=3D bfd_link_hash_defined >>> || h->root.type =3D=3D bfd_link_hash_defweak) >>> && h->root.u.def.section !=3D NULL >>> && h->root.u.def.section->output_section !=3D NULL) >>> @@ -4358,7 +4491,7 @@ loongarch_elf_relax_section (bfd *abfd, asection = *sec, >>> if (symtype !=3D STT_SECTION) >>> symval +=3D rel->r_addend; >>> } >>> - /* For R_LARCH_ALIGN, symval is sec_addr (sym_sec) + rel->r_offs= et >>> + /* For R_LARCH_ALIGN, symval is sec_addr (sec) + rel->r_offset >>> + (alingmeng - 4). >>> If r_symndx is 0, alignmeng-4 is r_addend. >>> If r_symndx > 0, alignment-4 is 2^(r_addend & 0xff)-4. */ >>> @@ -4399,6 +4532,25 @@ loongarch_elf_relax_section (bfd *abfd, asection= *sec, >>> info, again); >>> } >>> break; >>> + >>> + case R_LARCH_TLS_LD_PC_HI20: >>> + if (0 =3D=3D info->relax_pass && (i + 4) <=3D sec->reloc_count) >>> + loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, >>> + info, again); >>> + break; >>> + >>> + case R_LARCH_TLS_GD_PC_HI20: >>> + if (0 =3D=3D info->relax_pass && (i + 4) <=3D sec->reloc_count) >>> + loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, >>> + info, again); >>> + break; >>> + >>> + case R_LARCH_TLS_DESC_PC_HI20: >>> + if (0 =3D=3D info->relax_pass && (i + 4) <=3D sec->reloc_count) >>> + loongarch_relax_tls_ld_gd_desc (abfd, sec, sym_sec, rel, symval, >>> + info, again); >>> + break; >>> + >>> default: >>> break; >>> } >>> diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c >>> index 30a941a851f..310e6d62dc0 100644 >>> --- a/bfd/elfxx-loongarch.c >>> +++ b/bfd/elfxx-loongarch.c >>> @@ -1775,6 +1775,60 @@ static loongarch_reloc_howto_type loongarch_howt= o_table[] =3D >>> BFD_RELOC_LARCH_TLS_DESC_CALL, /* bfd_reloc_code_real_type. */ >>> NULL, /* adjust_reloc_bits. */ >>> "desc_call"), /* larch_reloc_type_name. */ >>>=20 >>> + >>> + /* For pcaddi, ld_pc_hi20 + ld_pc_lo12 can relax to ld_pcrel20_s2. = */ >>> + LOONGARCH_HOWTO (R_LARCH_TLS_LD_PCREL20_S2, /* type (124). */ >>> + 2, /* rightshift. */ >>> + 4, /* size. */ >>> + 20, /* bitsize. */ >>> + false, /* pc_relative. */ >>> + 5, /* bitpos. */ >>> + complain_overflow_signed, /* complain_on_overflow. */ >>> + bfd_elf_generic_reloc, /* special_function. */ >>> + "R_LARCH_TLS_LD_PCREL20_S2", /* name. */ >>> + false, /* partial_inplace. */ >>> + 0, /* src_mask. */ >>> + 0x1ffffe0, /* dst_mask. */ >>> + true, /* pcrel_offset. */ >>> + BFD_RELOC_LARCH_TLS_LD_PCREL20_S2, /* bfd_reloc_code_real_type. */ >>> + reloc_sign_bits, /* adjust_reloc_bits. */ >>> + "ld_pcrel_20"), /* larch_reloc_type_name. */ >>> + >>> + /* For pcaddi, gd_pc_hi20 + gd_pc_lo12 can relax to gd_pcrel20_s2. = */ >>> + LOONGARCH_HOWTO (R_LARCH_TLS_GD_PCREL20_S2, /* type (125). */ >>> + 2, /* rightshift. */ >>> + 4, /* size. */ >>> + 20, /* bitsize. */ >>> + false, /* pc_relative. */ >>> + 5, /* bitpos. */ >>> + complain_overflow_signed, /* complain_on_overflow. */ >>> + bfd_elf_generic_reloc, /* special_function. */ >>> + "R_LARCH_TLS_GD_PCREL20_S2", /* name. */ >>> + false, /* partial_inplace. */ >>> + 0, /* src_mask. */ >>> + 0x1ffffe0, /* dst_mask. */ >>> + true, /* pcrel_offset. */ >>> + BFD_RELOC_LARCH_TLS_GD_PCREL20_S2, /* bfd_reloc_code_real_type. */ >>> + reloc_sign_bits, /* adjust_reloc_bits. */ >>> + "gd_pcrel_20"), /* larch_reloc_type_name. */ >>> + >>> + /* For pcaddi, desc_pc_hi20 + desc_pc_lo12 can relax to desc_pcrel20= _s2. */ >>> + LOONGARCH_HOWTO (R_LARCH_TLS_DESC_PCREL20_S2, /* type (126). */ >>> + 2, /* rightshift. */ >>> + 4, /* size. */ >>> + 20, /* bitsize. */ >>> + false, /* pc_relative. */ >>> + 5, /* bitpos. */ >>> + complain_overflow_signed, /* complain_on_overflow. */ >>> + bfd_elf_generic_reloc, /* special_function. */ >>> + "R_LARCH_TLS_DESC_PCREL20_S2", /* name. */ >>> + false, /* partial_inplace. */ >>> + 0, /* src_mask. */ >>> + 0x1ffffe0, /* dst_mask. */ >>> + true, /* pcrel_offset. */ >>> + BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2, /* bfd_reloc_code_real_type. */ >>> + reloc_sign_bits, /* adjust_reloc_bits. */ >>> + "desc_pcrel_20"), /* larch_reloc_type_name. */ >>> }; >>>=20 >>>=20 >>>=20 >>> I think relaxation relocs is a concept internal to binutils and they sh= ould not be in the same number range as psABI defined relocs. Some linkers = (e.g. mold) doesn=E2=80=99t create new relocs when relaxing and rewrites th= e instruction right away, therefore these relocs would have no purpose in t= he psABI. >>>=20 >>> We recently refactored out all the linker-internal relocs to a differen= t range [1]; LoongArch might want to follow suit. >>>=20 >>> [1]: https://sourceware.org/pipermail/binutils/2023-November/130322.html >>>=20 >>>=20 >>> However, it should be noted that in handwritten assembly, these relocat= ions can be directly used. >>>=20 >>>=20 >>> Sorry for the delay in reply. I=E2=80=99m not sure if there is any use = cases to use relaxation-only relocations in assembly source. It=E2=80=99s o= ne of the reasons we did away with this in RISC-V [1]. >>>=20 >>> [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/398 >> Agreed. If a relocation type is only used for internal relaxation >> purposes, it should not be defined in the psABI and there should not >> be an assembler directive generating it (except .reloc using a >> hard-coded integer). >=20 > We have considered such a situation. For those familiar with LoongArch as= sembly, if you want to > use DESC to access "var" in assembly source, you can directly use pcaddi = $a0,%desc_pcrel_20(var) > instead of pcalau12i $a0,%desc_pc_hi20(var) and addi.d $a0, $a0,% desc_pc= _lo12(var). > The same situation applies to GD/LD. I see it now. LoongArch's =E2=80=9Cnormal code model=E2=80=9D restricts the= addressing of program code to a 256MiB address space, so being able to wri= te out the pcrel_20 variant makes perfect sense. Thanks for the clarificati= on. >>=20 >>> reloc_howto_type * >>> @@ -1783,7 +1837,9 @@ loongarch_elf_rtype_to_howto (bfd *abfd, unsigned= int r_type) >>> if(r_type < R_LARCH_count) >>> { >>> /* For search table fast. */ >>>=20 >>> + /* >>> BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) =3D=3D R_LARCH_cou= nt); >>> + */ >>>=20 >>>=20 >>>=20 >>> Was this supposed to be commented out and committed as-is? >>>=20 >>>=20 >>> It has been deleted. >>>=20 >>>=20 >>>=20 >>> if (loongarch_howto_table[r_type].howto.type =3D=3D r_type) >>> return (reloc_howto_type *)&loongarch_howto_table[r_type]; >>> @@ -1802,7 +1858,9 @@ loongarch_elf_rtype_to_howto (bfd *abfd, unsigned= int r_type) >>> reloc_howto_type * >>> loongarch_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_= name) >>> { >>> + /* >>> BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) =3D=3D R_LARCH_count); >>> + */ >>>=20 >>> for (size_t i =3D 0; i < ARRAY_SIZE (loongarch_howto_table); i++) >>> if (loongarch_howto_table[i].howto.name >>> @@ -1821,7 +1879,9 @@ reloc_howto_type * >>> loongarch_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, >>> bfd_reloc_code_real_type code) >>> { >>> + /* >>> BFD_ASSERT (ARRAY_SIZE (loongarch_howto_table) =3D=3D R_LARCH_count); >>> + */ >>>=20 >>> /* Fast search for new reloc types. */ >>> if (BFD_RELOC_LARCH_B16 <=3D code && code < BFD_RELOC_LARCH_RELAX) >>> diff --git a/bfd/libbfd.h b/bfd/libbfd.h >>> index 71b03da14d9..8dab44110a6 100644 >>> --- a/bfd/libbfd.h >>> +++ b/bfd/libbfd.h >>> @@ -3612,6 +3612,9 @@ static const char *const bfd_reloc_code_real_name= s[] =3D { "@@uninitialized@@", >>> "BFD_RELOC_LARCH_TLS_DESC64_HI12", >>> "BFD_RELOC_LARCH_TLS_DESC_LD", >>> "BFD_RELOC_LARCH_TLS_DESC_CALL", >>> + "BFD_RELOC_LARCH_TLS_LD_PCREL20_S2", >>> + "BFD_RELOC_LARCH_TLS_GD_PCREL20_S2", >>> + "BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2", >>> "@@overflow: BFD_RELOC_UNUSED@@", >>> }; >>> #endif >>> diff --git a/bfd/reloc.c b/bfd/reloc.c >>> index f7fe0c7ffe3..6fd0f1fb547 100644 >>> --- a/bfd/reloc.c >>> +++ b/bfd/reloc.c >>> @@ -8324,6 +8324,13 @@ ENUMX >>> ENUMX >>> BFD_RELOC_LARCH_TLS_DESC_CALL >>>=20 >>> +ENUMX >>> + BFD_RELOC_LARCH_TLS_LD_PCREL20_S2 >>> +ENUMX >>> + BFD_RELOC_LARCH_TLS_GD_PCREL20_S2 >>> +ENUMX >>> + BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2 >>> + >>> ENUMDOC >>> LARCH relocations. >>>=20 >>> diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c >>> index 1658025f918..def26daf634 100644 >>> --- a/gas/config/tc-loongarch.c >>> +++ b/gas/config/tc-loongarch.c >>> @@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char es= c_ch1, char esc_ch2, >>> esc_ch1, esc_ch2, bit_field, arg); >>>=20 >>> if (ip->reloc_info[0].type >=3D BFD_RELOC_LARCH_B16 >>> - && ip->reloc_info[0].type <=3D BFD_RELOC_LARCH_TLS_DESC_CALL) >>> + && ip->reloc_info[0].type <=3D BFD_RELOC_LARCH_TLS_DESC_PCREL20_= S2) >>> { >>> /* As we compact stack-relocs, it is no need for pop operation. >>> But break out until here in order to check the imm field. >>> @@ -694,7 +694,11 @@ loongarch_args_parser_can_match_arg_helper (char e= sc_ch1, char esc_ch2, >>> && (BFD_RELOC_LARCH_PCALA_HI20 =3D=3D reloc_type >>> || BFD_RELOC_LARCH_PCALA_LO12 =3D=3D reloc_type >>> || BFD_RELOC_LARCH_GOT_PC_HI20 =3D=3D reloc_type >>> - || BFD_RELOC_LARCH_GOT_PC_LO12 =3D=3D reloc_type)) >>> + || BFD_RELOC_LARCH_GOT_PC_LO12 =3D=3D reloc_type >>> + || BFD_RELOC_LARCH_TLS_LD_PC_HI20 =3D=3D reloc_type >>> + || BFD_RELOC_LARCH_TLS_GD_PC_HI20 =3D=3D reloc_type >>> + || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 =3D=3D reloc_type >>> + || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 =3D=3D reloc_type)) >>> { >>> ip->reloc_info[ip->reloc_num].type =3D BFD_RELOC_LARCH_RELAX; >>> ip->reloc_info[ip->reloc_num].value =3D const_0; >>> diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas= /loongarch/macro_op.d >>> index 32860864704..47f8f45c663 100644 >>> --- a/gas/testsuite/gas/loongarch/macro_op.d >>> +++ b/gas/testsuite/gas/loongarch/macro_op.d >>> @@ -2,70 +2,72 @@ >>> #objdump: -dr >>> #skip: loongarch32-*-* >>>=20 >>>=20 >>>=20 >>> -- >>> 2.43.0 --Apple-Mail=_4DF606EC-8DB1-4765-888C-6522C0CE9EF5--