From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11174 invoked by alias); 15 Feb 2011 02:33:40 -0000 Received: (qmail 11148 invoked by uid 22791); 15 Feb 2011 02:33:40 -0000 X-SWARE-Spam-Status: No, hits=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-iw0-f169.google.com (HELO mail-iw0-f169.google.com) (209.85.214.169) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 15 Feb 2011 02:33:34 +0000 Received: by iwc10 with SMTP id 10so5998363iwc.0 for ; Mon, 14 Feb 2011 18:33:33 -0800 (PST) Received: by 10.42.164.201 with SMTP id h9mr5949940icy.254.1297737213007; Mon, 14 Feb 2011 18:33:33 -0800 (PST) Received: from bookie.home (75-25-129-194.lightspeed.sjcpca.sbcglobal.net [75.25.129.194]) by mx.google.com with ESMTPS id 8sm3143690iba.22.2011.02.14.18.33.30 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 Feb 2011 18:33:31 -0800 (PST) Subject: Re: RFC: A new MIPS64 ABI Mime-Version: 1.0 (Apple Message framework v1082) Content-Type: text/plain; charset=us-ascii From: Matt Thomas In-Reply-To: <4D59E355.9050407@caviumnetworks.com> Date: Tue, 15 Feb 2011 02:33:00 -0000 Cc: GCC , binutils , Prasun Kapoor Content-Transfer-Encoding: quoted-printable Message-Id: References: <4D5990A4.2050308@caviumnetworks.com> <4D59E355.9050407@caviumnetworks.com> To: David Daney Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org X-SW-Source: 2011-02/txt/msg00154.txt.bz2 On Feb 14, 2011, at 6:22 PM, David Daney wrote: > On 02/14/2011 04:15 PM, Matt Thomas wrote: >>=20 >> I have to wonder if it's worth the effort. The primary problem I see >> is that this new ABI requires a 64bit kernel since faults through the >> upper 2G will go through the XTLB miss exception vector. >>=20 >=20 > Yes, that is correct. It is a 64-bit ABI, and like the existing n32 ABI = requires a 64-bit kernel. N32 doesn't require a LP64 kernel, just a 64-bit register aware kernel. Your N32-big does require a LP64 kernel.